From 2712f08898de84a9688b4a7b7752ba27e71d63ef Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Mon, 3 Dec 2012 13:56:51 +0000
Subject: x86: fdt: Create basic .dtsi file for coreboot

This contains just the minimum information for a coreboot-based board.

Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
---
 board/chromebook-x86/dts/link.dts | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)
 create mode 100644 board/chromebook-x86/dts/link.dts

(limited to 'board/chromebook-x86/dts/link.dts')

diff --git a/board/chromebook-x86/dts/link.dts b/board/chromebook-x86/dts/link.dts
new file mode 100644
index 0000000000..af60f59de7
--- /dev/null
+++ b/board/chromebook-x86/dts/link.dts
@@ -0,0 +1,24 @@
+/dts-v1/;
+
+/include/ "coreboot.dtsi"
+
+/ {
+        #address-cells = <1>;
+        #size-cells = <1>;
+	model = "Google Link";
+	compatible = "google,link", "intel,celeron-ivybridge";
+
+	config {
+	       silent_console = <0>;
+	};
+
+        gpio: gpio {};
+
+	serial {
+		reg = <0x3f8 8>;
+		clock-frequency = <115200>;
+	};
+
+        chosen { };
+        memory { device_type = "memory"; reg = <0 0>; };
+};
-- 
cgit