From 47cd00fa707af9de76408b69d3e911717dbbfab1 Mon Sep 17 00:00:00 2001
From: wdenk <wdenk>
Date: Thu, 6 Mar 2003 13:39:27 +0000
Subject: * Patches by Robert Schwebel, 06 Mar 2003:   - fix bug in BOOTP code
 (must use NetCopyIP)   - update of CSB226 port   - clear BSS segment on
 XScale   - added support for i2c_init_board() function   - update to the
 Innokom plattform

* Extend support for redundand environments for configurations where
  environment size < sector size
---
 board/csb226/memsetup.S | 32 ++++++++++++++++++--------------
 1 file changed, 18 insertions(+), 14 deletions(-)

(limited to 'board/csb226/memsetup.S')

diff --git a/board/csb226/memsetup.S b/board/csb226/memsetup.S
index d34ead4a5b..65671842aa 100644
--- a/board/csb226/memsetup.S
+++ b/board/csb226/memsetup.S
@@ -313,16 +313,22 @@ mem_init:
 	/*          documented in SDRAM data sheets. The address(es) used   */
 	/*          for this purpose must not be cacheable.                 */
 
-	ldr	r3,	=CFG_DRAM_BASE
-	str	r2,	[r3]
-	str	r2,	[r3]
-	str	r2,	[r3]
-	str	r2,	[r3]
-	str	r2,	[r3]
-	str	r2,	[r3]
-	str	r2,	[r3]
-	str	r2,	[r3]
+	/*          There should 9 writes, since the first write doesn't    */
+	/*          trigger a refresh cycle on PXA250. See Intel PXA250 and */
+	/*          PXA210 Processors Specification Update,                 */
+	/*          Jan 2003, Errata #116, page 30.                         */
+
 
+	ldr	r3,	=CFG_DRAM_BASE
+	str	r2, [r3]
+	str	r2, [r3]
+	str	r2, [r3]
+	str	r2, [r3]
+	str	r2, [r3]
+	str	r2, [r3]
+	str	r2, [r3]
+	str	r2, [r3]
+	str	r2, [r3]
 
 	/* Step 4g: Write MDCNFG with enable bits asserted                  */
 	/*          (MDCNFG:DEx set to 1).                                  */
@@ -339,7 +345,6 @@ mem_init:
 
 	/* We are finished with Intel's memory controller initialisation    */
 
-
 	/* ---------------------------------------------------------------- */
 	/* Disable (mask) all interrupts at interrupt controller            */
 	/* ---------------------------------------------------------------- */
@@ -378,10 +383,11 @@ initclks:
         str     r2,  [r1]
 
 	/* enable the 32Khz oscillator for RTC and PowerManager             */
+/*
         ldr     r1,  =OSCC
         mov     r2,  #OSCC_OON
         str     r2,  [r1]
-
+*/
 	/* NOTE:  spin here until OSCC.OOK get set, meaning the PLL         */
 	/* has settled.                                                     */
 60:
@@ -404,8 +410,7 @@ initclks:
 
 	/* FIXME */
 
-#define NODEBUG
-#ifdef NODEBUG
+#ifndef DEBUG
 	/*Disable software and data breakpoints */
 	mov	r0,#0
 	mcr	p15,0,r0,c14,c8,0  /* ibcr0 */
@@ -415,7 +420,6 @@ initclks:
 	/*Enable all debug functionality */
 	mov	r0,#0x80000000
 	mcr	p14,0,r0,c10,c0,0  /* dcsr */
-
 #endif
 
         /* ---------------------------------------------------------------- */
-- 
cgit