From d1c3b27525b664e8c4db6bb173eed51bfc8220de Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 9 Sep 2009 16:25:29 +0200 Subject: ppc4xx: Big cleanup of PPC4xx defines This patch cleans up multiple issues of the 4xx register (mostly DCR, SDR, CPR, etc) definitions: - Change lower case defines to upper case (plb4_acr -> PLB4_ACR) - Change the defines to better match the names from the user's manuals (e.g. cprpllc -> CPR0_PLLC) - Removal of some unused defines Please test this patch intensive on your PPC4xx platform. Even though I tried not to break anything and tested successfully on multiple 4xx AMCC platforms, testing on custom platforms is recommended. Signed-off-by: Stefan Roese --- board/esd/du405/du405.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'board/esd/du405/du405.c') diff --git a/board/esd/du405/du405.c b/board/esd/du405/du405.c index 8e9ac28b18..28a50c7b0e 100644 --- a/board/esd/du405/du405.c +++ b/board/esd/du405/du405.c @@ -135,7 +135,7 @@ int board_early_init_f (void) /* * EBC Configuration Register: set ready timeout to 100 us */ - mtebc (epcr, 0xb8400000); + mtebc (EBC0_CFG, 0xb8400000); return 0; } @@ -143,13 +143,13 @@ int board_early_init_f (void) int misc_init_r (void) { - unsigned long cntrl0Reg; + unsigned long CPC0_CR0Reg; /* * Setup UART1 handshaking: use CTS instead of DSR */ - cntrl0Reg = mfdcr(cntrl0); - mtdcr(cntrl0, cntrl0Reg | 0x00001000); + CPC0_CR0Reg = mfdcr(CPC0_CR0); + mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00001000); return (0); } -- cgit From 952e7760bfc5b0e3b142b9ce34e7fbb7d008c900 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Thu, 24 Sep 2009 09:55:50 +0200 Subject: ppc4xx: Convert PPC4xx UIC defines from lower case to upper case The latest PPC4xx register cleanup patch missed the UIC defines. This patch now changes lower case UIC defines to upper case. Signed-off-by: Stefan Roese --- board/esd/du405/du405.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) (limited to 'board/esd/du405/du405.c') diff --git a/board/esd/du405/du405.c b/board/esd/du405/du405.c index 28a50c7b0e..f475d11072 100644 --- a/board/esd/du405/du405.c +++ b/board/esd/du405/du405.c @@ -124,13 +124,13 @@ int board_early_init_f (void) * IRQ 30 (EXT IRQ 5) unused; active low; level sensitive * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive */ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr (uicer, 0x00000000); /* disable all ints */ - mtdcr (uiccr, 0x00000000); /* set all to be non-critical */ - mtdcr (uicpr, 0xFFFFFFB1); /* set int polarities */ - mtdcr (uictr, 0x10000000); /* set int trigger levels */ - mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr (UIC0ER, 0x00000000); /* disable all ints */ + mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */ + mtdcr (UIC0PR, 0xFFFFFFB1); /* set int polarities */ + mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */ + mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */ + mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ /* * EBC Configuration Register: set ready timeout to 100 us -- cgit