From 2146cf56821c3364786ca94a7306008c5824b238 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 19 Dec 2007 01:18:15 -0600 Subject: Reworked FSL Book-E TLB macros to be more readable The old macros made it difficult to know what WIMGE and perm bits were set for a TLB entry. Actually use the bit masks for these items since they are only a single bit. Also moved the macros into mmu.h out of e500.h since they aren't specific to e500. Signed-off-by: Kumar Gala --- board/freescale/mpc8541cds/init.S | 124 +++++++++++++++++--------------------- 1 file changed, 56 insertions(+), 68 deletions(-) (limited to 'board/freescale/mpc8541cds') diff --git a/board/freescale/mpc8541cds/init.S b/board/freescale/mpc8541cds/init.S index 978bda5e4d..8c8c087c4a 100644 --- a/board/freescale/mpc8541cds/init.S +++ b/board/freescale/mpc8541cds/init.S @@ -42,7 +42,7 @@ * * MAS0: tlbsel, esel, nv * MAS1: valid, iprot, tid, ts, tsize - * MAS2: epn, sharen, x0, x1, w, i, m, g, e + * MAS2: epn, x0, x1, w, i, m, g, e * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr */ @@ -74,10 +74,10 @@ tlb1_entry: * This ends up at a TLB0 Index==0 entry, and must not collide * with other TLB0 Entries. */ - .long TLB1_MAS0(0, 0, 0) - .long TLB1_MAS1(1, 0, 0, 0, 0) - .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1) + .long FSL_BOOKE_MAS0(0, 0, 0) + .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) + .long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT, (MAS2_I|MAS2_G)) + .long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) #else #error("Update the number of table entries in tlb1_entry") #endif @@ -93,33 +93,25 @@ tlb1_entry: * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c, * and must not collide with other TLB0 entries. */ - .long TLB1_MAS0(0, 0, 0) - .long TLB1_MAS1(1, 0, 0, 0, 0) - .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR), - 0,0,0,0,0,0,0,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR), - 0,0,0,0,0,1,0,1,0,1) - - .long TLB1_MAS0(0, 0, 0) - .long TLB1_MAS1(1, 0, 0, 0, 0) - .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024), - 0,0,0,0,0,0,0,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024), - 0,0,0,0,0,1,0,1,0,1) - - .long TLB1_MAS0(0, 0, 0) - .long TLB1_MAS1(1, 0, 0, 0, 0) - .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024), - 0,0,0,0,0,0,0,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024), - 0,0,0,0,0,1,0,1,0,1) - - .long TLB1_MAS0(0, 0, 0) - .long TLB1_MAS1(1, 0, 0, 0, 0) - .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024), - 0,0,0,0,0,0,0,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024), - 0,0,0,0,0,1,0,1,0,1) + .long FSL_BOOKE_MAS0(0, 0, 0) + .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) + .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, 0) + .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) + + .long FSL_BOOKE_MAS0(0, 0, 0) + .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) + .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 4 * 1024, 0) + .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 4 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) + + .long FSL_BOOKE_MAS0(0, 0, 0) + .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) + .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 8 * 1024, 0) + .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 8 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) + + .long FSL_BOOKE_MAS0(0, 0, 0) + .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) + .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 12 * 1024, 0) + .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 12 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) /* @@ -127,50 +119,46 @@ tlb1_entry: * 0xff000000 16M FLASH * Out of reset this entry is only 4K. */ - .long TLB1_MAS0(1, 0, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1) + .long FSL_BOOKE_MAS0(1, 0, 0) + .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M) + .long FSL_BOOKE_MAS2(CFG_FLASH_BASE, (MAS2_I|MAS2_G)) + .long FSL_BOOKE_MAS3(CFG_FLASH_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) /* * TLB 1: 256M Non-cacheable, guarded * 0x80000000 256M PCI1 MEM First half */ - .long TLB1_MAS0(1, 1, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1) + .long FSL_BOOKE_MAS0(1, 1, 0) + .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE, (MAS2_I|MAS2_G)) + .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) /* * TLB 2: 256M Non-cacheable, guarded * 0x90000000 256M PCI1 MEM Second half */ - .long TLB1_MAS0(1, 2, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000), - 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000), - 0,0,0,0,0,1,0,1,0,1) + .long FSL_BOOKE_MAS0(1, 2, 0) + .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G)) + .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) /* * TLB 3: 256M Non-cacheable, guarded * 0xa0000000 256M PCI2 MEM First half */ - .long TLB1_MAS0(1, 3, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI2_MEM_BASE), 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI2_MEM_BASE), 0,0,0,0,0,1,0,1,0,1) + .long FSL_BOOKE_MAS0(1, 3, 0) + .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long FSL_BOOKE_MAS2(CFG_PCI2_MEM_BASE, (MAS2_I|MAS2_G)) + .long FSL_BOOKE_MAS3(CFG_PCI2_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) /* * TLB 4: 256M Non-cacheable, guarded * 0xb0000000 256M PCI2 MEM Second half */ - .long TLB1_MAS0(1, 4, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI2_MEM_BASE + 0x10000000), - 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI2_MEM_BASE + 0x10000000), - 0,0,0,0,0,1,0,1,0,1) + .long FSL_BOOKE_MAS0(1, 4, 0) + .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long FSL_BOOKE_MAS2(CFG_PCI2_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G)) + .long FSL_BOOKE_MAS3(CFG_PCI2_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) /* * TLB 5: 64M Non-cacheable, guarded @@ -178,28 +166,28 @@ tlb1_entry: * 0xe200_0000 16M PCI1 IO * 0xe300_0000 16M PCI2 IO */ - .long TLB1_MAS0(1, 5, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1) + .long FSL_BOOKE_MAS0(1, 5, 0) + .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) + .long FSL_BOOKE_MAS2(CFG_CCSRBAR, (MAS2_I|MAS2_G)) + .long FSL_BOOKE_MAS3(CFG_CCSRBAR, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) /* * TLB 6: 64M Cacheable, non-guarded * 0xf000_0000 64M LBC SDRAM */ - .long TLB1_MAS0(1, 6, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) - .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0) - .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1) + .long FSL_BOOKE_MAS0(1, 6, 0) + .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) + .long FSL_BOOKE_MAS2(CFG_LBC_SDRAM_BASE, 0) + .long FSL_BOOKE_MAS3(CFG_LBC_SDRAM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) /* * TLB 7: 1M Non-cacheable, guarded * 0xf8000000 1M CADMUS registers */ - .long TLB1_MAS0(1, 7, 0) - .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M) - .long TLB1_MAS2(E500_TLB_EPN(CADMUS_BASE_ADDR), 0,0,0,0,1,0,1,0) - .long TLB1_MAS3(E500_TLB_RPN(CADMUS_BASE_ADDR), 0,0,0,0,0,1,0,1,0,1) + .long FSL_BOOKE_MAS0(1, 7, 0) + .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M) + .long FSL_BOOKE_MAS2(CADMUS_BASE_ADDR, (MAS2_I|MAS2_G)) + .long FSL_BOOKE_MAS3(CADMUS_BASE_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) entry_end -- cgit