From 765547dc5e0e8cbe6b8f4ea8a5d6ff237935c352 Mon Sep 17 00:00:00 2001
From: Haiying Wang <Haiying.Wang@freescale.com>
Date: Fri, 27 Mar 2009 17:02:45 -0400
Subject: MPC85xx: Add MPC8569MDS board support

This patch adds MPC8569MDS board support. The UART, QE UEC1 and UEC2, BRD
EEPROM on I2C2 bus, PCI express and DDR3 SPD are supported in this patch.

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Hillel Avni <Hillel.Avni@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
 board/freescale/mpc8569mds/ddr.c | 84 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 84 insertions(+)
 create mode 100644 board/freescale/mpc8569mds/ddr.c

(limited to 'board/freescale/mpc8569mds/ddr.c')

diff --git a/board/freescale/mpc8569mds/ddr.c b/board/freescale/mpc8569mds/ddr.c
new file mode 100644
index 0000000000..4b4533eb50
--- /dev/null
+++ b/board/freescale/mpc8569mds/ddr.c
@@ -0,0 +1,84 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <i2c.h>
+
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
+
+static void
+get_spd(ddr3_spd_eeprom_t *spd, unsigned char i2c_address)
+{
+	i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr3_spd_eeprom_t));
+}
+
+
+unsigned int fsl_ddr_get_mem_data_rate(void)
+{
+	return get_ddr_freq(0);
+}
+
+void fsl_ddr_get_spd(ddr3_spd_eeprom_t *ctrl_dimms_spd,
+		      unsigned int ctrl_num)
+{
+	unsigned int i;
+	unsigned int i2c_address = 0;
+
+	for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
+		if (ctrl_num == 0 && i == 0)
+			i2c_address = SPD_EEPROM_ADDRESS1;
+		if (ctrl_num == 0 && i == 1)
+			i2c_address = SPD_EEPROM_ADDRESS2;
+		get_spd(&(ctrl_dimms_spd[i]), i2c_address);
+	}
+}
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+				dimm_params_t *pdimm,
+				unsigned int ctrl_num)
+{
+	/*
+	 * Factors to consider for clock adjust:
+	 *	- number of chips on bus
+	 *	- position of slot
+	 *	- DDR1 vs. DDR2?
+	 *	- ???
+	 *
+	 * This needs to be determined on a board-by-board basis.
+	 *	0110	3/4 cycle late
+	 *	0111	7/8 cycle late
+	 */
+	popts->clk_adjust = 6;
+
+	/*
+	 * Factors to consider for CPO:
+	 *	- frequency
+	 *	- ddr1 vs. ddr2
+	 */
+	popts->cpo_override = 0xff;
+
+	/*
+	 * Factors to consider for write data delay:
+	 *	- number of DIMMs
+	 *
+	 * 1 = 1/4 clock delay
+	 * 2 = 1/2 clock delay
+	 * 3 = 3/4 clock delay
+	 * 4 = 1   clock delay
+	 * 5 = 5/4 clock delay
+	 * 6 = 3/2 clock delay
+	 */
+	popts->write_data_delay = 2;
+
+	/*
+	 * Factors to consider for half-strength driver enable:
+	 *	- number of DIMMs installed
+	 */
+	popts->half_strength_driver_enable = 0;
+}
-- 
cgit