From f45210d6e7aa600fa0fa96eb67afb37567fd4cce Mon Sep 17 00:00:00 2001 From: Matthew McClintock Date: Mon, 18 Feb 2013 10:02:19 +0000 Subject: powerpc/p1022ds: Add support for NAND and NAND boot using SPL Add defines needed to access NAND, remove second flash bank that is actually connected to NAND. Add nand booting support for P1022DS with hardcoded DDR config using SPL framework from 2011 Signed-off-by: Matthew McClintock Signed-off-by: Jerry Huang Signed-off-by: Jiang Yutang Signed-off-by: Kumar Gala Signed-off-by: Andy Fleming --- board/freescale/p1022ds/tlb.c | 20 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) (limited to 'board/freescale/p1022ds/tlb.c') diff --git a/board/freescale/p1022ds/tlb.c b/board/freescale/p1022ds/tlb.c index 71e71f7070..3acc44912d 100644 --- a/board/freescale/p1022ds/tlb.c +++ b/board/freescale/p1022ds/tlb.c @@ -41,6 +41,7 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 1, BOOKE_PAGESZ_1M, 1), +#ifndef CONFIG_SPL_BUILD /* W**G* - Flash/promjet, localbus */ /* This will be changed to *I*G* after relocation to RAM. */ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, @@ -67,24 +68,31 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 6, BOOKE_PAGESZ_256K, 1), +#endif SET_TLB_ENTRY(1, PIXIS_BASE, PIXIS_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 7, BOOKE_PAGESZ_4K, 1), -#ifdef CONFIG_SYS_RAMBOOT - /* *I*G - eSDHC/eSPI/NAND boot */ +#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL) + /* **** - eSDHC/eSPI/NAND boot */ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 8, BOOKE_PAGESZ_1G, 1), - - /* map the second 1G */ + /* **** - eSDHC/eSPI/NAND boot - second 1GB of memory */ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 9, BOOKE_PAGESZ_1G, 1), #endif -# + +#ifdef CONFIG_SYS_NAND_BASE + /* *I*G - NAND */ + SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 10, BOOKE_PAGESZ_16K, 1), +#endif + }; int num_tlb_entries = ARRAY_SIZE(tlb_table); -- cgit