From 316f0d0f8f3cbeeefda043e69f3e4e6aa57f7f1d Mon Sep 17 00:00:00 2001 From: York Sun Date: Tue, 5 Dec 2017 10:57:54 -0800 Subject: powerpc: mpc85xx: Fix static TLB table for SDRAM Most predefined TLB tables don't have memory coherence bit set for SDRAM. This wasn't an issue before invalidate_dcache_range() function was enabled. Without the coherence bit, dcache invalidation doesn't automatically flush the cache. The coherence bit is already set when dynamic TLB table is used. For some boards with different SPL boot method, or with legacy fixed setting, this bit needs to be set in TLB files. Signed-off-by: York Sun --- board/freescale/t4qds/tlb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'board/freescale/t4qds/tlb.c') diff --git a/board/freescale/t4qds/tlb.c b/board/freescale/t4qds/tlb.c index 1e4d096f5f..a6d8bb3603 100644 --- a/board/freescale/t4qds/tlb.c +++ b/board/freescale/t4qds/tlb.c @@ -139,7 +139,7 @@ struct fsl_e_tlb_entry tlb_table[] = { #if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD) SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, 0, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, 0, 19, BOOKE_PAGESZ_2G, 1) #endif }; -- cgit