From d3bee08332fbc9cc5b6dc22ecd34050a85d44d0a Mon Sep 17 00:00:00 2001 From: Poonam Aggrwal Date: Wed, 23 Jun 2010 19:32:28 +0530 Subject: 85xx/p1_p2_rdb: Modify the CLK_CTRL value for DDR at 667MHz Use a slighly larger value of CLK_CTRL for DDR at 667MHz which fixes random crashes while linux booting. Applicable for both NAND and NOR boot. Signed-off-by: Sandeep Gopalpet Signed-off-by: Poonam Aggrwal Acked-by: Andy Fleming --- board/freescale/p1_p2_rdb/ddr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'board/freescale') diff --git a/board/freescale/p1_p2_rdb/ddr.c b/board/freescale/p1_p2_rdb/ddr.c index fccc4f8f58..15b46b0da1 100644 --- a/board/freescale/p1_p2_rdb/ddr.c +++ b/board/freescale/p1_p2_rdb/ddr.c @@ -76,7 +76,7 @@ extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, #define CONFIG_SYS_DDR_TIMING_0_667 0x55770802 #define CONFIG_SYS_DDR_TIMING_1_667 0x5f599543 #define CONFIG_SYS_DDR_TIMING_2_667 0x0fa074d1 -#define CONFIG_SYS_DDR_CLK_CTRL_667 0x02800000 +#define CONFIG_SYS_DDR_CLK_CTRL_667 0x03000000 #define CONFIG_SYS_DDR_MODE_1_667 0x00040852 #define CONFIG_SYS_DDR_MODE_2_667 0x00000000 #define CONFIG_SYS_DDR_INTERVAL_667 0x0a280100 -- cgit From 75997dc54f4ddbc4e9ed5dcebbe79951aa7128d1 Mon Sep 17 00:00:00 2001 From: Poonam Aggrwal Date: Tue, 22 Jun 2010 12:50:46 +0530 Subject: 85xx/p1_p2_rdb: Added RevD board version support - Also modified the code to use io accessors. Signed-off-by: Poonam Aggrwal Signed-off-by: Dipen Dudhat Acked-by: Kumar Gala --- board/freescale/p1_p2_rdb/p1_p2_rdb.c | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) (limited to 'board/freescale') diff --git a/board/freescale/p1_p2_rdb/p1_p2_rdb.c b/board/freescale/p1_p2_rdb/p1_p2_rdb.c index 31cdf9ae4c..fae31f28c0 100644 --- a/board/freescale/p1_p2_rdb/p1_p2_rdb.c +++ b/board/freescale/p1_p2_rdb/p1_p2_rdb.c @@ -54,6 +54,7 @@ DECLARE_GLOBAL_DATA_PTR; #define BOARDREV_MASK 0x10100000 #define BOARDREV_B 0x10100000 #define BOARDREV_C 0x00100000 +#define BOARDREV_D 0x00000000 #define SYSCLK_66 66666666 #define SYSCLK_50 50000000 @@ -64,7 +65,7 @@ unsigned long get_board_sys_clk(ulong dummy) volatile ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); u32 val_gpdat, sysclk_gpio, board_rev_gpio; - val_gpdat = pgpio->gpdat; + val_gpdat = in_be32(&pgpio->gpdat); sysclk_gpio = val_gpdat & SYSCLK_MASK; board_rev_gpio = val_gpdat & BOARDREV_MASK; if (board_rev_gpio == BOARDREV_C) { @@ -77,6 +78,11 @@ unsigned long get_board_sys_clk(ulong dummy) return SYSCLK_66; else return SYSCLK_50; + } else if (board_rev_gpio == BOARDREV_D) { + if(sysclk_gpio == 0) + return SYSCLK_66; + else + return SYSCLK_100; } return 0; } @@ -100,12 +106,14 @@ int checkboard (void) char board_rev = 0; struct cpu_type *cpu; - val_gpdat = pgpio->gpdat; + val_gpdat = in_be32(&pgpio->gpdat); board_rev_gpio = val_gpdat & BOARDREV_MASK; if (board_rev_gpio == BOARDREV_C) board_rev = 'C'; else if (board_rev_gpio == BOARDREV_B) board_rev = 'B'; + else if (board_rev_gpio == BOARDREV_D) + board_rev = 'D'; else panic ("Unexpected Board REV %x detected!!\n", board_rev_gpio); @@ -159,6 +167,7 @@ int board_eth_init(bd_t *bis) volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); int num = 0; char *tmp; + u32 pordevsr; unsigned int vscfw_addr; #ifdef CONFIG_TSEC1 @@ -171,7 +180,8 @@ int board_eth_init(bd_t *bis) #endif #ifdef CONFIG_TSEC3 SET_STD_TSEC_INFO(tsec_info[num], 3); - if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS)) + pordevsr = in_be32(&gur->pordevsr); + if (!(pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS)) tsec_info[num].flags |= TSEC_SGMII; num++; #endif -- cgit