From 1d293e6804fe077853636b0517ef00609299936e Mon Sep 17 00:00:00 2001
From: Peng Fan <peng.fan@nxp.com>
Date: Thu, 8 Aug 2019 09:55:57 +0000
Subject: imx: add i.MX6ULZ board

Add i.MX6ULZ board support. the i.MX6ULZ is SW compatible
with i.MX6ULL. so most code of i.MX6ULL can be reused
by i.MX6ULZ.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
---
 board/freescale/mx6ullevk/MAINTAINERS |  1 +
 board/freescale/mx6ullevk/mx6ullevk.c | 10 ++++++++--
 2 files changed, 9 insertions(+), 2 deletions(-)

(limited to 'board/freescale')

diff --git a/board/freescale/mx6ullevk/MAINTAINERS b/board/freescale/mx6ullevk/MAINTAINERS
index 73031cd121..3d1b256036 100644
--- a/board/freescale/mx6ullevk/MAINTAINERS
+++ b/board/freescale/mx6ullevk/MAINTAINERS
@@ -5,3 +5,4 @@ F:	board/freescale/mx6ullevk/
 F:	include/configs/mx6ullevk.h
 F:	configs/mx6ull_14x14_evk_defconfig
 F:	configs/mx6ull_14x14_evk_plugin_defconfig
+F:	configs/mx6ulz_14x14_evk_defconfig
diff --git a/board/freescale/mx6ullevk/mx6ullevk.c b/board/freescale/mx6ullevk/mx6ullevk.c
index e119347802..20ae011eca 100644
--- a/board/freescale/mx6ullevk/mx6ullevk.c
+++ b/board/freescale/mx6ullevk/mx6ullevk.c
@@ -84,7 +84,10 @@ int board_late_init(void)
 #endif
 
 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
-	env_set("board_name", "EVK");
+	if (is_cpu_type(MXC_CPU_MX6ULZ))
+		env_set("board_name", "ULZ-EVK");
+	else
+		env_set("board_name", "EVK");
 	env_set("board_rev", "14X14");
 #endif
 
@@ -93,7 +96,10 @@ int board_late_init(void)
 
 int checkboard(void)
 {
-	puts("Board: MX6ULL 14x14 EVK\n");
+	if (is_cpu_type(MXC_CPU_MX6ULZ))
+		puts("Board: MX6ULZ 14x14 EVK\n");
+	else
+		puts("Board: MX6ULL 14x14 EVK\n");
 
 	return 0;
 }
-- 
cgit 


From 8a6e1b1dda2a95cc0b675b704faf2188681e363a Mon Sep 17 00:00:00 2001
From: Peng Fan <peng.fan@nxp.com>
Date: Thu, 1 Aug 2019 06:02:41 +0000
Subject: imx: mx6ul_14x14_evk: Fix SPL boot

When booting SPL on the board, met boot failure:
"
Trying to boot from MMC2
MMC Device 1 not found
spl: could not find mmc device 1. error: -19
SPL: failed to boot from all boot devices
"

Let's register the two mmc controllers in SPL stage to
avoid boot failure.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
---
 board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c | 16 ----------------
 1 file changed, 16 deletions(-)

(limited to 'board/freescale')

diff --git a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
index ccbe404478..32f3912751 100644
--- a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
+++ b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
@@ -111,7 +111,6 @@ static iomux_v3_cfg_t const uart1_pads[] = {
 	MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
 };
 
-#ifndef CONFIG_SPL_BUILD
 static iomux_v3_cfg_t const usdhc1_pads[] = {
 	MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
@@ -127,7 +126,6 @@ static iomux_v3_cfg_t const usdhc1_pads[] = {
 	/* RST_B */
 	MX6_PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
 };
-#endif
 
 /*
  * mx6ul_14x14_evk board default supports sd card. If want to use
@@ -238,19 +236,6 @@ int board_mmc_getcd(struct mmc *mmc)
 
 int board_mmc_init(bd_t *bis)
 {
-#ifdef CONFIG_SPL_BUILD
-#if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK)
-	imx_iomux_v3_setup_multiple_pads(usdhc2_emmc_pads,
-					 ARRAY_SIZE(usdhc2_emmc_pads));
-#else
-	imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
-#endif
-	gpio_direction_output(USDHC2_PWR_GPIO, 0);
-	udelay(500);
-	gpio_direction_output(USDHC2_PWR_GPIO, 1);
-	usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
-	return fsl_esdhc_initialize(bis, &usdhc_cfg[1]);
-#else
 	int i, ret;
 
 	/*
@@ -297,7 +282,6 @@ int board_mmc_init(bd_t *bis)
 				return ret;
 			}
 	}
-#endif
 	return 0;
 }
 #endif
-- 
cgit 


From ae0760584b386230c2c7a0fc0b29fee2627bda14 Mon Sep 17 00:00:00 2001
From: Peng Fan <peng.fan@nxp.com>
Date: Thu, 1 Aug 2019 06:02:49 +0000
Subject: imx: mx6ul_14x14_evk: convert to DM_VIDEO

To support DM_VIDEO,
 Add display node for lcdif
 Drop board iomuxc settings.
 Enable DM_VIDEO

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
---
 board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c | 57 ++++++++---------------
 1 file changed, 20 insertions(+), 37 deletions(-)

(limited to 'board/freescale')

diff --git a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
index 32f3912751..8e5f365d35 100644
--- a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
+++ b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
@@ -28,6 +28,10 @@
 #include "../common/pfuze.h"
 #include <usb.h>
 #include <usb/ehci-ci.h>
+#ifdef CONFIG_DM_VIDEO
+#include <bmp_logo_data.h>
+#include <video.h>
+#endif
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -421,40 +425,8 @@ int board_phy_config(struct phy_device *phydev)
 }
 #endif
 
-#ifdef CONFIG_VIDEO_MXS
+#ifdef CONFIG_DM_VIDEO
 static iomux_v3_cfg_t const lcd_pads[] = {
-	MX6_PAD_LCD_CLK__LCDIF_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
-	MX6_PAD_LCD_ENABLE__LCDIF_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),
-	MX6_PAD_LCD_HSYNC__LCDIF_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
-	MX6_PAD_LCD_VSYNC__LCDIF_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
-	MX6_PAD_LCD_DATA00__LCDIF_DATA00 | MUX_PAD_CTRL(LCD_PAD_CTRL),
-	MX6_PAD_LCD_DATA01__LCDIF_DATA01 | MUX_PAD_CTRL(LCD_PAD_CTRL),
-	MX6_PAD_LCD_DATA02__LCDIF_DATA02 | MUX_PAD_CTRL(LCD_PAD_CTRL),
-	MX6_PAD_LCD_DATA03__LCDIF_DATA03 | MUX_PAD_CTRL(LCD_PAD_CTRL),
-	MX6_PAD_LCD_DATA04__LCDIF_DATA04 | MUX_PAD_CTRL(LCD_PAD_CTRL),
-	MX6_PAD_LCD_DATA05__LCDIF_DATA05 | MUX_PAD_CTRL(LCD_PAD_CTRL),
-	MX6_PAD_LCD_DATA06__LCDIF_DATA06 | MUX_PAD_CTRL(LCD_PAD_CTRL),
-	MX6_PAD_LCD_DATA07__LCDIF_DATA07 | MUX_PAD_CTRL(LCD_PAD_CTRL),
-	MX6_PAD_LCD_DATA08__LCDIF_DATA08 | MUX_PAD_CTRL(LCD_PAD_CTRL),
-	MX6_PAD_LCD_DATA09__LCDIF_DATA09 | MUX_PAD_CTRL(LCD_PAD_CTRL),
-	MX6_PAD_LCD_DATA10__LCDIF_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
-	MX6_PAD_LCD_DATA11__LCDIF_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
-	MX6_PAD_LCD_DATA12__LCDIF_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
-	MX6_PAD_LCD_DATA13__LCDIF_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
-	MX6_PAD_LCD_DATA14__LCDIF_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
-	MX6_PAD_LCD_DATA15__LCDIF_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
-	MX6_PAD_LCD_DATA16__LCDIF_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
-	MX6_PAD_LCD_DATA17__LCDIF_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
-	MX6_PAD_LCD_DATA18__LCDIF_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL),
-	MX6_PAD_LCD_DATA19__LCDIF_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL),
-	MX6_PAD_LCD_DATA20__LCDIF_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL),
-	MX6_PAD_LCD_DATA21__LCDIF_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL),
-	MX6_PAD_LCD_DATA22__LCDIF_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL),
-	MX6_PAD_LCD_DATA23__LCDIF_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL),
-
-	/* LCD_RST */
-	MX6_PAD_SNVS_TAMPER9__GPIO5_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
-
 	/* Use GPIO for Brightness adjustment, duty cycle = period. */
 	MX6_PAD_GPIO1_IO08__GPIO1_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),
 };
@@ -505,10 +477,6 @@ int board_init(void)
 	board_qspi_init();
 #endif
 
-#ifdef CONFIG_VIDEO_MXS
-	setup_lcd();
-#endif
-
 	return 0;
 }
 
@@ -537,6 +505,21 @@ int board_late_init(void)
 		env_set("board_rev", "14X14");
 #endif
 
+#if defined(CONFIG_DM_VIDEO)
+	struct udevice *dev;
+	int ret;
+
+	ret = uclass_get_device(UCLASS_VIDEO, 0, &dev);
+	if (ret)
+		return ret;
+
+	setup_lcd();
+
+	ret = video_bmp_display(dev, (ulong)bmp_logo_bitmap, 0, 0, true);
+	if (ret)
+		return ret;
+#endif
+
 	return 0;
 }
 
-- 
cgit 


From bdcac955657b46d78f375f74bf5e7e9b29f726c2 Mon Sep 17 00:00:00 2001
From: Peng Fan <peng.fan@nxp.com>
Date: Wed, 31 Jul 2019 08:30:02 +0000
Subject: imx: mx6slevk: enable DM_SPI and DM_SPI_FLASH

With DM_SPI and DM_SPI_FLASH enabled, we could get:

spi          0  [   ]   mxc_spi               |   |   |   `-- ecspi@02008000
spi_flash    0  [   ]   spi_flash_std         |   |   |       `-- m25p80@0

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 board/freescale/mx6slevk/mx6slevk.c | 28 ----------------------------
 1 file changed, 28 deletions(-)

(limited to 'board/freescale')

diff --git a/board/freescale/mx6slevk/mx6slevk.c b/board/freescale/mx6slevk/mx6slevk.c
index 4c48679037..33ae91c307 100644
--- a/board/freescale/mx6slevk/mx6slevk.c
+++ b/board/freescale/mx6slevk/mx6slevk.c
@@ -15,7 +15,6 @@
 #include <asm/gpio.h>
 #include <asm/mach-imx/iomux-v3.h>
 #include <asm/mach-imx/mxc_i2c.h>
-#include <asm/mach-imx/spi.h>
 #include <asm/io.h>
 #include <linux/sizes.h>
 #include <common.h>
@@ -41,9 +40,6 @@ DECLARE_GLOBAL_DATA_PTR;
 	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED   |             \
 	PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
 
-#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
-		      PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
-
 #define OTGID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |		\
 			PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW |\
 			PAD_CTL_DSE_80ohm | PAD_CTL_HYS |	\
@@ -120,25 +116,6 @@ static iomux_v3_cfg_t const fec_pads[] = {
 	MX6_PAD_FEC_TX_CLK__GPIO_4_21 | MUX_PAD_CTRL(NO_PAD_CTRL),
 };
 
-#ifdef CONFIG_MXC_SPI
-static iomux_v3_cfg_t ecspi1_pads[] = {
-	MX6_PAD_ECSPI1_MISO__ECSPI_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
-	MX6_PAD_ECSPI1_MOSI__ECSPI_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
-	MX6_PAD_ECSPI1_SCLK__ECSPI_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
-	MX6_PAD_ECSPI1_SS0__GPIO4_IO11  | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-int board_spi_cs_gpio(unsigned bus, unsigned cs)
-{
-	return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 11)) : -1;
-}
-
-static void setup_spi(void)
-{
-	imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
-}
-#endif
-
 static void setup_iomux_uart(void)
 {
 	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
@@ -232,11 +209,6 @@ int board_init(void)
 	/* address of boot parameters */
 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 
-#ifdef CONFIG_MXC_SPI
-	gpio_request(IMX_GPIO_NR(4, 11), "spi_cs");
-	setup_spi();
-#endif
-
 #ifdef	CONFIG_FEC_MXC
 	setup_fec();
 #endif
-- 
cgit 


From bd1cc6ae6f8a8f2c1c44263e3a89f853c237306e Mon Sep 17 00:00:00 2001
From: Peng Fan <peng.fan@nxp.com>
Date: Mon, 22 Jul 2019 01:24:39 +0000
Subject: i.MX7ULP: evk: Modify FDT file to disable SD3.0 for usb boot

Since the SD3.0 kernel driver needs M4 image support, this causes
problem for usb boot booting into kernel.  To decouple the relationship,
we modify the FDT file in u-boot to disable SD3.0.
So the kernel won't depend on M4 image.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 board/freescale/mx7ulp_evk/mx7ulp_evk.c | 47 +++++++++++++++++++++++++++++++++
 1 file changed, 47 insertions(+)

(limited to 'board/freescale')

diff --git a/board/freescale/mx7ulp_evk/mx7ulp_evk.c b/board/freescale/mx7ulp_evk/mx7ulp_evk.c
index 3a12fe1551..7527263577 100644
--- a/board/freescale/mx7ulp_evk/mx7ulp_evk.c
+++ b/board/freescale/mx7ulp_evk/mx7ulp_evk.c
@@ -4,10 +4,12 @@
  */
 
 #include <common.h>
+#include <fdt_support.h>
 #include <asm/io.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/mx7ulp-pins.h>
 #include <asm/arch/iomux.h>
+#include <asm/mach-imx/boot_mode.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -45,3 +47,48 @@ int board_init(void)
 
 	return 0;
 }
+
+#if IS_ENABLED(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+	const char *path;
+	int rc, nodeoff;
+
+	if (get_boot_device() == USB_BOOT) {
+		path = fdt_get_alias(blob, "mmc0");
+		if (!path) {
+			puts("Not found mmc0\n");
+			return 0;
+		}
+
+		nodeoff = fdt_path_offset(blob, path);
+		if (nodeoff < 0)
+			return 0;
+
+		printf("Found usdhc0 node\n");
+		if (fdt_get_property(blob, nodeoff, "vqmmc-supply",
+		    NULL) != NULL) {
+			rc = fdt_delprop(blob, nodeoff, "vqmmc-supply");
+			if (!rc) {
+				puts("Removed vqmmc-supply property\n");
+add:
+				rc = fdt_setprop(blob, nodeoff,
+						 "no-1-8-v", NULL, 0);
+				if (rc == -FDT_ERR_NOSPACE) {
+					rc = fdt_increase_size(blob, 32);
+					if (!rc)
+						goto add;
+				} else if (rc) {
+					printf("Failed to add no-1-8-v property, %d\n", rc);
+				} else {
+					puts("Added no-1-8-v property\n");
+				}
+			} else {
+				printf("Failed to remove vqmmc-supply property, %d\n", rc);
+			}
+		}
+	}
+
+	return 0;
+}
+#endif
-- 
cgit 


From b152584283088b79b967f361e673c744d3ef325b Mon Sep 17 00:00:00 2001
From: Peng Fan <peng.fan@nxp.com>
Date: Wed, 21 Aug 2019 08:28:15 +0000
Subject: imx: imx8qxp_mek: fix CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR

The first stage of flash.bin is larger than 584 * 512, so when
writting u-boot.itb, some data will be override. Enlarge the
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR to fix boot.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 board/freescale/imx8qxp_mek/README | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'board/freescale')

diff --git a/board/freescale/imx8qxp_mek/README b/board/freescale/imx8qxp_mek/README
index f32290e3a2..9f2e2f7b12 100644
--- a/board/freescale/imx8qxp_mek/README
+++ b/board/freescale/imx8qxp_mek/README
@@ -43,7 +43,7 @@ $ export ATF_LOAD_ADDR=0x80000000
 $ export BL33_LOAD_ADDR=0x80020000
 $ make imx8qxp_mek_defconfig
 $ make flash.bin
-$ dd if=u-boot.itb of=flash.bin bs=512 seek=528
+$ dd if=u-boot.itb of=flash.bin bs=512 seek=1984
 
 Flash the binary into the SD card
 =================================
-- 
cgit 


From d94049ce19e20a07e12dbf2175981cbfeb43d8a7 Mon Sep 17 00:00:00 2001
From: Peng Fan <peng.fan@nxp.com>
Date: Thu, 22 Aug 2019 07:42:43 +0000
Subject: imx8qxp_mek: switch to use container image

Because FIT could not be used for AHAB secure boot on i.MX8,
so switch to use container image that could let SPL verify
ATF and U-Boot with AHAB.

Note: The AHAB related code has not been added.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 board/freescale/imx8qxp_mek/README              |  4 +---
 board/freescale/imx8qxp_mek/uboot-container.cfg | 13 +++++++++++++
 2 files changed, 14 insertions(+), 3 deletions(-)
 create mode 100644 board/freescale/imx8qxp_mek/uboot-container.cfg

(limited to 'board/freescale')

diff --git a/board/freescale/imx8qxp_mek/README b/board/freescale/imx8qxp_mek/README
index 9f2e2f7b12..1ee0357961 100644
--- a/board/freescale/imx8qxp_mek/README
+++ b/board/freescale/imx8qxp_mek/README
@@ -39,11 +39,9 @@ $ cp imx-sc-firmware-0.7/mx8qx-mek-scfw-tcm.bin	.
 
 Build U-Boot
 ============
-$ export ATF_LOAD_ADDR=0x80000000
-$ export BL33_LOAD_ADDR=0x80020000
 $ make imx8qxp_mek_defconfig
 $ make flash.bin
-$ dd if=u-boot.itb of=flash.bin bs=512 seek=1984
+$ dd if=u-boot.cnt of=flash.bin bs=512 seek=1984
 
 Flash the binary into the SD card
 =================================
diff --git a/board/freescale/imx8qxp_mek/uboot-container.cfg b/board/freescale/imx8qxp_mek/uboot-container.cfg
new file mode 100644
index 0000000000..8165811818
--- /dev/null
+++ b/board/freescale/imx8qxp_mek/uboot-container.cfg
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 NXP
+ */
+
+#define __ASSEMBLY__
+
+/* This file is to create a container image could be loaded by SPL */
+BOOT_FROM SD 0x400
+SOC_TYPE IMX8QX
+CONTAINER
+IMAGE A35 bl31.bin	0x80000000
+IMAGE A35 u-boot.bin	CONFIG_SYS_TEXT_BASE
-- 
cgit 


From f31f8b0434fd3f6f855b1d58cc66fc9b4c0b8cd9 Mon Sep 17 00:00:00 2001
From: Peng Fan <peng.fan@nxp.com>
Date: Thu, 22 Aug 2019 07:42:46 +0000
Subject: imx8qm_mek: switch to use container image

Because FIT could not be used for AHAB secure boot on i.MX8,
so switch to use container image that could let SPL verify
ATF and U-Boot with AHAB.

Enable HUSH_PARSER in defconfig to make run netboot could work.

Note: The AHAB related code has not been added.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 board/freescale/imx8qm_mek/README              |  4 +---
 board/freescale/imx8qm_mek/uboot-container.cfg | 13 +++++++++++++
 2 files changed, 14 insertions(+), 3 deletions(-)
 create mode 100644 board/freescale/imx8qm_mek/uboot-container.cfg

(limited to 'board/freescale')

diff --git a/board/freescale/imx8qm_mek/README b/board/freescale/imx8qm_mek/README
index c3523801ae..ebf630c446 100644
--- a/board/freescale/imx8qm_mek/README
+++ b/board/freescale/imx8qm_mek/README
@@ -39,11 +39,9 @@ $ cp imx-sc-firmware-0.7/mx8qm-mek-scfw-tcm.bin	.
 
 Build U-Boot
 ============
-$ export ATF_LOAD_ADDR=0x80000000
-$ export BL33_LOAD_ADDR=0x80020000
 $ make imx8qm_mek_defconfig
 $ make flash.bin
-$ dd if=u-boot.itb of=flash.bin bs=512 seek=1984
+$ dd if=u-boot.cnt of=flash.bin bs=512 seek=1984
 
 Flash the binary into the SD card
 =================================
diff --git a/board/freescale/imx8qm_mek/uboot-container.cfg b/board/freescale/imx8qm_mek/uboot-container.cfg
new file mode 100644
index 0000000000..6cc47cd102
--- /dev/null
+++ b/board/freescale/imx8qm_mek/uboot-container.cfg
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 NXP
+ */
+
+#define __ASSEMBLY__
+
+/* This file is to create a container image could be loaded by SPL */
+BOOT_FROM SD 0x400
+SOC_TYPE IMX8QM
+CONTAINER
+IMAGE A35 bl31.bin	0x80000000
+IMAGE A35 u-boot.bin	CONFIG_SYS_TEXT_BASE
-- 
cgit 


From 210e443d5ea8aee24a54048fc9a6d55cfebde9b2 Mon Sep 17 00:00:00 2001
From: Fabio Estevam <festevam@gmail.com>
Date: Fri, 4 Oct 2019 08:05:57 -0300
Subject: mx28evk: README: Fix location for the generic mxs README

doc/README.mxs no longer exists. It has been renamed doc/imx/common/mxs.txt,
so fix the mx28evk README accordingly.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
---
 board/freescale/mx28evk/README | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'board/freescale')

diff --git a/board/freescale/mx28evk/README b/board/freescale/mx28evk/README
index b8bee8931c..d32f0efb33 100644
--- a/board/freescale/mx28evk/README
+++ b/board/freescale/mx28evk/README
@@ -58,5 +58,5 @@ It is possible to solder a SOIC memory on U49 or use a DIP8 on J89.
 To get SPI communication to work R320, R321,R322 and C178 need to be populated.
 Look in the schematics for the proper component values.
 
-Follow the instructions from doc/README.mxs to generate a bootable SD card or
-to generate a binary to be flashed into SPI NOR.
+Follow the instructions from doc/imx/common/mxs.txt to generate a bootable
+SD card or to generate a binary to be flashed into SPI NOR.
-- 
cgit 


From 0a1a45b7d67b548d504f4e42359338a0bd4dfcee Mon Sep 17 00:00:00 2001
From: Anatolij Gustschin <agust@denx.de>
Date: Mon, 23 Sep 2019 18:05:05 +0200
Subject: imx: mx6ul_14x14_evk: fix link issue

Since recent splash changes common code for splashscreen logo
should be used instead of adding duplicated code under board
directories. mx6ul_9x9_evk and mx6ul_14x14_evk configurations
used old board specific logo code and do not link, fix them.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Acked-by: Peng Fan <peng.fan@nxp.com>
---
 board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c | 19 ++-----------------
 1 file changed, 2 insertions(+), 17 deletions(-)

(limited to 'board/freescale')

diff --git a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
index 8e5f365d35..c98e98b485 100644
--- a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
+++ b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
@@ -28,10 +28,6 @@
 #include "../common/pfuze.h"
 #include <usb.h>
 #include <usb/ehci-ci.h>
-#ifdef CONFIG_DM_VIDEO
-#include <bmp_logo_data.h>
-#include <video.h>
-#endif
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -449,6 +445,8 @@ static int setup_lcd(void)
 
 	return 0;
 }
+#else
+static inline int setup_lcd(void) { return 0; }
 #endif
 
 int board_early_init_f(void)
@@ -505,21 +503,8 @@ int board_late_init(void)
 		env_set("board_rev", "14X14");
 #endif
 
-#if defined(CONFIG_DM_VIDEO)
-	struct udevice *dev;
-	int ret;
-
-	ret = uclass_get_device(UCLASS_VIDEO, 0, &dev);
-	if (ret)
-		return ret;
-
 	setup_lcd();
 
-	ret = video_bmp_display(dev, (ulong)bmp_logo_bitmap, 0, 0, true);
-	if (ret)
-		return ret;
-#endif
-
 	return 0;
 }
 
-- 
cgit 


From 9b15ce91939d6469dda92eb297b44fa87572629a Mon Sep 17 00:00:00 2001
From: Peng Fan <peng.fan@nxp.com>
Date: Tue, 27 Aug 2019 06:26:08 +0000
Subject: imx: Add i.MX8MM EVK board support.

Add board and SoC dts
Add ddr training code
support SD/MMC/GPIO/PINCTRL/UART

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 board/freescale/imx8mm_evk/Kconfig         |   12 +
 board/freescale/imx8mm_evk/MAINTAINERS     |    6 +
 board/freescale/imx8mm_evk/Makefile        |   12 +
 board/freescale/imx8mm_evk/README          |   37 +
 board/freescale/imx8mm_evk/imx8mm_evk.c    |   29 +
 board/freescale/imx8mm_evk/lpddr4_timing.c | 1980 ++++++++++++++++++++++++++++
 board/freescale/imx8mm_evk/spl.c           |  129 ++
 7 files changed, 2205 insertions(+)
 create mode 100644 board/freescale/imx8mm_evk/Kconfig
 create mode 100644 board/freescale/imx8mm_evk/MAINTAINERS
 create mode 100644 board/freescale/imx8mm_evk/Makefile
 create mode 100644 board/freescale/imx8mm_evk/README
 create mode 100644 board/freescale/imx8mm_evk/imx8mm_evk.c
 create mode 100644 board/freescale/imx8mm_evk/lpddr4_timing.c
 create mode 100644 board/freescale/imx8mm_evk/spl.c

(limited to 'board/freescale')

diff --git a/board/freescale/imx8mm_evk/Kconfig b/board/freescale/imx8mm_evk/Kconfig
new file mode 100644
index 0000000000..299691a619
--- /dev/null
+++ b/board/freescale/imx8mm_evk/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_IMX8MM_EVK
+
+config SYS_BOARD
+	default "imx8mm_evk"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_CONFIG_NAME
+	default "imx8mm_evk"
+
+endif
diff --git a/board/freescale/imx8mm_evk/MAINTAINERS b/board/freescale/imx8mm_evk/MAINTAINERS
new file mode 100644
index 0000000000..b031bb0674
--- /dev/null
+++ b/board/freescale/imx8mm_evk/MAINTAINERS
@@ -0,0 +1,6 @@
+i.MX8MM EVK BOARD
+M:	Peng Fan <peng.fan@nxp.com>
+S:	Maintained
+F:	board/freescale/imx8mm_evk/
+F:	include/configs/imx8mm_evk.h
+F:	configs/imx8mm_evk_defconfig
diff --git a/board/freescale/imx8mm_evk/Makefile b/board/freescale/imx8mm_evk/Makefile
new file mode 100644
index 0000000000..1db7b62caf
--- /dev/null
+++ b/board/freescale/imx8mm_evk/Makefile
@@ -0,0 +1,12 @@
+#
+# Copyright 2018 NXP
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+obj-y += imx8mm_evk.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o
+endif
diff --git a/board/freescale/imx8mm_evk/README b/board/freescale/imx8mm_evk/README
new file mode 100644
index 0000000000..a885bc5c97
--- /dev/null
+++ b/board/freescale/imx8mm_evk/README
@@ -0,0 +1,37 @@
+U-Boot for the NXP i.MX8MM EVK board
+
+Quick Start
+===========
+- Build the ARM Trusted firmware binary
+- Get ddr fimware
+- Build U-Boot
+- Boot
+
+Get and Build the ARM Trusted firmware
+======================================
+Note: srctree is U-Boot source directory
+Get ATF from: https://source.codeaurora.org/external/imx/imx-atf
+branch: imx_4.19.35_1.0.0
+$ make PLAT=imx8mm bl31
+$ cp build/imx8mm/release/bl31.bin $(srctree)
+
+Get the ddr and hdmi firmware
+=============================
+$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.0.bin
+$ chmod +x firmware-imx-8.0.bin
+$ ./firmware-imx-8.0
+$ cp firmware-imx-7.9/firmware/ddr/synopsys/lpddr4*.bin $(srctree)
+
+Build U-Boot
+============
+$ export CROSS_COMPILE=aarch64-poky-linux-
+$ make imx8mm_evk_defconfig
+$ export ATF_LOAD_ADDR=0x920000
+$ make flash.bin
+
+Burn the flash.bin to MicroSD card offset 33KB
+$sudo dd if=flash.bin of=/dev/sd[x] bs=1024 seek=33
+
+Boot
+====
+Set Boot switch to SD boot
diff --git a/board/freescale/imx8mm_evk/imx8mm_evk.c b/board/freescale/imx8mm_evk/imx8mm_evk.c
new file mode 100644
index 0000000000..3706e1ec55
--- /dev/null
+++ b/board/freescale/imx8mm_evk/imx8mm_evk.c
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ */
+
+#include <common.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+	gd->ram_size = PHYS_SDRAM_SIZE;
+
+	return 0;
+}
+
+int board_init(void)
+{
+	return 0;
+}
+
+int board_late_init(void)
+{
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+	env_set("board_name", "EVK");
+	env_set("board_rev", "iMX8MM");
+#endif
+	return 0;
+}
diff --git a/board/freescale/imx8mm_evk/lpddr4_timing.c b/board/freescale/imx8mm_evk/lpddr4_timing.c
new file mode 100644
index 0000000000..8e48b9d81b
--- /dev/null
+++ b/board/freescale/imx8mm_evk/lpddr4_timing.c
@@ -0,0 +1,1980 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ */
+
+#include <linux/kernel.h>
+#include <common.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/lpddr4_define.h>
+
+struct dram_cfg_param lpddr4_ddrc_cfg[] = {
+	/* Start to config, default 3200mbps */
+	{ DDRC_DBG1(0),	0x00000001 },
+	{ DDRC_PWRCTL(0), 0x00000001 },
+	{ DDRC_MSTR(0),	0xa1080020 },
+	{ DDRC_RFSHTMG(0), 0x005b00d2 },
+	{ DDRC_INIT0(0), 0xC003061B },
+	{ DDRC_INIT1(0), 0x009D0000 },
+	{ DDRC_INIT3(0), 0x00D4002D },
+	{ DDRC_INIT4(0), (LPDDR4_MR3 << 16) | 0x0000 },
+	{ DDRC_INIT6(0), 0x0066004a },
+	{ DDRC_INIT7(0), 0x0006004a },
+
+	{ DDRC_DRAMTMG0(0), 0x1A201B22 },
+	{ DDRC_DRAMTMG1(0), 0x00060633 },
+	{ DDRC_DRAMTMG3(0), 0x00C0C000 },
+	{ DDRC_DRAMTMG4(0), 0x0F04080F },
+	{ DDRC_DRAMTMG5(0), 0x02040C0C },
+	{ DDRC_DRAMTMG6(0), 0x01010007 },
+	{ DDRC_DRAMTMG7(0), 0x00000401 },
+	{ DDRC_DRAMTMG12(0), 0x00020600 },
+	{ DDRC_DRAMTMG13(0), 0x0C100002 },
+	{ DDRC_DRAMTMG14(0), 0x000000E6 },
+	{ DDRC_DRAMTMG17(0), 0x00A00050 },
+
+	{ DDRC_ZQCTL0(0), 0x03200018 },
+	{ DDRC_ZQCTL1(0), 0x028061A8 },
+	{ DDRC_ZQCTL2(0), 0x00000000 },
+
+	{ DDRC_DFITMG0(0), 0x0497820A },
+	{ DDRC_DFITMG2(0), 0x0000170A },
+	{ DDRC_DRAMTMG2(0), 0x070E171a },
+	{ DDRC_DBICTL(0), 0x00000001 },
+
+	{ DDRC_DFITMG1(0), 0x00080303 },
+	{ DDRC_DFIUPD0(0), 0xE0400018 },
+	{ DDRC_DFIUPD1(0), 0x00DF00E4 },
+	{ DDRC_DFIUPD2(0), 0x80000000 },
+	{ DDRC_DFIMISC(0), 0x00000011 },
+
+	{ DDRC_DFIPHYMSTR(0), 0x00000000 },
+	{ DDRC_RANKCTL(0), 0x00000c99 },
+
+	/* address mapping */
+	{ DDRC_ADDRMAP0(0), 0x0000001f },
+	{ DDRC_ADDRMAP1(0), 0x00080808 },
+	{ DDRC_ADDRMAP2(0), 0x00000000 },
+	{ DDRC_ADDRMAP3(0), 0x00000000 },
+	{ DDRC_ADDRMAP4(0), 0x00001f1f },
+	{ DDRC_ADDRMAP5(0), 0x07070707 },
+	{ DDRC_ADDRMAP6(0), 0x07070707 },
+	{ DDRC_ADDRMAP7(0), 0x00000f0f },
+
+	/* performance setting */
+	{ DDRC_SCHED(0), 0x29001701 },
+	{ DDRC_SCHED1(0), 0x0000002c },
+	{ DDRC_PERFHPR1(0), 0x04000030 },
+	{ DDRC_PERFLPR1(0), 0x900093e7 },
+	{ DDRC_PERFWR1(0), 0x20005574 },
+	{ DDRC_PCCFG(0), 0x00000111 },
+	{ DDRC_PCFGW_0(0), 0x000072ff },
+	{ DDRC_PCFGQOS0_0(0), 0x02100e07 },
+	{ DDRC_PCFGQOS1_0(0), 0x00620096 },
+	{ DDRC_PCFGWQOS0_0(0), 0x01100e07 },
+	{ DDRC_PCFGWQOS1_0(0), 0x00c8012c },
+
+	/* frequency P1&P2 */
+	/* Frequency 1: 400mbps */
+	{ DDRC_FREQ1_DRAMTMG0(0), 0x0d0b010c },
+	{ DDRC_FREQ1_DRAMTMG1(0), 0x00030410 },
+	{ DDRC_FREQ1_DRAMTMG2(0), 0x0203090c },
+	{ DDRC_FREQ1_DRAMTMG3(0), 0x00505006 },
+	{ DDRC_FREQ1_DRAMTMG4(0), 0x05040305 },
+	{ DDRC_FREQ1_DRAMTMG5(0), 0x0d0e0504 },
+	{ DDRC_FREQ1_DRAMTMG6(0), 0x0a060004 },
+	{ DDRC_FREQ1_DRAMTMG7(0), 0x0000090e },
+	{ DDRC_FREQ1_DRAMTMG14(0), 0x00000032 },
+	{ DDRC_FREQ1_DRAMTMG15(0), 0x00000000 },
+	{ DDRC_FREQ1_DRAMTMG17(0), 0x0036001b },
+	{ DDRC_FREQ1_DERATEINT(0), 0x7e9fbeb1 },
+	{ DDRC_FREQ1_DFITMG0(0), 0x03818200 },
+	{ DDRC_FREQ1_DFITMG2(0), 0x00000000 },
+	{ DDRC_FREQ1_RFSHTMG(0), 0x000C001c },
+	{ DDRC_FREQ1_INIT3(0), 0x00840000 },
+	{ DDRC_FREQ1_INIT4(0), 0x00310000 },
+	{ DDRC_FREQ1_INIT6(0), 0x0066004a },
+	{ DDRC_FREQ1_INIT7(0), 0x0006004a },
+
+	/* Frequency 2: 100mbps */
+	{ DDRC_FREQ2_DRAMTMG0(0), 0x0d0b010c },
+	{ DDRC_FREQ2_DRAMTMG1(0), 0x00030410 },
+	{ DDRC_FREQ2_DRAMTMG2(0), 0x0203090c },
+	{ DDRC_FREQ2_DRAMTMG3(0), 0x00505006 },
+	{ DDRC_FREQ2_DRAMTMG4(0), 0x05040305 },
+	{ DDRC_FREQ2_DRAMTMG5(0), 0x0d0e0504 },
+	{ DDRC_FREQ2_DRAMTMG6(0), 0x0a060004 },
+	{ DDRC_FREQ2_DRAMTMG7(0), 0x0000090e },
+	{ DDRC_FREQ2_DRAMTMG14(0), 0x00000032 },
+	{ DDRC_FREQ2_DRAMTMG17(0), 0x0036001b },
+	{ DDRC_FREQ2_DERATEINT(0), 0x7e9fbeb1 },
+	{ DDRC_FREQ2_DFITMG0(0), 0x03818200 },
+	{ DDRC_FREQ2_DFITMG2(0), 0x00000000 },
+	{ DDRC_FREQ2_RFSHTMG(0), 0x0003800c },
+	{ DDRC_FREQ2_RFSHTMG(0), 0x00030007 },
+	{ DDRC_FREQ2_INIT3(0), 0x00840000 },
+	{ DDRC_FREQ2_INIT4(0), 0x00310008 },
+	{ DDRC_FREQ2_INIT4(0), (LPDDR4_MR3 << 16) | 0x0000 },
+	{ DDRC_FREQ2_INIT6(0), 0x0066004a },
+	{ DDRC_FREQ2_INIT7(0), 0x0006004a },
+
+	/* boot start point */
+	{ DDRC_MSTR2(0), 0x2 }, //DDRC_MSTR2
+};
+
+/* PHY Initialize Configuration */
+struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
+	{ 0x1005f, 0x1ff },
+	{ 0x1015f, 0x1ff },
+	{ 0x1105f, 0x1ff },
+	{ 0x1115f, 0x1ff },
+	{ 0x1205f, 0x1ff },
+	{ 0x1215f, 0x1ff },
+	{ 0x1305f, 0x1ff },
+	{ 0x1315f, 0x1ff },
+
+	{ 0x11005f, 0x1ff },
+	{ 0x11015f, 0x1ff },
+	{ 0x11105f, 0x1ff },
+	{ 0x11115f, 0x1ff },
+	{ 0x11205f, 0x1ff },
+	{ 0x11215f, 0x1ff },
+	{ 0x11305f, 0x1ff },
+	{ 0x11315f, 0x1ff },
+
+	{ 0x21005f, 0x1ff },
+	{ 0x21015f, 0x1ff },
+	{ 0x21105f, 0x1ff },
+	{ 0x21115f, 0x1ff },
+	{ 0x21205f, 0x1ff },
+	{ 0x21215f, 0x1ff },
+	{ 0x21305f, 0x1ff },
+	{ 0x21315f, 0x1ff },
+
+	{ 0x55, 0x1ff },
+	{ 0x1055, 0x1ff },
+	{ 0x2055, 0x1ff },
+	{ 0x3055, 0x1ff },
+	{ 0x4055, 0x1ff },
+	{ 0x5055, 0x1ff },
+	{ 0x6055, 0x1ff },
+	{ 0x7055, 0x1ff },
+	{ 0x8055, 0x1ff },
+	{ 0x9055, 0x1ff },
+
+	{ 0x200c5, 0x19 },
+	{ 0x1200c5, 0x7 },
+	{ 0x2200c5, 0x7 },
+
+	{ 0x2002e, 0x2 },
+	{ 0x12002e, 0x2 },
+	{ 0x22002e, 0x2 },
+
+	{ 0x90204, 0x0 },
+	{ 0x190204, 0x0 },
+	{ 0x290204, 0x0 },
+
+	{ 0x20024, 0xab },
+	{ 0x2003a, 0x0 },
+
+	{ 0x120024, 0xab },
+	{ 0x2003a, 0x0 },
+
+	{ 0x220024, 0xab },
+	{ 0x2003a, 0x0 },
+
+	{ 0x20056, 0x3 },
+	{ 0x120056, 0xa },
+	{ 0x220056, 0xa },
+
+	{ 0x1004d, 0xe00 },
+	{ 0x1014d, 0xe00 },
+	{ 0x1104d, 0xe00 },
+	{ 0x1114d, 0xe00 },
+	{ 0x1204d, 0xe00 },
+	{ 0x1214d, 0xe00 },
+	{ 0x1304d, 0xe00 },
+	{ 0x1314d, 0xe00 },
+
+	{ 0x11004d, 0xe00 },
+	{ 0x11014d, 0xe00 },
+	{ 0x11104d, 0xe00 },
+	{ 0x11114d, 0xe00 },
+	{ 0x11204d, 0xe00 },
+	{ 0x11214d, 0xe00 },
+	{ 0x11304d, 0xe00 },
+	{ 0x11314d, 0xe00 },
+
+	{ 0x21004d, 0xe00 },
+	{ 0x21014d, 0xe00 },
+	{ 0x21104d, 0xe00 },
+	{ 0x21114d, 0xe00 },
+	{ 0x21204d, 0xe00 },
+	{ 0x21214d, 0xe00 },
+	{ 0x21304d, 0xe00 },
+	{ 0x21314d, 0xe00 },
+
+	{ 0x10049, 0xfbe },
+	{ 0x10149, 0xfbe },
+	{ 0x11049, 0xfbe },
+	{ 0x11149, 0xfbe },
+	{ 0x12049, 0xfbe },
+	{ 0x12149, 0xfbe },
+	{ 0x13049, 0xfbe },
+	{ 0x13149, 0xfbe },
+
+	{ 0x110049, 0xfbe },
+	{ 0x110149, 0xfbe },
+	{ 0x111049, 0xfbe },
+	{ 0x111149, 0xfbe },
+	{ 0x112049, 0xfbe },
+	{ 0x112149, 0xfbe },
+	{ 0x113049, 0xfbe },
+	{ 0x113149, 0xfbe },
+
+	{ 0x210049, 0xfbe },
+	{ 0x210149, 0xfbe },
+	{ 0x211049, 0xfbe },
+	{ 0x211149, 0xfbe },
+	{ 0x212049, 0xfbe },
+	{ 0x212149, 0xfbe },
+	{ 0x213049, 0xfbe },
+	{ 0x213149, 0xfbe },
+
+	{ 0x43, 0x63 },
+	{ 0x1043, 0x63 },
+	{ 0x2043, 0x63 },
+	{ 0x3043, 0x63 },
+	{ 0x4043, 0x63 },
+	{ 0x5043, 0x63 },
+	{ 0x6043, 0x63 },
+	{ 0x7043, 0x63 },
+	{ 0x8043, 0x63 },
+	{ 0x9043, 0x63 },
+
+	{ 0x20018, 0x3 },
+	{ 0x20075, 0x4 },
+	{ 0x20050, 0x0 },
+	{ 0x20008, 0x2ee },
+	{ 0x120008, 0x64 },
+	{ 0x220008, 0x19 },
+	{ 0x20088, 0x9 },
+
+	{ 0x200b2, 0x1d4 },
+	{ 0x10043, 0x5a1 },
+	{ 0x10143, 0x5a1 },
+	{ 0x11043, 0x5a1 },
+	{ 0x11143, 0x5a1 },
+	{ 0x12043, 0x5a1 },
+	{ 0x12143, 0x5a1 },
+	{ 0x13043, 0x5a1 },
+	{ 0x13143, 0x5a1 },
+
+	{ 0x1200b2, 0xdc },
+	{ 0x110043, 0x5a1 },
+	{ 0x110143, 0x5a1 },
+	{ 0x111043, 0x5a1 },
+	{ 0x111143, 0x5a1 },
+	{ 0x112043, 0x5a1 },
+	{ 0x112143, 0x5a1 },
+	{ 0x113043, 0x5a1 },
+	{ 0x113143, 0x5a1 },
+
+	{ 0x2200b2, 0xdc },
+	{ 0x210043, 0x5a1 },
+	{ 0x210143, 0x5a1 },
+	{ 0x211043, 0x5a1 },
+	{ 0x211143, 0x5a1 },
+	{ 0x212043, 0x5a1 },
+	{ 0x212143, 0x5a1 },
+	{ 0x213043, 0x5a1 },
+	{ 0x213143, 0x5a1 },
+
+	{ 0x200fa, 0x1 },
+	{ 0x1200fa, 0x1 },
+	{ 0x2200fa, 0x1 },
+
+	{ 0x20019, 0x1 },
+	{ 0x120019, 0x1 },
+	{ 0x220019, 0x1 },
+
+	{ 0x200f0, 0x660 },
+	{ 0x200f1, 0x0 },
+	{ 0x200f2, 0x4444 },
+	{ 0x200f3, 0x8888 },
+	{ 0x200f4, 0x5665 },
+	{ 0x200f5, 0x0 },
+	{ 0x200f6, 0x0 },
+	{ 0x200f7, 0xf000 },
+
+	{ 0x20025, 0x0 },
+	{ 0x2002d, LPDDR4_PHY_DMIPinPresent },
+	{ 0x12002d, LPDDR4_PHY_DMIPinPresent },
+	{ 0x22002d, LPDDR4_PHY_DMIPinPresent },
+	{ 0x200c7, 0x21 },
+	{ 0x200ca, 0x24 },
+	{ 0x1200c7, 0x21 },
+	{ 0x1200ca, 0x24 },
+	{ 0x2200c7, 0x21 },
+	{ 0x2200ca, 0x24 },
+};
+
+/* ddr phy trained csr */
+struct dram_cfg_param lpddr4_ddrphy_trained_csr[] = {
+	{ 0x200b2, 0x0 },
+	{ 0x1200b2, 0x0 },
+	{ 0x2200b2, 0x0 },
+	{ 0x200cb, 0x0 },
+	{ 0x10043, 0x0 },
+	{ 0x110043, 0x0 },
+	{ 0x210043, 0x0 },
+	{ 0x10143, 0x0 },
+	{ 0x110143, 0x0 },
+	{ 0x210143, 0x0 },
+	{ 0x11043, 0x0 },
+	{ 0x111043, 0x0 },
+	{ 0x211043, 0x0 },
+	{ 0x11143, 0x0 },
+	{ 0x111143, 0x0 },
+	{ 0x211143, 0x0 },
+	{ 0x12043, 0x0 },
+	{ 0x112043, 0x0 },
+	{ 0x212043, 0x0 },
+	{ 0x12143, 0x0 },
+	{ 0x112143, 0x0 },
+	{ 0x212143, 0x0 },
+	{ 0x13043, 0x0 },
+	{ 0x113043, 0x0 },
+	{ 0x213043, 0x0 },
+	{ 0x13143, 0x0 },
+	{ 0x113143, 0x0 },
+	{ 0x213143, 0x0 },
+	{ 0x80, 0x0 },
+	{ 0x100080, 0x0 },
+	{ 0x200080, 0x0 },
+	{ 0x1080, 0x0 },
+	{ 0x101080, 0x0 },
+	{ 0x201080, 0x0 },
+	{ 0x2080, 0x0 },
+	{ 0x102080, 0x0 },
+	{ 0x202080, 0x0 },
+	{ 0x3080, 0x0 },
+	{ 0x103080, 0x0 },
+	{ 0x203080, 0x0 },
+	{ 0x4080, 0x0 },
+	{ 0x104080, 0x0 },
+	{ 0x204080, 0x0 },
+	{ 0x5080, 0x0 },
+	{ 0x105080, 0x0 },
+	{ 0x205080, 0x0 },
+	{ 0x6080, 0x0 },
+	{ 0x106080, 0x0 },
+	{ 0x206080, 0x0 },
+	{ 0x7080, 0x0 },
+	{ 0x107080, 0x0 },
+	{ 0x207080, 0x0 },
+	{ 0x8080, 0x0 },
+	{ 0x108080, 0x0 },
+	{ 0x208080, 0x0 },
+	{ 0x9080, 0x0 },
+	{ 0x109080, 0x0 },
+	{ 0x209080, 0x0 },
+	{ 0x10080, 0x0 },
+	{ 0x110080, 0x0 },
+	{ 0x210080, 0x0 },
+	{ 0x10180, 0x0 },
+	{ 0x110180, 0x0 },
+	{ 0x210180, 0x0 },
+	{ 0x11080, 0x0 },
+	{ 0x111080, 0x0 },
+	{ 0x211080, 0x0 },
+	{ 0x11180, 0x0 },
+	{ 0x111180, 0x0 },
+	{ 0x211180, 0x0 },
+	{ 0x12080, 0x0 },
+	{ 0x112080, 0x0 },
+	{ 0x212080, 0x0 },
+	{ 0x12180, 0x0 },
+	{ 0x112180, 0x0 },
+	{ 0x212180, 0x0 },
+	{ 0x13080, 0x0 },
+	{ 0x113080, 0x0 },
+	{ 0x213080, 0x0 },
+	{ 0x13180, 0x0 },
+	{ 0x113180, 0x0 },
+	{ 0x213180, 0x0 },
+	{ 0x10081, 0x0 },
+	{ 0x110081, 0x0 },
+	{ 0x210081, 0x0 },
+	{ 0x10181, 0x0 },
+	{ 0x110181, 0x0 },
+	{ 0x210181, 0x0 },
+	{ 0x11081, 0x0 },
+	{ 0x111081, 0x0 },
+	{ 0x211081, 0x0 },
+	{ 0x11181, 0x0 },
+	{ 0x111181, 0x0 },
+	{ 0x211181, 0x0 },
+	{ 0x12081, 0x0 },
+	{ 0x112081, 0x0 },
+	{ 0x212081, 0x0 },
+	{ 0x12181, 0x0 },
+	{ 0x112181, 0x0 },
+	{ 0x212181, 0x0 },
+	{ 0x13081, 0x0 },
+	{ 0x113081, 0x0 },
+	{ 0x213081, 0x0 },
+	{ 0x13181, 0x0 },
+	{ 0x113181, 0x0 },
+	{ 0x213181, 0x0 },
+	{ 0x100d0, 0x0 },
+	{ 0x1100d0, 0x0 },
+	{ 0x2100d0, 0x0 },
+	{ 0x101d0, 0x0 },
+	{ 0x1101d0, 0x0 },
+	{ 0x2101d0, 0x0 },
+	{ 0x110d0, 0x0 },
+	{ 0x1110d0, 0x0 },
+	{ 0x2110d0, 0x0 },
+	{ 0x111d0, 0x0 },
+	{ 0x1111d0, 0x0 },
+	{ 0x2111d0, 0x0 },
+	{ 0x120d0, 0x0 },
+	{ 0x1120d0, 0x0 },
+	{ 0x2120d0, 0x0 },
+	{ 0x121d0, 0x0 },
+	{ 0x1121d0, 0x0 },
+	{ 0x2121d0, 0x0 },
+	{ 0x130d0, 0x0 },
+	{ 0x1130d0, 0x0 },
+	{ 0x2130d0, 0x0 },
+	{ 0x131d0, 0x0 },
+	{ 0x1131d0, 0x0 },
+	{ 0x2131d0, 0x0 },
+	{ 0x100d1, 0x0 },
+	{ 0x1100d1, 0x0 },
+	{ 0x2100d1, 0x0 },
+	{ 0x101d1, 0x0 },
+	{ 0x1101d1, 0x0 },
+	{ 0x2101d1, 0x0 },
+	{ 0x110d1, 0x0 },
+	{ 0x1110d1, 0x0 },
+	{ 0x2110d1, 0x0 },
+	{ 0x111d1, 0x0 },
+	{ 0x1111d1, 0x0 },
+	{ 0x2111d1, 0x0 },
+	{ 0x120d1, 0x0 },
+	{ 0x1120d1, 0x0 },
+	{ 0x2120d1, 0x0 },
+	{ 0x121d1, 0x0 },
+	{ 0x1121d1, 0x0 },
+	{ 0x2121d1, 0x0 },
+	{ 0x130d1, 0x0 },
+	{ 0x1130d1, 0x0 },
+	{ 0x2130d1, 0x0 },
+	{ 0x131d1, 0x0 },
+	{ 0x1131d1, 0x0 },
+	{ 0x2131d1, 0x0 },
+	{ 0x10068, 0x0 },
+	{ 0x10168, 0x0 },
+	{ 0x10268, 0x0 },
+	{ 0x10368, 0x0 },
+	{ 0x10468, 0x0 },
+	{ 0x10568, 0x0 },
+	{ 0x10668, 0x0 },
+	{ 0x10768, 0x0 },
+	{ 0x10868, 0x0 },
+	{ 0x11068, 0x0 },
+	{ 0x11168, 0x0 },
+	{ 0x11268, 0x0 },
+	{ 0x11368, 0x0 },
+	{ 0x11468, 0x0 },
+	{ 0x11568, 0x0 },
+	{ 0x11668, 0x0 },
+	{ 0x11768, 0x0 },
+	{ 0x11868, 0x0 },
+	{ 0x12068, 0x0 },
+	{ 0x12168, 0x0 },
+	{ 0x12268, 0x0 },
+	{ 0x12368, 0x0 },
+	{ 0x12468, 0x0 },
+	{ 0x12568, 0x0 },
+	{ 0x12668, 0x0 },
+	{ 0x12768, 0x0 },
+	{ 0x12868, 0x0 },
+	{ 0x13068, 0x0 },
+	{ 0x13168, 0x0 },
+	{ 0x13268, 0x0 },
+	{ 0x13368, 0x0 },
+	{ 0x13468, 0x0 },
+	{ 0x13568, 0x0 },
+	{ 0x13668, 0x0 },
+	{ 0x13768, 0x0 },
+	{ 0x13868, 0x0 },
+	{ 0x10069, 0x0 },
+	{ 0x10169, 0x0 },
+	{ 0x10269, 0x0 },
+	{ 0x10369, 0x0 },
+	{ 0x10469, 0x0 },
+	{ 0x10569, 0x0 },
+	{ 0x10669, 0x0 },
+	{ 0x10769, 0x0 },
+	{ 0x10869, 0x0 },
+	{ 0x11069, 0x0 },
+	{ 0x11169, 0x0 },
+	{ 0x11269, 0x0 },
+	{ 0x11369, 0x0 },
+	{ 0x11469, 0x0 },
+	{ 0x11569, 0x0 },
+	{ 0x11669, 0x0 },
+	{ 0x11769, 0x0 },
+	{ 0x11869, 0x0 },
+	{ 0x12069, 0x0 },
+	{ 0x12169, 0x0 },
+	{ 0x12269, 0x0 },
+	{ 0x12369, 0x0 },
+	{ 0x12469, 0x0 },
+	{ 0x12569, 0x0 },
+	{ 0x12669, 0x0 },
+	{ 0x12769, 0x0 },
+	{ 0x12869, 0x0 },
+	{ 0x13069, 0x0 },
+	{ 0x13169, 0x0 },
+	{ 0x13269, 0x0 },
+	{ 0x13369, 0x0 },
+	{ 0x13469, 0x0 },
+	{ 0x13569, 0x0 },
+	{ 0x13669, 0x0 },
+	{ 0x13769, 0x0 },
+	{ 0x13869, 0x0 },
+	{ 0x1008c, 0x0 },
+	{ 0x11008c, 0x0 },
+	{ 0x21008c, 0x0 },
+	{ 0x1018c, 0x0 },
+	{ 0x11018c, 0x0 },
+	{ 0x21018c, 0x0 },
+	{ 0x1108c, 0x0 },
+	{ 0x11108c, 0x0 },
+	{ 0x21108c, 0x0 },
+	{ 0x1118c, 0x0 },
+	{ 0x11118c, 0x0 },
+	{ 0x21118c, 0x0 },
+	{ 0x1208c, 0x0 },
+	{ 0x11208c, 0x0 },
+	{ 0x21208c, 0x0 },
+	{ 0x1218c, 0x0 },
+	{ 0x11218c, 0x0 },
+	{ 0x21218c, 0x0 },
+	{ 0x1308c, 0x0 },
+	{ 0x11308c, 0x0 },
+	{ 0x21308c, 0x0 },
+	{ 0x1318c, 0x0 },
+	{ 0x11318c, 0x0 },
+	{ 0x21318c, 0x0 },
+	{ 0x1008d, 0x0 },
+	{ 0x11008d, 0x0 },
+	{ 0x21008d, 0x0 },
+	{ 0x1018d, 0x0 },
+	{ 0x11018d, 0x0 },
+	{ 0x21018d, 0x0 },
+	{ 0x1108d, 0x0 },
+	{ 0x11108d, 0x0 },
+	{ 0x21108d, 0x0 },
+	{ 0x1118d, 0x0 },
+	{ 0x11118d, 0x0 },
+	{ 0x21118d, 0x0 },
+	{ 0x1208d, 0x0 },
+	{ 0x11208d, 0x0 },
+	{ 0x21208d, 0x0 },
+	{ 0x1218d, 0x0 },
+	{ 0x11218d, 0x0 },
+	{ 0x21218d, 0x0 },
+	{ 0x1308d, 0x0 },
+	{ 0x11308d, 0x0 },
+	{ 0x21308d, 0x0 },
+	{ 0x1318d, 0x0 },
+	{ 0x11318d, 0x0 },
+	{ 0x21318d, 0x0 },
+	{ 0x100c0, 0x0 },
+	{ 0x1100c0, 0x0 },
+	{ 0x2100c0, 0x0 },
+	{ 0x101c0, 0x0 },
+	{ 0x1101c0, 0x0 },
+	{ 0x2101c0, 0x0 },
+	{ 0x102c0, 0x0 },
+	{ 0x1102c0, 0x0 },
+	{ 0x2102c0, 0x0 },
+	{ 0x103c0, 0x0 },
+	{ 0x1103c0, 0x0 },
+	{ 0x2103c0, 0x0 },
+	{ 0x104c0, 0x0 },
+	{ 0x1104c0, 0x0 },
+	{ 0x2104c0, 0x0 },
+	{ 0x105c0, 0x0 },
+	{ 0x1105c0, 0x0 },
+	{ 0x2105c0, 0x0 },
+	{ 0x106c0, 0x0 },
+	{ 0x1106c0, 0x0 },
+	{ 0x2106c0, 0x0 },
+	{ 0x107c0, 0x0 },
+	{ 0x1107c0, 0x0 },
+	{ 0x2107c0, 0x0 },
+	{ 0x108c0, 0x0 },
+	{ 0x1108c0, 0x0 },
+	{ 0x2108c0, 0x0 },
+	{ 0x110c0, 0x0 },
+	{ 0x1110c0, 0x0 },
+	{ 0x2110c0, 0x0 },
+	{ 0x111c0, 0x0 },
+	{ 0x1111c0, 0x0 },
+	{ 0x2111c0, 0x0 },
+	{ 0x112c0, 0x0 },
+	{ 0x1112c0, 0x0 },
+	{ 0x2112c0, 0x0 },
+	{ 0x113c0, 0x0 },
+	{ 0x1113c0, 0x0 },
+	{ 0x2113c0, 0x0 },
+	{ 0x114c0, 0x0 },
+	{ 0x1114c0, 0x0 },
+	{ 0x2114c0, 0x0 },
+	{ 0x115c0, 0x0 },
+	{ 0x1115c0, 0x0 },
+	{ 0x2115c0, 0x0 },
+	{ 0x116c0, 0x0 },
+	{ 0x1116c0, 0x0 },
+	{ 0x2116c0, 0x0 },
+	{ 0x117c0, 0x0 },
+	{ 0x1117c0, 0x0 },
+	{ 0x2117c0, 0x0 },
+	{ 0x118c0, 0x0 },
+	{ 0x1118c0, 0x0 },
+	{ 0x2118c0, 0x0 },
+	{ 0x120c0, 0x0 },
+	{ 0x1120c0, 0x0 },
+	{ 0x2120c0, 0x0 },
+	{ 0x121c0, 0x0 },
+	{ 0x1121c0, 0x0 },
+	{ 0x2121c0, 0x0 },
+	{ 0x122c0, 0x0 },
+	{ 0x1122c0, 0x0 },
+	{ 0x2122c0, 0x0 },
+	{ 0x123c0, 0x0 },
+	{ 0x1123c0, 0x0 },
+	{ 0x2123c0, 0x0 },
+	{ 0x124c0, 0x0 },
+	{ 0x1124c0, 0x0 },
+	{ 0x2124c0, 0x0 },
+	{ 0x125c0, 0x0 },
+	{ 0x1125c0, 0x0 },
+	{ 0x2125c0, 0x0 },
+	{ 0x126c0, 0x0 },
+	{ 0x1126c0, 0x0 },
+	{ 0x2126c0, 0x0 },
+	{ 0x127c0, 0x0 },
+	{ 0x1127c0, 0x0 },
+	{ 0x2127c0, 0x0 },
+	{ 0x128c0, 0x0 },
+	{ 0x1128c0, 0x0 },
+	{ 0x2128c0, 0x0 },
+	{ 0x130c0, 0x0 },
+	{ 0x1130c0, 0x0 },
+	{ 0x2130c0, 0x0 },
+	{ 0x131c0, 0x0 },
+	{ 0x1131c0, 0x0 },
+	{ 0x2131c0, 0x0 },
+	{ 0x132c0, 0x0 },
+	{ 0x1132c0, 0x0 },
+	{ 0x2132c0, 0x0 },
+	{ 0x133c0, 0x0 },
+	{ 0x1133c0, 0x0 },
+	{ 0x2133c0, 0x0 },
+	{ 0x134c0, 0x0 },
+	{ 0x1134c0, 0x0 },
+	{ 0x2134c0, 0x0 },
+	{ 0x135c0, 0x0 },
+	{ 0x1135c0, 0x0 },
+	{ 0x2135c0, 0x0 },
+	{ 0x136c0, 0x0 },
+	{ 0x1136c0, 0x0 },
+	{ 0x2136c0, 0x0 },
+	{ 0x137c0, 0x0 },
+	{ 0x1137c0, 0x0 },
+	{ 0x2137c0, 0x0 },
+	{ 0x138c0, 0x0 },
+	{ 0x1138c0, 0x0 },
+	{ 0x2138c0, 0x0 },
+	{ 0x100c1, 0x0 },
+	{ 0x1100c1, 0x0 },
+	{ 0x2100c1, 0x0 },
+	{ 0x101c1, 0x0 },
+	{ 0x1101c1, 0x0 },
+	{ 0x2101c1, 0x0 },
+	{ 0x102c1, 0x0 },
+	{ 0x1102c1, 0x0 },
+	{ 0x2102c1, 0x0 },
+	{ 0x103c1, 0x0 },
+	{ 0x1103c1, 0x0 },
+	{ 0x2103c1, 0x0 },
+	{ 0x104c1, 0x0 },
+	{ 0x1104c1, 0x0 },
+	{ 0x2104c1, 0x0 },
+	{ 0x105c1, 0x0 },
+	{ 0x1105c1, 0x0 },
+	{ 0x2105c1, 0x0 },
+	{ 0x106c1, 0x0 },
+	{ 0x1106c1, 0x0 },
+	{ 0x2106c1, 0x0 },
+	{ 0x107c1, 0x0 },
+	{ 0x1107c1, 0x0 },
+	{ 0x2107c1, 0x0 },
+	{ 0x108c1, 0x0 },
+	{ 0x1108c1, 0x0 },
+	{ 0x2108c1, 0x0 },
+	{ 0x110c1, 0x0 },
+	{ 0x1110c1, 0x0 },
+	{ 0x2110c1, 0x0 },
+	{ 0x111c1, 0x0 },
+	{ 0x1111c1, 0x0 },
+	{ 0x2111c1, 0x0 },
+	{ 0x112c1, 0x0 },
+	{ 0x1112c1, 0x0 },
+	{ 0x2112c1, 0x0 },
+	{ 0x113c1, 0x0 },
+	{ 0x1113c1, 0x0 },
+	{ 0x2113c1, 0x0 },
+	{ 0x114c1, 0x0 },
+	{ 0x1114c1, 0x0 },
+	{ 0x2114c1, 0x0 },
+	{ 0x115c1, 0x0 },
+	{ 0x1115c1, 0x0 },
+	{ 0x2115c1, 0x0 },
+	{ 0x116c1, 0x0 },
+	{ 0x1116c1, 0x0 },
+	{ 0x2116c1, 0x0 },
+	{ 0x117c1, 0x0 },
+	{ 0x1117c1, 0x0 },
+	{ 0x2117c1, 0x0 },
+	{ 0x118c1, 0x0 },
+	{ 0x1118c1, 0x0 },
+	{ 0x2118c1, 0x0 },
+	{ 0x120c1, 0x0 },
+	{ 0x1120c1, 0x0 },
+	{ 0x2120c1, 0x0 },
+	{ 0x121c1, 0x0 },
+	{ 0x1121c1, 0x0 },
+	{ 0x2121c1, 0x0 },
+	{ 0x122c1, 0x0 },
+	{ 0x1122c1, 0x0 },
+	{ 0x2122c1, 0x0 },
+	{ 0x123c1, 0x0 },
+	{ 0x1123c1, 0x0 },
+	{ 0x2123c1, 0x0 },
+	{ 0x124c1, 0x0 },
+	{ 0x1124c1, 0x0 },
+	{ 0x2124c1, 0x0 },
+	{ 0x125c1, 0x0 },
+	{ 0x1125c1, 0x0 },
+	{ 0x2125c1, 0x0 },
+	{ 0x126c1, 0x0 },
+	{ 0x1126c1, 0x0 },
+	{ 0x2126c1, 0x0 },
+	{ 0x127c1, 0x0 },
+	{ 0x1127c1, 0x0 },
+	{ 0x2127c1, 0x0 },
+	{ 0x128c1, 0x0 },
+	{ 0x1128c1, 0x0 },
+	{ 0x2128c1, 0x0 },
+	{ 0x130c1, 0x0 },
+	{ 0x1130c1, 0x0 },
+	{ 0x2130c1, 0x0 },
+	{ 0x131c1, 0x0 },
+	{ 0x1131c1, 0x0 },
+	{ 0x2131c1, 0x0 },
+	{ 0x132c1, 0x0 },
+	{ 0x1132c1, 0x0 },
+	{ 0x2132c1, 0x0 },
+	{ 0x133c1, 0x0 },
+	{ 0x1133c1, 0x0 },
+	{ 0x2133c1, 0x0 },
+	{ 0x134c1, 0x0 },
+	{ 0x1134c1, 0x0 },
+	{ 0x2134c1, 0x0 },
+	{ 0x135c1, 0x0 },
+	{ 0x1135c1, 0x0 },
+	{ 0x2135c1, 0x0 },
+	{ 0x136c1, 0x0 },
+	{ 0x1136c1, 0x0 },
+	{ 0x2136c1, 0x0 },
+	{ 0x137c1, 0x0 },
+	{ 0x1137c1, 0x0 },
+	{ 0x2137c1, 0x0 },
+	{ 0x138c1, 0x0 },
+	{ 0x1138c1, 0x0 },
+	{ 0x2138c1, 0x0 },
+	{ 0x10020, 0x0 },
+	{ 0x110020, 0x0 },
+	{ 0x210020, 0x0 },
+	{ 0x11020, 0x0 },
+	{ 0x111020, 0x0 },
+	{ 0x211020, 0x0 },
+	{ 0x12020, 0x0 },
+	{ 0x112020, 0x0 },
+	{ 0x212020, 0x0 },
+	{ 0x13020, 0x0 },
+	{ 0x113020, 0x0 },
+	{ 0x213020, 0x0 },
+	{ 0x20072, 0x0 },
+	{ 0x20073, 0x0 },
+	{ 0x20074, 0x0 },
+	{ 0x100aa, 0x0 },
+	{ 0x110aa, 0x0 },
+	{ 0x120aa, 0x0 },
+	{ 0x130aa, 0x0 },
+	{ 0x20010, 0x0 },
+	{ 0x120010, 0x0 },
+	{ 0x220010, 0x0 },
+	{ 0x20011, 0x0 },
+	{ 0x120011, 0x0 },
+	{ 0x220011, 0x0 },
+	{ 0x100ae, 0x0 },
+	{ 0x1100ae, 0x0 },
+	{ 0x2100ae, 0x0 },
+	{ 0x100af, 0x0 },
+	{ 0x1100af, 0x0 },
+	{ 0x2100af, 0x0 },
+	{ 0x110ae, 0x0 },
+	{ 0x1110ae, 0x0 },
+	{ 0x2110ae, 0x0 },
+	{ 0x110af, 0x0 },
+	{ 0x1110af, 0x0 },
+	{ 0x2110af, 0x0 },
+	{ 0x120ae, 0x0 },
+	{ 0x1120ae, 0x0 },
+	{ 0x2120ae, 0x0 },
+	{ 0x120af, 0x0 },
+	{ 0x1120af, 0x0 },
+	{ 0x2120af, 0x0 },
+	{ 0x130ae, 0x0 },
+	{ 0x1130ae, 0x0 },
+	{ 0x2130ae, 0x0 },
+	{ 0x130af, 0x0 },
+	{ 0x1130af, 0x0 },
+	{ 0x2130af, 0x0 },
+	{ 0x20020, 0x0 },
+	{ 0x120020, 0x0 },
+	{ 0x220020, 0x0 },
+	{ 0x100a0, 0x0 },
+	{ 0x100a1, 0x0 },
+	{ 0x100a2, 0x0 },
+	{ 0x100a3, 0x0 },
+	{ 0x100a4, 0x0 },
+	{ 0x100a5, 0x0 },
+	{ 0x100a6, 0x0 },
+	{ 0x100a7, 0x0 },
+	{ 0x110a0, 0x0 },
+	{ 0x110a1, 0x0 },
+	{ 0x110a2, 0x0 },
+	{ 0x110a3, 0x0 },
+	{ 0x110a4, 0x0 },
+	{ 0x110a5, 0x0 },
+	{ 0x110a6, 0x0 },
+	{ 0x110a7, 0x0 },
+	{ 0x120a0, 0x0 },
+	{ 0x120a1, 0x0 },
+	{ 0x120a2, 0x0 },
+	{ 0x120a3, 0x0 },
+	{ 0x120a4, 0x0 },
+	{ 0x120a5, 0x0 },
+	{ 0x120a6, 0x0 },
+	{ 0x120a7, 0x0 },
+	{ 0x130a0, 0x0 },
+	{ 0x130a1, 0x0 },
+	{ 0x130a2, 0x0 },
+	{ 0x130a3, 0x0 },
+	{ 0x130a4, 0x0 },
+	{ 0x130a5, 0x0 },
+	{ 0x130a6, 0x0 },
+	{ 0x130a7, 0x0 },
+	{ 0x2007c, 0x0 },
+	{ 0x12007c, 0x0 },
+	{ 0x22007c, 0x0 },
+	{ 0x2007d, 0x0 },
+	{ 0x12007d, 0x0 },
+	{ 0x22007d, 0x0 },
+	{ 0x400fd, 0x0 },
+	{ 0x400c0, 0x0 },
+	{ 0x90201, 0x0 },
+	{ 0x190201, 0x0 },
+	{ 0x290201, 0x0 },
+	{ 0x90202, 0x0 },
+	{ 0x190202, 0x0 },
+	{ 0x290202, 0x0 },
+	{ 0x90203, 0x0 },
+	{ 0x190203, 0x0 },
+	{ 0x290203, 0x0 },
+	{ 0x90204, 0x0 },
+	{ 0x190204, 0x0 },
+	{ 0x290204, 0x0 },
+	{ 0x90205, 0x0 },
+	{ 0x190205, 0x0 },
+	{ 0x290205, 0x0 },
+	{ 0x90206, 0x0 },
+	{ 0x190206, 0x0 },
+	{ 0x290206, 0x0 },
+	{ 0x90207, 0x0 },
+	{ 0x190207, 0x0 },
+	{ 0x290207, 0x0 },
+	{ 0x90208, 0x0 },
+	{ 0x190208, 0x0 },
+	{ 0x290208, 0x0 },
+	{ 0x10062, 0x0 },
+	{ 0x10162, 0x0 },
+	{ 0x10262, 0x0 },
+	{ 0x10362, 0x0 },
+	{ 0x10462, 0x0 },
+	{ 0x10562, 0x0 },
+	{ 0x10662, 0x0 },
+	{ 0x10762, 0x0 },
+	{ 0x10862, 0x0 },
+	{ 0x11062, 0x0 },
+	{ 0x11162, 0x0 },
+	{ 0x11262, 0x0 },
+	{ 0x11362, 0x0 },
+	{ 0x11462, 0x0 },
+	{ 0x11562, 0x0 },
+	{ 0x11662, 0x0 },
+	{ 0x11762, 0x0 },
+	{ 0x11862, 0x0 },
+	{ 0x12062, 0x0 },
+	{ 0x12162, 0x0 },
+	{ 0x12262, 0x0 },
+	{ 0x12362, 0x0 },
+	{ 0x12462, 0x0 },
+	{ 0x12562, 0x0 },
+	{ 0x12662, 0x0 },
+	{ 0x12762, 0x0 },
+	{ 0x12862, 0x0 },
+	{ 0x13062, 0x0 },
+	{ 0x13162, 0x0 },
+	{ 0x13262, 0x0 },
+	{ 0x13362, 0x0 },
+	{ 0x13462, 0x0 },
+	{ 0x13562, 0x0 },
+	{ 0x13662, 0x0 },
+	{ 0x13762, 0x0 },
+	{ 0x13862, 0x0 },
+	{ 0x20077, 0x0 },
+	{ 0x10001, 0x0 },
+	{ 0x11001, 0x0 },
+	{ 0x12001, 0x0 },
+	{ 0x13001, 0x0 },
+	{ 0x10040, 0x0 },
+	{ 0x10140, 0x0 },
+	{ 0x10240, 0x0 },
+	{ 0x10340, 0x0 },
+	{ 0x10440, 0x0 },
+	{ 0x10540, 0x0 },
+	{ 0x10640, 0x0 },
+	{ 0x10740, 0x0 },
+	{ 0x10840, 0x0 },
+	{ 0x10030, 0x0 },
+	{ 0x10130, 0x0 },
+	{ 0x10230, 0x0 },
+	{ 0x10330, 0x0 },
+	{ 0x10430, 0x0 },
+	{ 0x10530, 0x0 },
+	{ 0x10630, 0x0 },
+	{ 0x10730, 0x0 },
+	{ 0x10830, 0x0 },
+	{ 0x11040, 0x0 },
+	{ 0x11140, 0x0 },
+	{ 0x11240, 0x0 },
+	{ 0x11340, 0x0 },
+	{ 0x11440, 0x0 },
+	{ 0x11540, 0x0 },
+	{ 0x11640, 0x0 },
+	{ 0x11740, 0x0 },
+	{ 0x11840, 0x0 },
+	{ 0x11030, 0x0 },
+	{ 0x11130, 0x0 },
+	{ 0x11230, 0x0 },
+	{ 0x11330, 0x0 },
+	{ 0x11430, 0x0 },
+	{ 0x11530, 0x0 },
+	{ 0x11630, 0x0 },
+	{ 0x11730, 0x0 },
+	{ 0x11830, 0x0 },
+	{ 0x12040, 0x0 },
+	{ 0x12140, 0x0 },
+	{ 0x12240, 0x0 },
+	{ 0x12340, 0x0 },
+	{ 0x12440, 0x0 },
+	{ 0x12540, 0x0 },
+	{ 0x12640, 0x0 },
+	{ 0x12740, 0x0 },
+	{ 0x12840, 0x0 },
+	{ 0x12030, 0x0 },
+	{ 0x12130, 0x0 },
+	{ 0x12230, 0x0 },
+	{ 0x12330, 0x0 },
+	{ 0x12430, 0x0 },
+	{ 0x12530, 0x0 },
+	{ 0x12630, 0x0 },
+	{ 0x12730, 0x0 },
+	{ 0x12830, 0x0 },
+	{ 0x13040, 0x0 },
+	{ 0x13140, 0x0 },
+	{ 0x13240, 0x0 },
+	{ 0x13340, 0x0 },
+	{ 0x13440, 0x0 },
+	{ 0x13540, 0x0 },
+	{ 0x13640, 0x0 },
+	{ 0x13740, 0x0 },
+	{ 0x13840, 0x0 },
+	{ 0x13030, 0x0 },
+	{ 0x13130, 0x0 },
+	{ 0x13230, 0x0 },
+	{ 0x13330, 0x0 },
+	{ 0x13430, 0x0 },
+	{ 0x13530, 0x0 },
+	{ 0x13630, 0x0 },
+	{ 0x13730, 0x0 },
+	{ 0x13830, 0x0 },
+};
+
+/* P0 message block paremeter for training firmware */
+struct dram_cfg_param lpddr4_fsp0_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54000, 0x0 },
+	{ 0x54001, 0x0 },
+	{ 0x54002, 0x0 },
+	{ 0x54003, 0xbb8 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },//PHY Ron/Rtt
+	{ 0x54006, LPDDR4_PHY_VREF_VALUE },
+	{ 0x54007, 0x0 },
+	{ 0x54008, 0x131f },
+	{ 0x54009, 0xc8 },
+	{ 0x5400a, 0x0 },
+	{ 0x5400b, 0x2 },
+	{ 0x5400c, 0x0 },
+	{ 0x5400d, 0x0 },
+	{ 0x5400e, 0x0 },
+	{ 0x5400f, 0x0 },
+	{ 0x54010, 0x0 },
+	{ 0x54011, 0x0 },
+	{ 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) },
+	{ 0x54013, 0x0 },
+	{ 0x54014, 0x0 },
+	{ 0x54015, 0x0 },
+	{ 0x54016, 0x0 },
+	{ 0x54017, 0x0 },
+	{ 0x54018, 0x0 },
+	{ 0x54019, 0x2dd4 },
+	{ 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 },
+	{ 0x5401b, 0x4d66 },
+	{ 0x5401c, 0x4d08 },
+	{ 0x5401d, 0x0 },
+	{ 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ },
+	{ 0x5401f, 0x2dd4 },
+	{ 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 },
+	{ 0x54021, 0x4d66 },
+	{ 0x54022, 0x4d08 },
+	{ 0x54023, 0x0 },
+	{ 0x54024, LPDDR4_MR22_RANK1/*0x16*/ },
+	{ 0x54025, 0x0 },
+	{ 0x54026, 0x0 },
+	{ 0x54027, 0x0 },
+	{ 0x54028, 0x0 },
+	{ 0x54029, 0x0 },
+	{ 0x5402a, 0x0 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, LPDDR4_CS },
+	{ 0x5402d, 0x0 },
+	{ 0x5402e, 0x0 },
+	{ 0x5402f, 0x0 },
+	{ 0x54030, 0x0 },
+	{ 0x54031, 0x0 },
+	{ 0x54032, 0xd400 },
+	{ 0x54033, (LPDDR4_MR3 << 8) | (0x312d & 0xff) },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x84d },
+	{ 0x54036, 0x4d },
+	{ 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ },
+	{ 0x54038, 0xd400 },
+	{ 0x54039, (LPDDR4_MR3 << 8) | (0x312d & 0xff) },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x84d },
+	{ 0x5403c, 0x4d },
+	{ 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ },
+	{ 0x5403e, 0x0 },
+	{ 0x5403f, 0x0 },
+	{ 0x54040, 0x0 },
+	{ 0x54041, 0x0 },
+	{ 0x54042, 0x0 },
+	{ 0x54043, 0x0 },
+	{ 0x54044, 0x0 },
+	{ 0xd0000, 0x1 },
+};
+
+/* P1 message block paremeter for training firmware */
+struct dram_cfg_param lpddr4_fsp1_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54000, 0x0 },
+	{ 0x54001, 0x0 },
+	{ 0x54002, 0x101 },
+	{ 0x54003, 0x190 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },/* PHY Ron/Rtt */
+	{ 0x54006, LPDDR4_PHY_VREF_VALUE },
+	{ 0x54007, 0x0 },
+	{ 0x54008, 0x121f },
+	{ 0x54009, 0xc8 },
+	{ 0x5400a, 0x0 },
+	{ 0x5400b, 0x2 },
+	{ 0x5400c, 0x0 },
+	{ 0x5400d, 0x0 },
+	{ 0x5400e, 0x0 },
+	{ 0x5400f, 0x0 },
+	{ 0x54010, 0x0 },
+	{ 0x54011, 0x0 },
+	{ 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) },
+	{ 0x54013, 0x0 },
+	{ 0x54014, 0x0 },
+	{ 0x54015, 0x0 },
+	{ 0x54016, 0x0 },
+	{ 0x54017, 0x0 },
+	{ 0x54018, 0x0 },
+	{ 0x54019, 0x84 },
+	{ 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 },
+	{ 0x5401b, 0x4d66 },
+	{ 0x5401c, 0x4d08 },
+	{ 0x5401d, 0x0 },
+	{ 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ },
+	{ 0x5401f, 0x84 },
+	{ 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 },
+	{ 0x54021, 0x4d66 },
+	{ 0x54022, 0x4d08 },
+	{ 0x54023, 0x0 },
+	{ 0x54024, LPDDR4_MR22_RANK1/*0x16*/ },
+	{ 0x54025, 0x0 },
+	{ 0x54026, 0x0 },
+	{ 0x54027, 0x0 },
+	{ 0x54028, 0x0 },
+	{ 0x54029, 0x0 },
+	{ 0x5402a, 0x0 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, LPDDR4_CS },
+	{ 0x5402d, 0x0 },
+	{ 0x5402e, 0x0 },
+	{ 0x5402f, 0x0 },
+	{ 0x54030, 0x0 },
+	{ 0x54031, 0x0 },
+	{ 0x54032, 0x8400 },
+	{ 0x54033, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x84d },
+	{ 0x54036, 0x4d },
+	{ 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ },
+	{ 0x54038, 0x8400 },
+	{ 0x54039, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x84d },
+	{ 0x5403c, 0x4d },
+	{ 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ },
+	{ 0x5403e, 0x0 },
+	{ 0x5403f, 0x0 },
+	{ 0x54040, 0x0 },
+	{ 0x54041, 0x0 },
+	{ 0x54042, 0x0 },
+	{ 0x54043, 0x0 },
+	{ 0x54044, 0x0 },
+	{ 0xd0000, 0x1 },
+};
+
+/* P1 message block paremeter for training firmware */
+struct dram_cfg_param lpddr4_fsp2_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54000, 0x0 },
+	{ 0x54001, 0x0 },
+	{ 0x54002, 0x102 },
+	{ 0x54003, 0x64 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },//PHY Ron/Rtt
+	{ 0x54006, LPDDR4_PHY_VREF_VALUE },
+	{ 0x54007, 0x0 },
+	{ 0x54008, 0x121f },
+	{ 0x54009, 0xc8 },
+	{ 0x5400a, 0x0 },
+	{ 0x5400b, 0x2 },
+	{ 0x5400c, 0x0 },
+	{ 0x5400d, 0x0 },
+	{ 0x5400e, 0x0 },
+	{ 0x5400f, 0x0 },
+	{ 0x54010, 0x0 },
+	{ 0x54011, 0x0 },
+	{ 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) },
+	{ 0x54013, 0x0 },
+	{ 0x54014, 0x0 },
+	{ 0x54015, 0x0 },
+	{ 0x54016, 0x0 },
+	{ 0x54017, 0x0 },
+	{ 0x54018, 0x0 },
+	{ 0x54019, 0x84 },
+	{ 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 },
+	{ 0x5401b, 0x4d66 },
+	{ 0x5401c, 0x4d08 },
+	{ 0x5401d, 0x0 },
+	{ 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ },
+	{ 0x5401f, 0x84 },
+	{ 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 },
+	{ 0x54021, 0x4d66 },
+	{ 0x54022, 0x4d08 },
+	{ 0x54023, 0x0 },
+	{ 0x54024, LPDDR4_MR22_RANK1/*0x16*/ },
+	{ 0x54025, 0x0 },
+	{ 0x54026, 0x0 },
+	{ 0x54027, 0x0 },
+	{ 0x54028, 0x0 },
+	{ 0x54029, 0x0 },
+	{ 0x5402a, 0x0 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, LPDDR4_CS },
+	{ 0x5402d, 0x0 },
+	{ 0x5402e, 0x0 },
+	{ 0x5402f, 0x0 },
+	{ 0x54030, 0x0 },
+	{ 0x54031, 0x0 },
+	{ 0x54032, 0x8400 },
+	{ 0x54033, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x84d },
+	{ 0x54036, 0x4d },
+	{ 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ },
+	{ 0x54038, 0x8400 },
+	{ 0x54039, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x84d },
+	{ 0x5403c, 0x4d },
+	{ 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ },
+	{ 0x5403e, 0x0 },
+	{ 0x5403f, 0x0 },
+	{ 0x54040, 0x0 },
+	{ 0x54041, 0x0 },
+	{ 0x54042, 0x0 },
+	{ 0x54043, 0x0 },
+	{ 0x54044, 0x0 },
+	{ 0xd0000, 0x1 },
+};
+
+/* P0 2D message block paremeter for training firmware */
+struct dram_cfg_param lpddr4_fsp0_2d_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54000, 0x0 },
+	{ 0x54001, 0x0 },
+	{ 0x54002, 0x0 },
+	{ 0x54003, 0xbb8 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },//PHY Ron/Rtt
+	{ 0x54006, LPDDR4_PHY_VREF_VALUE },
+	{ 0x54007, 0x0 },
+	{ 0x54008, 0x61 },
+	{ 0x54009, 0xc8 },
+	{ 0x5400a, 0x0 },
+	{ 0x5400b, 0x2 },
+	{ 0x5400c, 0x0 },
+	{ 0x5400d, 0x0 },
+	{ 0x5400e, 0x0 },
+	{ 0x5400f, 0x100 },
+	{ 0x54010, 0x1f7f },
+	{ 0x54011, 0x0 },
+	{ 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) },
+	{ 0x54013, 0x0 },
+	{ 0x54014, 0x0 },
+	{ 0x54015, 0x0 },
+	{ 0x54016, 0x0 },
+	{ 0x54017, 0x0 },
+	{ 0x54018, 0x0 },
+	{ 0x54019, 0x2dd4 },
+	{ 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 },
+	{ 0x5401b, 0x4d66 },
+	{ 0x5401c, 0x4d08 },
+	{ 0x5401d, 0x0 },
+	{ 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ },
+	{ 0x5401f, 0x2dd4 },
+	{ 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 },
+	{ 0x54021, 0x4d66 },
+	{ 0x54022, 0x4d08 },
+	{ 0x54023, 0x0 },
+	{ 0x54024, LPDDR4_MR22_RANK1/*0x16*/ },
+	{ 0x54025, 0x0 },
+	{ 0x54026, 0x0 },
+	{ 0x54027, 0x0 },
+	{ 0x54028, 0x0 },
+	{ 0x54029, 0x0 },
+	{ 0x5402a, 0x0 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, LPDDR4_CS },
+	{ 0x5402d, 0x0 },
+	{ 0x5402e, 0x0 },
+	{ 0x5402f, 0x0 },
+	{ 0x54030, 0x0 },
+	{ 0x54031, 0x0 },
+	{ 0x54032, 0xd400 },
+	{ 0x54033, (LPDDR4_MR3 << 8) | (0x312d & 0xff) },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x84d },
+	{ 0x54036, 0x4d },
+	{ 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ },
+	{ 0x54038, 0xd400 },
+	{ 0x54039, (LPDDR4_MR3 << 8) | (0x312d & 0xff) },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x84d },
+	{ 0x5403c, 0x4d },
+	{ 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ },
+	{ 0x5403e, 0x0 },
+	{ 0x5403f, 0x0 },
+	{ 0x54040, 0x0 },
+	{ 0x54041, 0x0 },
+	{ 0x54042, 0x0 },
+	{ 0x54043, 0x0 },
+	{ 0x54044, 0x0 },
+	{ 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+struct dram_cfg_param lpddr4_phy_pie[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x90000, 0x10 },
+	{ 0x90001, 0x400 },
+	{ 0x90002, 0x10e },
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+	{ 0x90005, 0x8 },
+	{ 0x90029, 0xb },
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+	{ 0x9002d, 0x448 },
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+	{ 0x9002f, 0x8 },
+	{ 0x90030, 0x478 },
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+	{ 0x90038, 0xf },
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+	{ 0x9003a, 0x139 },
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+	{ 0x9003c, 0x630 },
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+	{ 0x90040, 0x159 },
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+	{ 0x9004c, 0x109 },
+	{ 0x9004d, 0x0 },
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+	{ 0x9005f, 0x8 },
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+	{ 0x90063, 0x630 },
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+	{ 0x900a1, 0x5 },
+	{ 0x900a2, 0x7c0 },
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+	{ 0x900a4, 0x10 },
+	{ 0x900a5, 0x10 },
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+	{ 0x40000, 0x811 },
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+	{ 0x40001, 0x4008 },
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+	{ 0x40022, 0x83 },
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+	{ 0x40063, 0x0 },
+	{ 0x40004, 0x720 },
+	{ 0x40024, 0xf },
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+	{ 0x40005, 0x16 },
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+	{ 0x40007, 0x716 },
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+	{ 0x40009, 0x720 },
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+	{ 0x4000a, 0xe08 },
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+	{ 0x4000c, 0x4028 },
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+	{ 0x4002f, 0x80 },
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+	{ 0x40071, 0x2002 },
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+	{ 0x40035, 0x80 },
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+	{ 0x40056, 0x1200 },
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+	{ 0x40078, 0x0 },
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+	{ 0x40039, 0x1a },
+	{ 0x40059, 0x1300 },
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+	{ 0x4001a, 0x4808 },
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+	{ 0x900c2, 0x8 },
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+	{ 0x900da, 0x50 },
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+	{ 0x900fb, 0x78 },
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+	{ 0x90119, 0x80 },
+	{ 0x9011a, 0x790 },
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+	{ 0x9011d, 0x7aa },
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+	{ 0x90122, 0x8 },
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+	{ 0x90125, 0xf },
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+	{ 0x90132, 0x8080 },
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+	{ 0x90134, 0x8 },
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+	{ 0x90143, 0xf },
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+	{ 0x90146, 0xc },
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+	{ 0x9014f, 0x8 },
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+	{ 0x90152, 0x3 },
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+	{ 0x90160, 0x10c },
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+	{ 0x90162, 0x8138 },
+	{ 0x90163, 0x10c },
+	{ 0x90164, 0x8 },
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+	{ 0x90166, 0x101 },
+	{ 0x90167, 0x8 },
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+	{ 0x9016c, 0x109 },
+	{ 0x9016d, 0xf },
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+	{ 0x90173, 0x47 },
+	{ 0x90174, 0x630 },
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+	{ 0x90176, 0x8 },
+	{ 0x90177, 0x618 },
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+	{ 0x9017e, 0x109 },
+	{ 0x9017f, 0x8 },
+	{ 0x90180, 0x8140 },
+	{ 0x90181, 0x10c },
+	{ 0x90182, 0x0 },
+	{ 0x90183, 0x1 },
+	{ 0x90184, 0x8 },
+	{ 0x90185, 0x8 },
+	{ 0x90186, 0x4 },
+	{ 0x90187, 0x8 },
+	{ 0x90188, 0x8 },
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+	{ 0x9018a, 0x101 },
+	{ 0x90006, 0x0 },
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+	{ 0x90008, 0x8 },
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+	{ 0x9000a, 0x0 },
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+	{ 0x400d0, 0x0 },
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+	{ 0x400d2, 0x105 },
+	{ 0x400d3, 0x107 },
+	{ 0x400d4, 0x10f },
+	{ 0x400d5, 0x202 },
+	{ 0x400d6, 0x20a },
+	{ 0x400d7, 0x20b },
+	{ 0x2003a, 0x2 },
+	{ 0x2000b, 0x5d },
+	{ 0x2000c, 0xbb },
+	{ 0x2000d, 0x753 },
+	{ 0x2000e, 0x2c },
+	{ 0x12000b, 0xc },
+	{ 0x12000c, 0x19 },
+	{ 0x12000d, 0xfa },
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+	{ 0x22000b, 0x3 },
+	{ 0x22000c, 0x6 },
+	{ 0x22000d, 0x3e },
+	{ 0x22000e, 0x10 },
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+	{ 0x9000d, 0x173 },
+	{ 0x9000e, 0x60 },
+	{ 0x9000f, 0x6110 },
+	{ 0x90010, 0x2152 },
+	{ 0x90011, 0xdfbd },
+	{ 0x90012, 0x60 },
+	{ 0x90013, 0x6152 },
+	{ 0x20010, 0x5a },
+	{ 0x20011, 0x3 },
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+	{ 0x40083, 0x12 },
+	{ 0x40084, 0xe0 },
+	{ 0x40085, 0x12 },
+	{ 0x140080, 0xe0 },
+	{ 0x140081, 0x12 },
+	{ 0x140082, 0xe0 },
+	{ 0x140083, 0x12 },
+	{ 0x140084, 0xe0 },
+	{ 0x140085, 0x12 },
+	{ 0x240080, 0xe0 },
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+	{ 0x240082, 0xe0 },
+	{ 0x240083, 0x12 },
+	{ 0x240084, 0xe0 },
+	{ 0x240085, 0x12 },
+	{ 0x400fd, 0xf },
+	{ 0x10011, 0x1 },
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+	{ 0x10013, 0x180 },
+	{ 0x10018, 0x1 },
+	{ 0x10002, 0x6209 },
+	{ 0x100b2, 0x1 },
+	{ 0x101b4, 0x1 },
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+	{ 0x103b4, 0x1 },
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+	{ 0x105b4, 0x1 },
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+	{ 0x108b4, 0x1 },
+	{ 0x11011, 0x1 },
+	{ 0x11012, 0x1 },
+	{ 0x11013, 0x180 },
+	{ 0x11018, 0x1 },
+	{ 0x11002, 0x6209 },
+	{ 0x110b2, 0x1 },
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+	{ 0x118b4, 0x1 },
+	{ 0x12011, 0x1 },
+	{ 0x12012, 0x1 },
+	{ 0x12013, 0x180 },
+	{ 0x12018, 0x1 },
+	{ 0x12002, 0x6209 },
+	{ 0x120b2, 0x1 },
+	{ 0x121b4, 0x1 },
+	{ 0x122b4, 0x1 },
+	{ 0x123b4, 0x1 },
+	{ 0x124b4, 0x1 },
+	{ 0x125b4, 0x1 },
+	{ 0x126b4, 0x1 },
+	{ 0x127b4, 0x1 },
+	{ 0x128b4, 0x1 },
+	{ 0x13011, 0x1 },
+	{ 0x13012, 0x1 },
+	{ 0x13013, 0x180 },
+	{ 0x13018, 0x1 },
+	{ 0x13002, 0x6209 },
+	{ 0x130b2, 0x1 },
+	{ 0x131b4, 0x1 },
+	{ 0x132b4, 0x1 },
+	{ 0x133b4, 0x1 },
+	{ 0x134b4, 0x1 },
+	{ 0x135b4, 0x1 },
+	{ 0x136b4, 0x1 },
+	{ 0x137b4, 0x1 },
+	{ 0x138b4, 0x1 },
+	{ 0x2003a, 0x2 },
+	{ 0xc0080, 0x2 },
+	{ 0xd0000, 0x1 },
+};
+
+struct dram_fsp_msg lpddr4_dram_fsp_msg[] = {
+	{
+		/* P0 3000mts 1D */
+		.drate = 3000,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = lpddr4_fsp0_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_cfg),
+	},
+	{
+		/* P0 3000mts 2D */
+		.drate = 3000,
+		.fw_type = FW_2D_IMAGE,
+		.fsp_cfg = lpddr4_fsp0_2d_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_2d_cfg),
+	},
+	{
+		/* P1 400mts 1D */
+		.drate = 400,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = lpddr4_fsp1_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp1_cfg),
+	},
+	{
+		/* P1 100mts 1D */
+		.drate = 100,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = lpddr4_fsp2_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp2_cfg),
+	},
+};
+
+/* lpddr4 timing config params on EVK board */
+struct dram_timing_info dram_timing = {
+	.ddrc_cfg = lpddr4_ddrc_cfg,
+	.ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg),
+	.ddrphy_cfg = lpddr4_ddrphy_cfg,
+	.ddrphy_cfg_num = ARRAY_SIZE(lpddr4_ddrphy_cfg),
+	.fsp_msg = lpddr4_dram_fsp_msg,
+	.fsp_msg_num = ARRAY_SIZE(lpddr4_dram_fsp_msg),
+	.ddrphy_trained_csr = lpddr4_ddrphy_trained_csr,
+	.ddrphy_trained_csr_num = ARRAY_SIZE(lpddr4_ddrphy_trained_csr),
+	.ddrphy_pie = lpddr4_phy_pie,
+	.ddrphy_pie_num = ARRAY_SIZE(lpddr4_phy_pie),
+};
diff --git a/board/freescale/imx8mm_evk/spl.c b/board/freescale/imx8mm_evk/spl.c
new file mode 100644
index 0000000000..043b5f4342
--- /dev/null
+++ b/board/freescale/imx8mm_evk/spl.c
@@ -0,0 +1,129 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <asm/io.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx8mm_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/arch/ddr.h>
+
+#include <dm/uclass.h>
+#include <dm/device.h>
+#include <dm/uclass-internal.h>
+#include <dm/device-internal.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int spl_board_boot_device(enum boot_device boot_dev_spl)
+{
+	switch (boot_dev_spl) {
+	case SD2_BOOT:
+	case MMC2_BOOT:
+		return BOOT_DEVICE_MMC1;
+	case SD3_BOOT:
+	case MMC3_BOOT:
+		return BOOT_DEVICE_MMC2;
+	default:
+		return BOOT_DEVICE_NONE;
+	}
+}
+
+void spl_dram_init(void)
+{
+	ddr_init(&dram_timing);
+}
+
+void spl_board_init(void)
+{
+	struct udevice *dev;
+	int ret;
+
+	puts("Normal Boot\n");
+
+	ret = uclass_get_device_by_name(UCLASS_CLK,
+					"clock-controller@30380000",
+					&dev);
+	if (ret < 0)
+		printf("Failed to find clock node. Check device tree\n");
+}
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+	/* Just empty function now - can't decide what to choose */
+	debug("%s: %s\n", __func__, name);
+
+	return 0;
+}
+#endif
+
+#define UART_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_FSEL1)
+#define WDOG_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
+
+static iomux_v3_cfg_t const uart_pads[] = {
+	IMX8MM_PAD_UART2_RXD_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	IMX8MM_PAD_UART2_TXD_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const wdog_pads[] = {
+	IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B  | MUX_PAD_CTRL(WDOG_PAD_CTRL),
+};
+
+int board_early_init_f(void)
+{
+	struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
+
+	imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
+
+	set_wdog_reset(wdog);
+
+	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
+
+	return 0;
+}
+
+void board_init_f(ulong dummy)
+{
+	int ret;
+
+	arch_cpu_init();
+
+	init_uart_clk(1);
+
+	board_early_init_f();
+
+	timer_init();
+
+	preloader_console_init();
+
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	ret = spl_init();
+	if (ret) {
+		debug("spl_init() failed: %d\n", ret);
+		hang();
+	}
+
+	enable_tzc380();
+
+	/* DDR initialization */
+	spl_dram_init();
+
+	board_init_r(NULL, 0);
+}
+
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	puts ("resetting ...\n");
+
+	reset_cpu(WDOG1_BASE_ADDR);
+
+	return 0;
+}
-- 
cgit 


From 62f0bfc016d25d22425fc24cd34684d8030f919b Mon Sep 17 00:00:00 2001
From: Peng Fan <peng.fan@nxp.com>
Date: Mon, 23 Sep 2019 10:18:45 +0800
Subject: imx8: update README

After u-boot.cnt is padded to flash.bin automatically by script,
no need to burn the image mannually, so drop the step.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 board/freescale/imx8qm_mek/README  | 1 -
 board/freescale/imx8qxp_mek/README | 1 -
 2 files changed, 2 deletions(-)

(limited to 'board/freescale')

diff --git a/board/freescale/imx8qm_mek/README b/board/freescale/imx8qm_mek/README
index ebf630c446..a187ad8a09 100644
--- a/board/freescale/imx8qm_mek/README
+++ b/board/freescale/imx8qm_mek/README
@@ -41,7 +41,6 @@ Build U-Boot
 ============
 $ make imx8qm_mek_defconfig
 $ make flash.bin
-$ dd if=u-boot.cnt of=flash.bin bs=512 seek=1984
 
 Flash the binary into the SD card
 =================================
diff --git a/board/freescale/imx8qxp_mek/README b/board/freescale/imx8qxp_mek/README
index 1ee0357961..e676e88664 100644
--- a/board/freescale/imx8qxp_mek/README
+++ b/board/freescale/imx8qxp_mek/README
@@ -41,7 +41,6 @@ Build U-Boot
 ============
 $ make imx8qxp_mek_defconfig
 $ make flash.bin
-$ dd if=u-boot.cnt of=flash.bin bs=512 seek=1984
 
 Flash the binary into the SD card
 =================================
-- 
cgit 


From 7b14cc991ba85d2b035479177cc1391ed729abd3 Mon Sep 17 00:00:00 2001
From: Bai Ping <ping.bai@nxp.com>
Date: Thu, 8 Aug 2019 09:59:05 +0000
Subject: imx8mq: Update the ddrc QoS setting for B1 chip

Update the ddrc Qos setting for B1 to align with B0's setting.
Correct the initial clock for dram_pll. This setting will be
overwrite before ddr phy training. Although there is no impact
on the dram init, we still need to correct it to eliminate
confusion.

Signed-off-by: Bai Ping <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Tested-by: Robby Cai <robby.cai@nxp.com>
---
 board/freescale/imx8mq_evk/lpddr4_timing.c | 16 ++++++++++------
 1 file changed, 10 insertions(+), 6 deletions(-)

(limited to 'board/freescale')

diff --git a/board/freescale/imx8mq_evk/lpddr4_timing.c b/board/freescale/imx8mq_evk/lpddr4_timing.c
index f7ea799343..46bc7f8591 100644
--- a/board/freescale/imx8mq_evk/lpddr4_timing.c
+++ b/board/freescale/imx8mq_evk/lpddr4_timing.c
@@ -72,8 +72,10 @@ struct dram_cfg_param lpddr4_ddrc_cfg[] = {
 	{ DDRC_SCHED(0), 0x29511505 },
 	{ DDRC_SCHED1(0), 0x0000002c },
 	{ DDRC_PERFHPR1(0), 0x5900575b },
-	{ DDRC_PERFLPR1(0), 0x00000009 },
-	{ DDRC_PERFWR1(0), 0x02005574 },
+	/* 150T starve and 0x90 max tran len */
+	{ DDRC_PERFLPR1(0), 0x90000096 },
+	/* 300T starve and 0x10 max tran len */
+	{ DDRC_PERFWR1(0), 0x1000012c },
 	{ DDRC_DBG0(0), 0x00000016 },
 	{ DDRC_DBG1(0), 0x00000000 },
 	{ DDRC_DBGCMD(0), 0x00000000 },
@@ -83,10 +85,12 @@ struct dram_cfg_param lpddr4_ddrc_cfg[] = {
 	{ DDRC_PCFGR_0(0), 0x000010f3 },
 	{ DDRC_PCFGW_0(0), 0x000072ff },
 	{ DDRC_PCTRL_0(0), 0x00000001 },
-	{ DDRC_PCFGQOS0_0(0), 0x01110d00 },
-	{ DDRC_PCFGQOS1_0(0), 0x00620790 },
-	{ DDRC_PCFGWQOS0_0(0), 0x00100001 },
-	{ DDRC_PCFGWQOS1_0(0), 0x0000041f },
+	/* disable Read Qos*/
+	{ DDRC_PCFGQOS0_0(0), 0x00000e00 },
+	{ DDRC_PCFGQOS1_0(0), 0x0062ffff },
+	/* disable Write Qos*/
+	{ DDRC_PCFGWQOS0_0(0), 0x00000e00 },
+	{ DDRC_PCFGWQOS1_0(0), 0x0000ffff },
 
 	/* Frequency 1: 400mbps */
 	{ DDRC_FREQ1_DRAMTMG0(0), 0x0d0b010c },
-- 
cgit 


From 80be404a25953ff14743705f2ec7403eb894c6f5 Mon Sep 17 00:00:00 2001
From: Breno Matheus Lima <breno.lima@nxp.com>
Date: Thu, 18 Jul 2019 20:44:31 +0000
Subject: mx6ulevk: Include SDP boot instructions in README

Add instructions on how to boot mx6ul_14x14_evk_defconfig target
using the Serial Download Protocol.

Add examples from uuu and imx_usb_loader tools.

Signed-off-by: Breno Lima <breno.lima@nxp.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
---
 board/freescale/mx6ul_14x14_evk/README | 50 ++++++++++++++++++++++++++++++++++
 1 file changed, 50 insertions(+)

(limited to 'board/freescale')

diff --git a/board/freescale/mx6ul_14x14_evk/README b/board/freescale/mx6ul_14x14_evk/README
index 1edccf688c..e101abe48c 100644
--- a/board/freescale/mx6ul_14x14_evk/README
+++ b/board/freescale/mx6ul_14x14_evk/README
@@ -9,6 +9,9 @@ $ make
 
 This will generate the SPL image called SPL and the u-boot.img.
 
+1. Booting via SDCard
+---------------------
+
 - Flash the SPL image into the micro SD card:
 
 sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync
@@ -30,3 +33,50 @@ switch label numbers reference).
 
 - Insert the micro SD card in the board, power it up and U-Boot messages should
 come up.
+
+2. Booting via Serial Download Protocol (SDP)
+---------------------------------------------
+
+The mx6ulevk board can boot from USB OTG port using the SDP, target will
+enter in SDP mode in case an SD Card is not connect or boot switches are
+set as below:
+
+Sw602: 0 1
+SW601: x x x x
+
+The following tools can be used to boot via SDP, for both tools you must
+connect an USB cable in USB OTG port.
+
+- Method 1: Universal Update Utility (uuu)
+
+The UUU binary can be downloaded in release tab from link below:
+https://github.com/NXPmicro/mfgtools
+
+The following script should be created to boot SPL + u-boot-dtb.img binaries:
+
+  $ cat uuu_script
+    uuu_version 1.1.4
+
+    SDP: boot -f SPL
+    SDPU: write -f u-boot-dtb.img -addr 0x877fffc0
+    SDPU: jump -addr 0x877fffc0
+    SDPU: done
+
+Please note that the address above is calculated based on SYS_TEXT_BASE address:
+
+0x877fffc0 = 0x87800000 (SYS_TEXT_BASE) - 0x40 (U-Boot proper Header size)
+
+Power on the target and run the following command from U-Boot root directory:
+
+  $ sudo ./uuu uuu_script
+
+- Method 2: imx usb loader tool (imx_usb):
+
+The imx_usb_loader tool can be downloaded in link below:
+https://github.com/boundarydevices/imx_usb_loader
+
+Build the source code and run the following commands from U-Boot root
+directory:
+
+  $ sudo ./imx_usb SPL
+  $ sudo ./imx_usb u-boot-dtb.img
-- 
cgit 


From d714a75fd4dcfb0eb8b7e1dd29f43e07113cec0b Mon Sep 17 00:00:00 2001
From: Stefano Babic <sbabic@denx.de>
Date: Fri, 20 Sep 2019 08:47:53 +0200
Subject: imx: replace CONFIG_SECURE_BOOT with CONFIG_IMX_HAB

CONFIG_SECURE_BOOT is too generic and forbids to use it for cross
architecture purposes. If Secure Boot is required for imx, this means to
enable and use the HAB processor in the soc.

Signed-off-by: Stefano Babic <sbabic@denx.de>
---
 board/freescale/mx6slevk/imximage.cfg     | 2 +-
 board/freescale/mx6sllevk/imximage.cfg    | 2 +-
 board/freescale/mx6sxsabresd/imximage.cfg | 2 +-
 board/freescale/mx6ullevk/imximage.cfg    | 2 +-
 board/freescale/mx7dsabresd/imximage.cfg  | 2 +-
 board/freescale/mx7ulp_evk/imximage.cfg   | 2 +-
 6 files changed, 6 insertions(+), 6 deletions(-)

(limited to 'board/freescale')

diff --git a/board/freescale/mx6slevk/imximage.cfg b/board/freescale/mx6slevk/imximage.cfg
index b33bb93f4c..fd71bef286 100644
--- a/board/freescale/mx6slevk/imximage.cfg
+++ b/board/freescale/mx6slevk/imximage.cfg
@@ -24,7 +24,7 @@ BOOT_FROM	sd
 /*
  * Secure boot support
  */
-#ifdef CONFIG_SECURE_BOOT
+#ifdef CONFIG_IMX_HAB
 CSF CONFIG_CSF_SIZE
 #endif
 
diff --git a/board/freescale/mx6sllevk/imximage.cfg b/board/freescale/mx6sllevk/imximage.cfg
index 2dcff0014a..74b3a907bf 100644
--- a/board/freescale/mx6sllevk/imximage.cfg
+++ b/board/freescale/mx6sllevk/imximage.cfg
@@ -27,7 +27,7 @@ BOOT_FROM	sd
 PLUGIN	board/freescale/mx6sllevk/plugin.bin 0x00907000
 #else
 
-#ifdef CONFIG_SECURE_BOOT
+#ifdef CONFIG_IMX_HAB
 CSF CONFIG_CSF_SIZE
 #endif
 
diff --git a/board/freescale/mx6sxsabresd/imximage.cfg b/board/freescale/mx6sxsabresd/imximage.cfg
index 0354bb36e2..28ffb2f8bc 100644
--- a/board/freescale/mx6sxsabresd/imximage.cfg
+++ b/board/freescale/mx6sxsabresd/imximage.cfg
@@ -20,7 +20,7 @@ BOOT_FROM	sd
 /*
  * Secure boot support
  */
-#ifdef CONFIG_SECURE_BOOT
+#ifdef CONFIG_IMX_HAB
 CSF CONFIG_CSF_SIZE
 #endif
 
diff --git a/board/freescale/mx6ullevk/imximage.cfg b/board/freescale/mx6ullevk/imximage.cfg
index 39306d4cd1..40818d0a03 100644
--- a/board/freescale/mx6ullevk/imximage.cfg
+++ b/board/freescale/mx6ullevk/imximage.cfg
@@ -33,7 +33,7 @@ BOOT_FROM	sd
 PLUGIN	board/freescale/mx6ullevk/plugin.bin 0x00907000
 #else
 
-#ifdef CONFIG_SECURE_BOOT
+#ifdef CONFIG_IMX_HAB
 CSF CONFIG_CSF_SIZE
 #endif
 
diff --git a/board/freescale/mx7dsabresd/imximage.cfg b/board/freescale/mx7dsabresd/imximage.cfg
index b72e0cf47c..a0f39c4062 100644
--- a/board/freescale/mx7dsabresd/imximage.cfg
+++ b/board/freescale/mx7dsabresd/imximage.cfg
@@ -24,7 +24,7 @@ BOOT_FROM	sd
 /*
  * Secure boot support
  */
-#ifdef CONFIG_SECURE_BOOT
+#ifdef CONFIG_IMX_HAB
 CSF CONFIG_CSF_SIZE
 #endif
 
diff --git a/board/freescale/mx7ulp_evk/imximage.cfg b/board/freescale/mx7ulp_evk/imximage.cfg
index 43ebc23091..ec3673040b 100644
--- a/board/freescale/mx7ulp_evk/imximage.cfg
+++ b/board/freescale/mx7ulp_evk/imximage.cfg
@@ -27,7 +27,7 @@ BOOT_FROM	sd
 PLUGIN	board/freescale/mx7ulp_evk/plugin.bin 0x2F020000
 #else
 
-#ifdef CONFIG_SECURE_BOOT
+#ifdef CONFIG_IMX_HAB
 CSF CONFIG_CSF_SIZE
 #endif
 /*
-- 
cgit