From 3f0da8748ad777ea2d26f86a041872e5f8c4c4da Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Mon, 4 Feb 2019 13:10:49 -0800 Subject: imx: ventana: remove setup of I2C3 from SPL Do not setup I2C3 in the SPL for Ventana as some devices on that bus (aic3x codecs) can hang the bus causing i2c_setup to spin endlessly until they are put into reset. Removing the setup of I2C3 from the SPL allows the board-specific GPIO to be configured to take care of putting codecs in reset prior to U-Boot setting up I2C3. Signed-off-by: Tim Harvey --- board/gateworks/gw_ventana/gw_ventana_spl.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'board/gateworks/gw_ventana/gw_ventana_spl.c') diff --git a/board/gateworks/gw_ventana/gw_ventana_spl.c b/board/gateworks/gw_ventana/gw_ventana_spl.c index a6ac546e95..80ade9f437 100644 --- a/board/gateworks/gw_ventana/gw_ventana_spl.c +++ b/board/gateworks/gw_ventana/gw_ventana_spl.c @@ -599,9 +599,10 @@ void board_init_f(ulong dummy) /* setup AXI */ gpr_init(); - /* iomux and setup of i2c */ + /* iomux and setup of uart/i2c */ setup_iomux_uart(); - setup_ventana_i2c(); + setup_ventana_i2c(0); + setup_ventana_i2c(1); /* setup GP timer */ timer_init(); -- cgit From d1c3867a08de98e23c375c76076ab301d9783596 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Mon, 4 Feb 2019 13:10:50 -0800 Subject: imx: ventana: add support for GW5905 The GW5905 is single-board tablet computer based on the i.MX6 SoC with the following peripheral set: - eMMC flash (boot device) - microSD expansion - LVDS display connector for off-board 3D+1C with PWM backlight and I2C based touch controller - MIPI camera connector supporting the TRULY CM8487-B500SA-E (OV5640) - ublox EMMY-W1 WiFi/Bluetooth/NFC module (SDIO/UART) - ublox ZOE-M8Q GPS - LSM9DS1 9-DOF IMU - 1x 1-lane miniPCIe socket with USB 2.0 - Gateworks System Controller - Audio jack with TLV320AIC Audio Codec, Speaker AMP and TSA227E Headphone detect - MAX8607 3-mode LED camera flash - DECT ULE module - FUSB302 USB-C PD and ISL9238 Battery charger Signed-off-by: Tim Harvey --- board/gateworks/gw_ventana/gw_ventana_spl.c | 48 ++++++++++++++++++++++++----- 1 file changed, 41 insertions(+), 7 deletions(-) (limited to 'board/gateworks/gw_ventana/gw_ventana_spl.c') diff --git a/board/gateworks/gw_ventana/gw_ventana_spl.c b/board/gateworks/gw_ventana/gw_ventana_spl.c index 80ade9f437..280493dd46 100644 --- a/board/gateworks/gw_ventana/gw_ventana_spl.c +++ b/board/gateworks/gw_ventana/gw_ventana_spl.c @@ -390,6 +390,25 @@ static struct mx6_mmdc_calibration mx6sdl_256x64x2_mmdc_calib = { .p1_mpwrdlctl = 0x3F36363F, }; +static struct mx6_mmdc_calibration mx6sdl_128x64x2_mmdc_calib = { + /* write leveling calibration determine */ + .p0_mpwldectrl0 = 0x001F003F, + .p0_mpwldectrl1 = 0x001F001F, + .p1_mpwldectrl0 = 0x001F004E, + .p1_mpwldectrl1 = 0x0059001F, + /* Read DQS Gating calibration */ + .p0_mpdgctrl0 = 0x42220225, + .p0_mpdgctrl1 = 0x0213021F, + .p1_mpdgctrl0 = 0x022C0242, + .p1_mpdgctrl1 = 0x022C0244, + /* Read Calibration: DQS delay relative to DQ read access */ + .p0_mprddlctl = 0x474A4C4A, + .p1_mprddlctl = 0x48494C45, + /* Write Calibration: DQ/DM delay relative to DQS write access */ + .p0_mpwrdlctl = 0x3F3F3F36, + .p1_mpwrdlctl = 0x3F36363F, +}; + static struct mx6_mmdc_calibration mx6dq_512x32_mmdc_calib = { /* write leveling calibration determine */ .p0_mpwldectrl0 = 0x002A0025, @@ -519,18 +538,33 @@ static void spl_dram_init(int width, int size_mb, int board_model) calib = &mx6sdl_128x64_mmdc_calib; debug("2gB density\n"); } else if (width == 64 && size_mb == 2048) { - mem = &mt41k256m16ha_125; - if (is_cpu_type(MXC_CPU_MX6Q)) - calib = &mx6dq_256x64_mmdc_calib; - else - calib = &mx6sdl_256x64_mmdc_calib; - debug("4gB density\n"); + switch(board_model) { + case GW5905: + /* 8xMT41K128M16 (2GiB) fly-by mirrored 2-chipsels */ + mem = &mt41k128m16jt_125; + debug("2gB density - 2 chipsel\n"); + if (!is_cpu_type(MXC_CPU_MX6Q)) { + calib = &mx6sdl_128x64x2_mmdc_calib; + sysinfo.ncs = 2; + sysinfo.cs_density = 10; /* CS0_END=39 */ + sysinfo.cs1_mirror = 1; /* mirror enabled */ + } + break; + default: + mem = &mt41k256m16ha_125; + if (is_cpu_type(MXC_CPU_MX6Q)) + calib = &mx6dq_256x64_mmdc_calib; + else + calib = &mx6sdl_256x64_mmdc_calib; + debug("4gB density\n"); + break; + } } else if (width == 64 && size_mb == 4096) { switch(board_model) { case GW5903: /* 8xMT41K256M16 (4GiB) fly-by mirrored 2-chipsels */ mem = &mt41k256m16ha_125; - debug("4gB density\n"); + debug("4gB density - 2 chipsel\n"); if (!is_cpu_type(MXC_CPU_MX6Q)) { calib = &mx6sdl_256x64x2_mmdc_calib; sysinfo.ncs = 2; -- cgit From ebe07ef754937ea57c828fea32b1b42b9e797882 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Mon, 4 Feb 2019 13:10:56 -0800 Subject: imx: ventana: add support for GW5908 The GW5908 is a small single board computer based on the i.MX6DL SoC with the same peripheral set as the GW530x but with 1GiB density DRAM (64bit 512MiB). Signed-off-by: Tim Harvey --- board/gateworks/gw_ventana/gw_ventana_spl.c | 44 +++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) (limited to 'board/gateworks/gw_ventana/gw_ventana_spl.c') diff --git a/board/gateworks/gw_ventana/gw_ventana_spl.c b/board/gateworks/gw_ventana/gw_ventana_spl.c index 280493dd46..27f3774140 100644 --- a/board/gateworks/gw_ventana/gw_ventana_spl.c +++ b/board/gateworks/gw_ventana/gw_ventana_spl.c @@ -217,6 +217,46 @@ static struct mx6_mmdc_calibration mx6sdl_64x16_mmdc_calib = { .p0_mpwrdlctl = 0x33382C31, }; +/* TODO: update with calibrated values */ +static struct mx6_mmdc_calibration mx6dq_64x64_mmdc_calib = { + /* write leveling calibration determine */ + .p0_mpwldectrl0 = 0x00190017, + .p0_mpwldectrl1 = 0x00140026, + .p1_mpwldectrl0 = 0x0021001C, + .p1_mpwldectrl1 = 0x0011001D, + /* Read DQS Gating calibration */ + .p0_mpdgctrl0 = 0x43380347, + .p0_mpdgctrl1 = 0x433C034D, + .p1_mpdgctrl0 = 0x032C0324, + .p1_mpdgctrl1 = 0x03310232, + /* Read Calibration: DQS delay relative to DQ read access */ + .p0_mprddlctl = 0x3C313539, + .p1_mprddlctl = 0x37343141, + /* Write Calibration: DQ/DM delay relative to DQS write access */ + .p0_mpwrdlctl = 0x36393C39, + .p1_mpwrdlctl = 0x42344438, +}; + +/* TODO: update with calibrated values */ +static struct mx6_mmdc_calibration mx6sdl_64x64_mmdc_calib = { + /* write leveling calibration determine */ + .p0_mpwldectrl0 = 0x003C003C, + .p0_mpwldectrl1 = 0x001F002A, + .p1_mpwldectrl0 = 0x00330038, + .p1_mpwldectrl1 = 0x0022003F, + /* Read DQS Gating calibration */ + .p0_mpdgctrl0 = 0x42410244, + .p0_mpdgctrl1 = 0x4234023A, + .p1_mpdgctrl0 = 0x022D022D, + .p1_mpdgctrl1 = 0x021C0228, + /* Read Calibration: DQS delay relative to DQ read access */ + .p0_mprddlctl = 0x484A4C4B, + .p1_mprddlctl = 0x4B4D4E4B, + /* Write Calibration: DQ/DM delay relative to DQS write access */ + .p0_mpwrdlctl = 0x33342B32, + .p1_mpwrdlctl = 0x3933332B, +}; + static struct mx6_mmdc_calibration mx6dq_256x16_mmdc_calib = { /* write leveling calibration determine */ .p0_mpwldectrl0 = 0x001B0016, @@ -530,6 +570,10 @@ static void spl_dram_init(int width, int size_mb, int board_model) } else if (width == 64 && size_mb == 512) { mem = &mt41k64m16jt_125; debug("1gB density\n"); + if (is_cpu_type(MXC_CPU_MX6Q)) + calib = &mx6dq_64x64_mmdc_calib; + else + calib = &mx6sdl_64x64_mmdc_calib; } else if (width == 64 && size_mb == 1024) { mem = &mt41k128m16jt_125; if (is_cpu_type(MXC_CPU_MX6Q)) -- cgit