From e25fbe3fe531029dc7b100ea4c79dbc802e17fc2 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Fri, 14 Nov 2014 09:37:00 -0200 Subject: gw_ventana: Move the DCD settings to spl code mx6sabresd_spl.cfg configures CCM registers, GPR registers and CCM_CCOSR. Move the configuration to the spl code. CCM_CCOSR setting is no longer required to get audio functionality in the kernel, so remove such setting. Signed-off-by: Fabio Estevam --- board/gateworks/gw_ventana/clocks.cfg | 42 ----------------------------- board/gateworks/gw_ventana/gw_ventana.cfg | 6 ----- board/gateworks/gw_ventana/gw_ventana_spl.c | 28 +++++++++++++++++++ 3 files changed, 28 insertions(+), 48 deletions(-) delete mode 100644 board/gateworks/gw_ventana/clocks.cfg (limited to 'board/gateworks') diff --git a/board/gateworks/gw_ventana/clocks.cfg b/board/gateworks/gw_ventana/clocks.cfg deleted file mode 100644 index a8118a258e..0000000000 --- a/board/gateworks/gw_ventana/clocks.cfg +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Copyright (C) 2013 Boundary Devices - * Copyright (C) 2013 Gateworks Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - * - * Device Configuration Data (DCD) - * - * Each entry must have the format: - * Addr-type Address Value - * - * where: - * Addr-type register length (1,2 or 4 bytes) - * Address absolute address of the register - * value value to be stored in the register - */ - -/* set the default clock gate to save power */ -DATA 4, CCM_CCGR0, 0x00C03F3F -DATA 4, CCM_CCGR1, 0x0030FC03 -DATA 4, CCM_CCGR2, 0x0FFFC000 -DATA 4, CCM_CCGR3, 0x3FF00000 -DATA 4, CCM_CCGR4, 0xFFFFF300 /* enable NAND/GPMI/BCH clocks */ -DATA 4, CCM_CCGR5, 0x0F0000C3 -DATA 4, CCM_CCGR6, 0x000003FF - -/* enable AXI cache for VDOA/VPU/IPU */ -DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF -/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ -DATA 4, MX6_IOMUXC_GPR6, 0x007F007F -DATA 4, MX6_IOMUXC_GPR7, 0x007F007F - -/* - * Setup CCM_CCOSR register as follows: - * - * cko1_en = 1 --> CKO1 enabled - * cko1_div = 111 --> divide by 8 - * cko1_sel = 1011 --> ahb_clk_root - * - * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz - */ -DATA 4, CCM_CCOSR, 0x000000fb diff --git a/board/gateworks/gw_ventana/gw_ventana.cfg b/board/gateworks/gw_ventana/gw_ventana.cfg index 9ab95f5c93..dd8aa613f0 100644 --- a/board/gateworks/gw_ventana/gw_ventana.cfg +++ b/board/gateworks/gw_ventana/gw_ventana.cfg @@ -21,9 +21,3 @@ BOOT_FROM spi #else BOOT_FROM nand #endif - -#define __ASSEMBLY__ -#include -#include "asm/arch/iomux.h" -#include "asm/arch/crm_regs.h" -#include "clocks.cfg" diff --git a/board/gateworks/gw_ventana/gw_ventana_spl.c b/board/gateworks/gw_ventana/gw_ventana_spl.c index ca35b3cb7e..d6a584745b 100644 --- a/board/gateworks/gw_ventana/gw_ventana_spl.c +++ b/board/gateworks/gw_ventana/gw_ventana_spl.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -392,6 +393,30 @@ static void spl_dram_init(int width, int size_mb, int board_model) mx6_dram_cfg(&sysinfo, calib, mem); } +static void ccgr_init(void) +{ + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + writel(0x00C03F3F, &ccm->CCGR0); + writel(0x0030FC03, &ccm->CCGR1); + writel(0x0FFFC000, &ccm->CCGR2); + writel(0x3FF00000, &ccm->CCGR3); + writel(0x00FFF300, &ccm->CCGR4); + writel(0x0F0000C3, &ccm->CCGR5); + writel(0x000003FF, &ccm->CCGR6); +} + +static void gpr_init(void) +{ + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + + /* enable AXI cache for VDOA/VPU/IPU */ + writel(0xF00000CF, &iomux->gpr[4]); + /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ + writel(0x007F007F, &iomux->gpr[6]); + writel(0x007F007F, &iomux->gpr[7]); +} + /* * called from C runtime startup code (arch/arm/lib/crt0.S:_main) * - we have a stack and a place to store GD, both in SRAM @@ -405,6 +430,9 @@ void board_init_f(ulong dummy) /* setup AIPS and disable watchdog */ arch_cpu_init(); + ccgr_init(); + gpr_init(); + /* iomux and setup of i2c */ board_early_init_f(); i2c_setup_iomux(); -- cgit From 3a7577e5f384f6fdbd8e9b8eefa8573c508fd6de Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 20 Nov 2014 13:17:56 -0200 Subject: gw_ventana: Use the generic spl_sd.cfg gw_ventana can boot from SPI or NAND and both of these interfaces boot from the same 0x400 offset. This means that we could simplify the code and replace the custom gw_ventana.cfg with the generic spl_sd.cfg, as it provides the same boot offset of 0x400. Cc: Tim Harvey Signed-off-by: Fabio Estevam --- board/gateworks/gw_ventana/gw_ventana.cfg | 23 ----------------------- 1 file changed, 23 deletions(-) delete mode 100644 board/gateworks/gw_ventana/gw_ventana.cfg (limited to 'board/gateworks') diff --git a/board/gateworks/gw_ventana/gw_ventana.cfg b/board/gateworks/gw_ventana/gw_ventana.cfg deleted file mode 100644 index dd8aa613f0..0000000000 --- a/board/gateworks/gw_ventana/gw_ventana.cfg +++ /dev/null @@ -1,23 +0,0 @@ -/* - * Copyright (C) 2013 Gateworks Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - * - * Refer doc/README.imximage for more details about how-to configure - * and create imximage boot image - * - * The syntax is taken as close as possible with the kwbimage - */ - -/* image version */ -IMAGE_VERSION 2 - -/* - * Boot Device : one of - * spi, sd, nand, sata - */ -#ifdef CONFIG_SPI_FLASH -BOOT_FROM spi -#else -BOOT_FROM nand -#endif -- cgit