From 372286217f050bfd57695001d59f618c52822f40 Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Fri, 27 May 2016 14:28:05 +0100 Subject: MIPS: Split I & D cache line size config Allow L1 Icache & L1 Dcache line size to be specified separately, since there's no architectural mandate that they be the same. The [id]cache_line_size functions are tidied up to take advantage of the fact that the Kconfig entries are always present to simply check them for zero rather than needing to #ifdef on their presence. Signed-off-by: Paul Burton [removed CONFIG_SYS_CACHELINE_SIZE in include/configs/pic32mzdask.h] Signed-off-by: Daniel Schwierzeck --- board/micronas/vct/Kconfig | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'board/micronas') diff --git a/board/micronas/vct/Kconfig b/board/micronas/vct/Kconfig index 5bb6f03f30..df7c0296c7 100644 --- a/board/micronas/vct/Kconfig +++ b/board/micronas/vct/Kconfig @@ -15,10 +15,13 @@ config SYS_TEXT_BASE config SYS_DCACHE_SIZE default 16384 +config SYS_DCACHE_LINE_SIZE + default 32 + config SYS_ICACHE_SIZE default 16384 -config SYS_CACHELINE_SIZE +config SYS_ICACHE_LINE_SIZE default 32 menu "vct board options" -- cgit