From 625bb5ddb50b243f931262ca8c46956409471917 Mon Sep 17 00:00:00 2001 From: roy zang Date: Thu, 2 Nov 2006 18:52:21 +0800 Subject: Add mpc7448hpc2 (mpc7448 + tsi108) board associated code support. The mpc7448hpc2 board support low level assemble language init code. Signed-off-by: Alexandre Bounine Signed-off-by: Roy Zang --- board/mpc7448hpc2/asm_init.S | 955 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 955 insertions(+) create mode 100644 board/mpc7448hpc2/asm_init.S (limited to 'board/mpc7448hpc2') diff --git a/board/mpc7448hpc2/asm_init.S b/board/mpc7448hpc2/asm_init.S new file mode 100644 index 0000000000..8c15a3d497 --- /dev/null +++ b/board/mpc7448hpc2/asm_init.S @@ -0,0 +1,955 @@ +/***************************************************************************** + * (C) Copyright 2004-05; Tundra Semiconductor Corp. + * + * Added automatic detect of SDC settings + * Copyright (c) 2005 Freescale Semiconductor, Inc. + * Maintainer tie-fei.zang@freescale.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + ****************************************************************************/ + +/*---------------------------------------------------------------------------- + * FILENAME: asm_init.s + * + * Originator: Alex Bounine + * + * DESCRIPTION: + * Initialization code for the Tundra Tsi108 bridge chip + * + *---------------------------------------------------------------------------*/ + +#include +#include + +#include +#include +#include + +#include + +/*=========================================================================== + * Build Configuration Options + */ + +/* #define DISABLE_PBM disables usage of PB Master */ +/* #define SDC_HARDCODED_INIT config SDRAM controller with hardcoded values */ +/* #define SDC_AUTOPRECH_EN enable SDRAM auto precharge */ + +/* =========================================================================== + * Hardcoded SDC settings + */ + +#ifdef SDC_HARDCODED_INIT + +/* Micron MT9HTF6472AY-40EA1 : Unbuffered, 512MB, 400, CL3, Single Rank */ + +#define VAL_SD_REFRESH (0x61A) +#define VAL_SD_TIMING (0x0308336b) +#define VAL_SD_D0_CTRL (0x07100021) /* auto-precharge disabled */ +#define VAL_SD_D0_BAR (0x0FE00000) /* 512MB @ 0x00000000 */ +#define VAL_SD_D1_CTRL (0x07100021) /* auto-precharge disabled */ +#define VAL_SD_D1_BAR (0x0FE00200) /* 512MB @ 0x20000000 */ + +#endif /* SDC_HARDCODED_INIT */ + +/*--------------------------------------------------------------------------- + CPU Configuration: + + CPU Address and Data Parity enables. + +#define CPU_AP +#define CPU_DP + +=========================================================================== + Macros + + !!! Attention !!! Macros LOAD_PTR, LOAD_U32 and LOAD_MEM defined below are + expected to work correctly for the CSR space within 32KB range. + + LOAD_PTR and LOAD_U32 - load specified register with a 32 bit constant. + These macros are absolutely identical except their names. This difference + is provided intentionally for better readable code. + -------------------------------------------------------------------------*/ + +#define LOAD_PTR(reg,const32) \ + addis reg,r0,const32@h; ori reg,reg,const32@l + +#define LOAD_U32(reg,const32) \ + addis reg,r0,const32@h; ori reg,reg,const32@l + +/* LOADMEM initializes a register with the contents of a specified 32-bit memory + location, usually a CSR value.*/ + +#define LOAD_MEM(reg,addr32) \ + addis reg,r0,addr32@ha; lwz reg,addr32@l(reg) + +#ifndef SDC_HARDCODED_INIT +sdc_clk_sync: + /* MHz: 0,0,183,100,133,167,200,233 */ + .long 0,0, 6, 10, 8, 6, 5, 4 /* nSec */ +#endif + +/*=========================================================================== + board_asm_init() - early initialization function. Coded to be portable to + dual-CPU configuration. + Checks CPU number and performs board HW initialization if called for CPU0. + + Registers used: r3,r4,r5,r6,r19,r29 +=========================================================================== + +--------------------------------------------------------------------------- + NOTE: For dual-CPU configuration only CPU0 is allowed to configure Tsi108 + and the rest of the board. Current implementation demonstrates two + possible ways to identify CPU number: + - for MPC74xx platform: uses MSSCR0[ID] bit as defined in UM. + - for PPC750FX/GX boards: uses WHO_AM_I bit reported by Tsi108. +---------------------------------------------------------------------------*/ + + .globl board_asm_init +board_asm_init: + + mflr r19 /* Save LR to be able return later. */ + + bl icache_enable /* Enable icache to reduce reads from flash. */ + + /* Initialize pointer to Tsi108 register space + -------------------------------------------------------------------------*/ + + LOAD_PTR(r29,CFG_TSI108_CSR_RST_BASE)/* r29 - pointer to tsi108 CSR space */ + ori r4,r29,TSI108_PB_REG_OFFSET + + /*------------------------------------------------------------------------- + Check Processor Version Number */ + + mfspr r3, PVR + rlwinm r3,r3,16,16,23 /* get ((Processor Version Number) & 0xFF00) */ + + cmpli 0,0,r3,0x8000 /* MPC74xx */ + bne cont_brd_init + + /* ------------------------------------------ + For MPC744x/5x enable extended BATs[4-7] + Sri: Set HIGH_BAT_EN and XBSEN, and SPD =1 + to disable prefetch + */ + + mfspr r5, HID0 + oris r5, r5, 0x0080 /* Set HID0[HIGH_BAT_EN] bit #8 */ + ori r5, r5, 0x0380 /* Set SPD,XBSEN,SGE bits #22,23,24 */ + mtspr HID0, r5 + isync + sync + + /* Adding code to disable external interventions in MPX bus mode */ + mfspr r3, 1014 + oris r3, r3, 0x0100 /* Set the EIDIS bit in MSSCR0: bit 7 */ + mtspr 1014, r3 + isync + sync + + /* Sri: code to enable FP unit */ + mfmsr r3 + ori r3, r3, 0x2000 + mtmsr r3 + isync + sync + +#if(1) /* def CONFIG_DUAL_CPU + ------------------------------------------------------------------------- + For MPC74xx processor, use MSSCR0[ID] bit to identify CPU number. + */ + + mfspr r3,1014 /* read MSSCR0 */ + rlwinm. r3,r3,27,31,31 /* get processor ID number */ + mtspr SPRN_PIR,r3 /* Save CPU ID */ + sync + bne init_done + b do_tsi108_init + +cont_brd_init: + + /* An alternative method of checking the processor number (in addition + to configuration using MSSCR0[ID] bit on MPC74xx). + Good for IBM PPC750FX/GX. + */ + + lwz r3,PB_BUS_MS_SELECT(r4) /* read PB_ID register */ + rlwinm. r3,r3,24,31,31 /* get processor ID number */ + + bne init_done + +#else + +cont_brd_init: + +#endif /* CONFIG_DUAL_CPU */ + + /* Initialize Tsi108 chip + --------------------------------------------------------------------------- + */ + +do_tsi108_init: + + /*-------------------------------------------------------------------------- + Adjust HLP/Flash parameters. By default after reset the HLP port is set + to support slow devices. Better performance can be achived when an optimal + parameters are used for specific EPROM device. + NOTE: This should be performed ASAP for the emulation platform because + it has 5MHz HLP clocking. + */ + +#ifdef CONFIG_TSI108EMU + ori r4,r29,TSI108_HLP_REG_OFFSET + LOAD_U32(r5,0x434422c0) + stw r5,0x08(r4) /* set HLP B0_CTRL0 */ + sync + LOAD_U32(r5,0xd0012000) + stw r5,0x0c(r4) /* set HLP B0_CTRL1 */ + sync +#endif + + /* ------------------------------------------------------------------------- + * Initialize PB interface. + */ + + ori r4,r29,TSI108_PB_REG_OFFSET + +#if (CFG_TSI108_CSR_BASE != CFG_TSI108_CSR_RST_BASE) + /* Relocate (if required) Tsi108 registers. Set new value for PB_REG_BAR: + * Note we are in the 32-bit address mode. + */ + LOAD_U32(r5,(CFG_TSI108_CSR_BASE | 0x01)) /* value for PB_REG_BAR: BA + EN*/ + stw r5,PB_REG_BAR(r4) + andis. r29,r5,0xFFFF + sync + + ori r4,r29,TSI108_PB_REG_OFFSET +#endif + + /* Set PB Slave configuration register */ + +/* LOAD_U32(r5,0x000024C7) value for PB_SCR: TEA enabled,AACK delay = 7 */ + LOAD_U32(r5,0x00002481) /* value for PB_SCR: TEA enabled,AACK delay = 1 */ + lwz r3, PB_RSR(r4) /* get PB bus mode */ + xori r3,r3,0x0001 /* mask PB_BMODE: r3 -> (0 = 60X, 1 = MPX) */ + rlwimi r5,r3,14,17,17 /* for MPX: set DTI_MODE bit */ + stw r5,PB_SCR(r4) + sync + + /* Configure PB Arbiter */ + + lwz r5,PB_ARB_CTRL(r4) /* Read PB Arbiter Control Register */ + li r3, 0x00F0 /* ARB_PIPELINE_DEP mask */ +#ifdef DISABLE_PBM + ori r3,r3,0x1000 /* add PBM_EN to clear (enabled by default) */ +#endif + andc r5,r5,r3 /* Clear the masked bit fields */ +/* ori r5,r5,0x0040 Set pipeline depth 4 + ori r5,r5,0x0080 Set pipeline depth 8 + ori r5,r5,0x0020 !!!avb Testing: set pipeline depth 2 */ + ori r5,r5,0x0001 + stw r5,PB_ARB_CTRL(r4) + +#if (0) /* currently using the default settings for PBM after reset */ + LOAD_U32(r5,0x) /* value for PB_MCR */ + stw r5,PB_MCR(r4) + sync + + LOAD_U32(r5,0x) /* value for PB_MCMD */ + stw r5,PB_MCMD(r4) + sync +#endif + +/* Disable or enable PVT based on processor bus frequency + 1. Read CG_PWRUP_STATUS register field bits 18,17,16 + 2. See if the value is < or > 133mhz (18:16 = 100) + 3. If > enable PVT + */ + + LOAD_U32(r3,0xC0002234) + lwz r3,0(r3) + rlwinm r3,r3,16,29,31 + + cmpi 0,0,r3,0x0004 + bgt sdc_init + +#ifndef CONFIG_TSI108EMU + /* FIXME: Disable PB calibration control for any real Tsi108 board */ + li r5,0x0101 /* disable calibration control */ + stw r5,PB_PVT_CTRL2(r4) + sync +#endif + +/*--------------------------------------------------------------------------- + Initialize SDRAM controller. +----------------------------------------------------------------------------*/ + +sdc_init: + +#ifndef SDC_HARDCODED_INIT + /* get SDC clock prior doing sdram controller autoconfig */ + ori r4,r29,TSI108_CLK_REG_OFFSET /* r4 - ptr to CG registers */ + lwz r3, CG_PWRUP_STATUS(r4) /* get CG configuration */ + rlwinm r3,r3,12,29,31 /* r3 - SD clk */ + lis r5,sdc_clk_sync@h + ori r5,r5,sdc_clk_sync@l + /* Sri: At this point check if r3 = 001. If yes, + * the memory frequency should be same as the + * MPX bus frequency + */ + cmpi 0,0,r3,0x0001 + bne get_nsec + lwz r6, CG_PWRUP_STATUS(r4) + rlwinm r6,r6,16,29,31 + mr r3,r6 + +get_nsec: + rlwinm r3,r3,2,0,31 + lwzx r9,r5,r3 /* get SD clk rate in nSec */ + /* ATTN: r9 will be used by SPD routine */ +#endif /* !SDC_HARDCODED_INIT */ + + ori r4,r29,TSI108_SD_REG_OFFSET /* r4 - ptr to SDRAM registers */ + + /* Initialize SDRAM controller. SDRAM Size = 512MB, One DIMM. */ + + LOAD_U32(r5,0x00) + stw r5,SD_INT_ENABLE(r4) /* Ensure that interrupts are disabled */ +#ifdef ENABLE_SDRAM_ECC + li r5, 0x01 +#endif /* ENABLE_SDRAM_ECC */ + stw r5,SD_ECC_CTRL(r4) /* Enable/Disable ECC */ + sync + +#ifdef SDC_HARDCODED_INIT /* config sdram controller with hardcoded values */ + + /* First read the CG_PWRUP_STATUS register to get the + memory speed from bits 22,21,20 */ + + LOAD_U32(r3,0xC0002234) + lwz r3,0(r3) + rlwinm r3,r3,12,29,31 + + /* Now first check for 166, then 200, or default */ + + cmpi 0,0,r3,0x0005 + bne check_for_200mhz + + /* set values for 166 Mhz memory speed */ + + /* Set refresh rate and timing parameters */ + LOAD_U32(r5,0x00000515) + stw r5,SD_REFRESH(r4) + LOAD_U32(r5,0x03073368) + stw r5,SD_TIMING(r4) + sync + + /* Initialize DIMM0 control and BAR registers */ + LOAD_U32(r5,VAL_SD_D0_CTRL) /* auto-precharge disabled */ +#ifdef SDC_AUTOPRECH_EN + oris r5,r5,0x0001 /* set auto precharge EN bit */ +#endif + stw r5,SD_D0_CTRL(r4) + LOAD_U32(r5,VAL_SD_D0_BAR) + stw r5,SD_D0_BAR(r4) + sync + + /* Initialize DIMM1 control and BAR registers + * (same as dimm 0, next 512MB, disabled) + */ + LOAD_U32(r5,VAL_SD_D1_CTRL) /* auto-precharge disabled */ +#ifdef SDC_AUTOPRECH_EN + oris r5,r5,0x0001 /* set auto precharge EN bit */ +#endif + stw r5,SD_D1_CTRL(r4) + LOAD_U32(r5,VAL_SD_D1_BAR) + stw r5,SD_D1_BAR(r4) + sync + + b sdc_init_done + +check_for_200mhz: + + cmpi 0,0,r3,0x0006 + bne set_default_values + + /* set values for 200Mhz memory speed */ + + /* Set refresh rate and timing parameters */ + LOAD_U32(r5,0x0000061a) + stw r5,SD_REFRESH(r4) + LOAD_U32(r5,0x03083348) + stw r5,SD_TIMING(r4) + sync + + /* Initialize DIMM0 control and BAR registers */ + LOAD_U32(r5,VAL_SD_D0_CTRL) /* auto-precharge disabled */ +#ifdef SDC_AUTOPRECH_EN + oris r5,r5,0x0001 /* set auto precharge EN bit */ +#endif + stw r5,SD_D0_CTRL(r4) + LOAD_U32(r5,VAL_SD_D0_BAR) + stw r5,SD_D0_BAR(r4) + sync + + /* Initialize DIMM1 control and BAR registers + * (same as dimm 0, next 512MB, disabled) + */ + LOAD_U32(r5,VAL_SD_D1_CTRL) /* auto-precharge disabled */ +#ifdef SDC_AUTOPRECH_EN + oris r5,r5,0x0001 /* set auto precharge EN bit */ +#endif + stw r5,SD_D1_CTRL(r4) + LOAD_U32(r5,VAL_SD_D1_BAR) + stw r5,SD_D1_BAR(r4) + sync + + b sdc_init_done + +set_default_values: + + /* Set refresh rate and timing parameters */ + LOAD_U32(r5,VAL_SD_REFRESH) + stw r5,SD_REFRESH(r4) + LOAD_U32(r5,VAL_SD_TIMING) + stw r5,SD_TIMING(r4) + sync + + /* Initialize DIMM0 control and BAR registers */ + LOAD_U32(r5,VAL_SD_D0_CTRL) /* auto-precharge disabled */ +#ifdef SDC_AUTOPRECH_EN + oris r5,r5,0x0001 /* set auto precharge EN bit */ +#endif + stw r5,SD_D0_CTRL(r4) + LOAD_U32(r5,VAL_SD_D0_BAR) + stw r5,SD_D0_BAR(r4) + sync + + /* Initialize DIMM1 control and BAR registers + * (same as dimm 0, next 512MB, disabled) + */ + LOAD_U32(r5,VAL_SD_D1_CTRL) /* auto-precharge disabled */ +#ifdef SDC_AUTOPRECH_EN + oris r5,r5,0x0001 /* set auto precharge EN bit */ +#endif + stw r5,SD_D1_CTRL(r4) + LOAD_U32(r5,VAL_SD_D1_BAR) + stw r5,SD_D1_BAR(r4) + sync + +#else /* !SDC_HARDCODED_INIT */ + + bl tsi108_sdram_spd /* automatically detect SDC settings */ + +#endif /* SDC_HARDCODED_INIT */ + +sdc_init_done: + +#ifdef DISABLE_PBM + LOAD_U32(r5,0x00000030) /* PB_EN + OCN_EN */ +#else + LOAD_U32(r5,0x00000230) /* PB_EN + OCN_EN + PB/OCN=80/20 */ +#endif /* DISABLE_PBM */ + +#ifdef CONFIG_TSI108EMU + oris r5,r5,0x0010 /* set EMULATION_MODE bit */ +#endif + + stw r5,SD_CTRL(r4) + eieio + sync + + /* Enable SDRAM access */ + + oris r5,r5,0x8000 /* start SDC: set SD_CTRL[ENABLE] bit */ + stw r5,SD_CTRL(r4) + sync + +wait_init_complete: + lwz r5,SD_STATUS(r4) + andi. r5,r5,0x0001 + beq wait_init_complete /* wait until SDRAM initialization is complete */ + +/*--------------------------------------------------------------------------- + Map SDRAM into the processor bus address space +---------------------------------------------------------------------------*/ + + ori r4,r29,TSI108_PB_REG_OFFSET + + /* Setup BARs associated with direct path PB<->SDRAM */ + + /* PB_SDRAM_BAR1: + provides a direct path to the main system memory (cacheable SDRAM) */ + + LOAD_U32(r5, 0x00000011) /* BA=0,Size=512MB, ENable, No Addr.Translation */ + stw r5,PB_SDRAM_BAR1(r4) + sync + + /* Make sure that PB_SDRAM_BAR1 decoder is set + (to allow following immediate read from SDRAM) */ + lwz r5,PB_SDRAM_BAR1(r4) + sync + + /* PB_SDRAM_BAR2: + provides non-cacheable alias (via the direct path) to main system memory. + Size = 512MB, ENable, Addr.Translation - ON, + BA = 0x0_40000000, TA = 0x0_00000000 */ + + LOAD_U32(r5, 0x40010011) + stw r5,PB_SDRAM_BAR2(r4) + sync + + /* Make sure that PB_SDRAM_BAR2 decoder is set + (to allow following immediate read from SDRAM) */ + lwz r5,PB_SDRAM_BAR2(r4) + sync + + +init_done: + + /* All done. Restore LR and return. */ + mtlr r19 + blr + +#if (0) +/*=========================================================================== + init_cpu1 + + This routine enables CPU1 on the dual-processor system. +===========================================================================*/ + + .global enable_cpu1 +enable_cpu1: + + lis r3,Tsi108_Base@ha /* Get Grendel CSR Base Addr */ + addi r3,r3,Tsi108_Base@l + lwz r3,0(r3) /* R3 = CSR Base Addr */ + ori r4,r3,TSI108_PB_REG_OFFSET + lwz r3,PB_ARB_CTRL(r4) /* Read PB Arbiter Control Register */ + ori r3,r3,0x0200 /* Set M1_EN bit */ + stw r3,PB_ARB_CTRL(r4) + + blr +#endif + +/*=========================================================================== + enable_EI + + Enable CPU core external interrupt +===========================================================================*/ + + .global enable_EI +enable_EI: + mfmsr r3 + ori r3,r3,0x8000 /* set EE bit */ + mtmsr r3 + blr + +/*=========================================================================== + disable_EI + + Disable CPU core external interrupt +===========================================================================*/ + + .global disable_EI +disable_EI: + mfmsr r3 + li r4,-32768 /* aka "li r4,0x8000" */ + andc r3,r3,r4 /* clear EE bit */ + mtmsr r3 + blr + +#ifdef ENABLE_SDRAM_ECC +/*=========================================================================== + enable_ECC + + enables SDRAM ECC +===========================================================================*/ + + .global enable_ECC +enable_ECC: + ori r4,r29,TSI108_SD_REG_OFFSET + lwz r3,SD_ECC_CTRL(r4) /* Read SDRAM ECC Control Register */ + ori r3,r3,0x0001 /* Set ECC_EN bit */ + stw r3,SD_ECC_CTRL(r4) + blr + +/*=========================================================================== + clear_ECC_err + + Clears all pending SDRAM ECC errors + (normally after SDRAM scrubbing/initialization) +===========================================================================*/ + + .global clear_ECC_err +clear_ECC_err: + ori r4,r29,TSI108_SD_REG_OFFSET +/* lwz r3,SD_INT_STATUS(r4) Read SDRAM ECC Control Register */ + ori r3,r0,0x0030 /* ECC_UE_INT + ECC_CE_INT bits */ + stw r3,SD_INT_STATUS(r4) + blr + +#endif /* ENABLE_SDRAM_ECC */ + +#ifndef SDC_HARDCODED_INIT + +/******************************************************************** + * SDRAM SPD Support + */ + +#define SD_I2C_CTRL1 (0x400) +#define SD_I2C_CTRL2 (0x404) +#define SD_I2C_RD_DATA (0x408) +#define SD_I2C_WR_DATA (0x40C) + +/* + * SDRAM SPD Support Macros + */ + +#define SPD_DIMM0 (0x00000100) +#define SPD_DIMM1 (0x00000200) /* SPD_DIMM1 was 0x00000000 */ + +#define SPD_RDIMM (0x01) +#define SPD_UDIMM (0x02) + +#define SPD_CAS_3 0x8 +#define SPD_CAS_4 0x10 +#define SPD_CAS_5 0x20 + +#define ERR_NO_DIMM_FOUND (0xdb0) +#define ERR_TRAS_FAIL (0xdb1) +#define ERR_TRCD_FAIL (0xdb2) +#define ERR_TRP_FAIL (0xdb3) +#define ERR_TWR_FAIL (0xdb4) +#define ERR_UNKNOWN_PART (0xdb5) +#define ERR_NRANK_INVALID (0xdb6) +#define ERR_DIMM_SIZE (0xdb7) +#define ERR_ADDR_MODE (0xdb8) +#define ERR_RFRSH_RATE (0xdb9) +#define ERR_DIMM_TYPE (0xdba) +#define ERR_CL_VALUE (0xdbb) +#define ERR_TRFC_FAIL (0xdbc) + +/* READ_SPD requirements: + * byte - byte address in SPD device (0 - 255) + * r3 = will return data read from I2C Byte location + * r4 - unchanged (SDC base addr) + * r5 - clobbered in routine (I2C status) + * r10 - number of DDR slot where first SPD device is detected + */ + +#define READ_SPD(byte_num) \ + addis r3, 0, byte_num@l;\ + or r3, r3, r10;\ + ori r3, r3, 0x0A;\ + stw r3, SD_I2C_CTRL1(r4);\ + li r3, I2C_CNTRL2_START;\ + stw r3, SD_I2C_CTRL2(r4);\ + eieio;\ + sync;\ + li r3, 0x100;\ +1: ;\ + addic. r3, r3, -1;\ + bne 1b;\ +2: ;\ + lwz r5, SD_I2C_CTRL2(r4);\ + rlwinm. r3,r5,0,23,23;\ + bne 2b;\ + rlwinm. r3,r5,0,3,3;\ + lwz r3, SD_I2C_RD_DATA(r4) + +#define SPD_MIN_RFRSH (0x80) +#define SPD_MAX_RFRSH (0x85) + +refresh_rates: /* in nSec */ + .long 15625 /* Normal (0x80) */ + .long 3900 /* Reduced 0.25x (0x81) */ + .long 7800 /* Reduced 0.5x (0x82) */ + .long 31300 /* Extended 2x (0x83) */ + .long 62500 /* Extended 4x (0x84) */ + .long 125000 /* Extended 8x (0x85) */ + +/*=========================================================================== + * tsi108_sdram_spd + * + * Inittializes SDRAM Controller using DDR2 DIMM Serial Presence Detect data + * Uses registers: r4 - SDC base address (not changed) + * r9 - SDC clocking period in nSec + * Changes registers: r3,r5,r6,r7,r8,r10,r11 + *==========================================================================*/ + +tsi108_sdram_spd: + + li r10,SPD_DIMM0 + xor r11,r11,r11 /* DIMM Base Address: starts from 0 */ + +do_first_dimm: + + /************************************** + * Program Refresh Rate Register + */ + + READ_SPD(12) /* get Refresh Rate */ + beq check_next_slot + li r5, ERR_RFRSH_RATE + cmpi 0,0,r3,SPD_MIN_RFRSH + ble spd_fail + cmpi 0,0,r3,SPD_MAX_RFRSH + bgt spd_fail + addi r3,r3,-SPD_MIN_RFRSH + rlwinm r3,r3,2,0,31 + lis r5,refresh_rates@h + ori r5,r5,refresh_rates@l + lwzx r5,r5,r3 /* get refresh rate in nSec */ + divwu r5,r5,r9 /* calculate # of SDC clocks */ + stw r5,SD_REFRESH(r4) /* Set refresh rate */ + sync + + /************************************** + * Program SD Timing Register + */ + + li r7, 0 /* clear r7 prior parameter collection */ + + READ_SPD(20) /* get DIMM type: Registered or Unbuffered */ + beq spd_read_fail + li r5, ERR_DIMM_TYPE + cmpi 0,0,r3,SPD_UDIMM + beq do_cl + cmpi 0,0,r3,SPD_RDIMM + bne spd_fail + oris r7,r7,0x1000 /* set SD_TIMING[DIMM_TYPE] bit */ + +do_cl: + READ_SPD(18) /* Get CAS Latency */ + beq spd_read_fail + li r5,ERR_CL_VALUE + andi. r6,r3,SPD_CAS_3 + beq cl_4 + li r6,3 + b set_cl +cl_4: + andi. r6,r3,SPD_CAS_4 + beq cl_5 + li r6,4 + b set_cl +cl_5: + andi. r6,r3,SPD_CAS_5 + beq spd_fail + li r6,5 +set_cl: + rlwimi r7,r6,24,5,7 + + READ_SPD(30) /* Get tRAS */ + beq spd_read_fail + divwu r6,r3,r9 + mullw r8,r6,r9 + subf. r8,r8,r3 + beq set_tras + addi r6,r6,1 +set_tras: + li r5,ERR_TRAS_FAIL + cmpi 0,0,r6,0x0F /* max supported value */ + bgt spd_fail + rlwimi r7,r6,16,12,15 + + READ_SPD(29) /* Get tRCD */ + beq spd_read_fail + rlwinm r3,r3,30,2,31/* right shift tRCD by 2 bits as per DDR2 spec */ + divwu r6,r3,r9 + mullw r8,r6,r9 + subf. r8,r8,r3 + beq set_trcd + addi r6,r6,1 +set_trcd: + li r5,ERR_TRCD_FAIL + cmpi 0,0,r6,0x07 /* max supported value */ + bgt spd_fail + rlwimi r7,r6,12,17,19 + + READ_SPD(27) /* Get tRP value */ + beq spd_read_fail + rlwinm r3,r3,30,2,31 /* right shift tRP by 2 bits as per DDR2 spec */ + divwu r6,r3,r9 + mullw r8,r6,r9 + subf. r8,r8,r3 + beq set_trp + addi r6,r6,1 +set_trp: + li r5,ERR_TRP_FAIL + cmpi 0,0,r6,0x07 /* max supported value */ + bgt spd_fail + rlwimi r7,r6,8,21,23 + + READ_SPD(36) /* Get tWR value */ + beq spd_read_fail + rlwinm r3,r3,30,2,31 /* right shift tWR by 2 bits as per DDR2 spec */ + divwu r6,r3,r9 + mullw r8,r6,r9 + subf. r8,r8,r3 + beq set_twr + addi r6,r6,1 +set_twr: + addi r6,r6,-1 /* Tsi108 SDC always gives one extra clock */ + li r5,ERR_TWR_FAIL + cmpi 0,0,r6,0x07 /* max supported value */ + bgt spd_fail + rlwimi r7,r6,5,24,26 + + READ_SPD(42) /* Get tRFC */ + beq spd_read_fail + li r5, ERR_TRFC_FAIL + /* Tsi108 spec: tRFC=(tRFC + 1)/2 */ + addi r3,r3,1 + rlwinm. r3,r3,31,1,31 /* divide by 2 */ + beq spd_fail + divwu r6,r3,r9 + mullw r8,r6,r9 + subf. r8,r8,r3 + beq set_trfc + addi r6,r6,1 +set_trfc: + cmpi 0,0,r6,0x1F /* max supported value */ + bgt spd_fail + rlwimi r7,r6,0,27,31 + + stw r7,SD_TIMING(r4) + sync + + /*===================================================================== + * The following two registers are set on per-DIMM basis. + * The SD_REFRESH and SD_TIMING settings are common for both DIMMS + *===================================================================== + */ + +do_each_dimm: + + /***************************************** + * Program SDRAM DIMM Control Register + */ + + li r7, 0 /* clear r7 prior parameter collection */ + + READ_SPD(13) /* Get Primary SDRAM Width */ + beq spd_read_fail + cmpi 0,0,r3,4 /* Check for 4-bit SDRAM */ + beq do_nbank + oris r7,r7,0x0010 /* Set MEM_WIDTH bit */ + +do_nbank: + READ_SPD(17) /* Get Number of banks on SDRAM device */ + beq spd_read_fail + /* Grendel only distinguish betw. 4 or 8-bank memory parts */ + li r5,ERR_UNKNOWN_PART /* non-supported memory part */ + cmpi 0,0,r3,4 + beq do_nrank + cmpi 0,0,r3,8 + bne spd_fail + ori r7,r7,0x1000 + +do_nrank: + READ_SPD(5) /* Get # of Ranks */ + beq spd_read_fail + li r5,ERR_NRANK_INVALID + andi. r6,r3,0x7 /* Use bits [2..0] only */ + beq do_addr_mode + cmpi 0,0,r6,1 + bgt spd_fail + rlwimi r7,r6,8,23,23 + +do_addr_mode: + READ_SPD(4) /* Get # of Column Addresses */ + beq spd_read_fail + li r5, ERR_ADDR_MODE + andi. r3,r3,0x0f /* cut off reserved bits */ + cmpi 0,0,r3,8 + ble spd_fail + cmpi 0,0,r3,15 + bgt spd_fail + addi r6,r3,-8 /* calculate ADDR_MODE parameter */ + rlwimi r7,r6,4,24,27 /* set ADDR_MODE field */ + +set_dimm_ctrl: +#ifdef SDC_AUTOPRECH_EN + oris r7,r7,0x0001 /* set auto precharge EN bit */ +#endif + ori r7,r7,1 /* set ENABLE bit */ + cmpi 0,0,r10,SPD_DIMM0 + bne 1f + stw r7,SD_D0_CTRL(r4) + sync + b set_dimm_bar +1: + stw r7,SD_D1_CTRL(r4) + sync + + + /******************************************** + * Program SDRAM DIMMx Base Address Register + */ + +set_dimm_bar: + READ_SPD(5) /* get # of Ranks */ + beq spd_read_fail + andi.r7,r3,0x7 + addi r7,r7,1 + READ_SPD(31) /* Read DIMM rank density */ + beq spd_read_fail + rlwinm r5,r3,27,29,31 + rlwinm r6,r3,3,24,28 + or r5,r6,r5 /* r5 = Normalized Rank Density byte */ + lis r8, 0x0080 /* 128MB >> 4 */ + mullw r8,r8,r5 /* r8 = (rank_size >> 4) */ + mullw r8,r8,r7 /* r8 = (DIMM_size >> 4) */ + neg r7,r8 + rlwinm r7,r7,28,4,31 + or r7,r7,r11 /* set ADDR field */ + rlwinm r8,r8,12,20,31 + add r11,r11,r8 /* set Base Addr for next DIMM */ + + cmpi 0,0,r10,SPD_DIMM0 + bne set_dimm1_size + stw r7,SD_D0_BAR(r4) + sync + li r10,SPD_DIMM1 + READ_SPD(0) + bne do_each_dimm + b spd_done + +set_dimm1_size: + stw r7,SD_D1_BAR(r4) + sync +spd_done: + blr + +check_next_slot: + cmpi 0,0,r10,SPD_DIMM1 + beq spd_read_fail + li r10,SPD_DIMM1 + b do_first_dimm +spd_read_fail: + ori r3,r0,0xdead + b err_hung +spd_fail: + li r3,0x0bad + sync +err_hung: /* hang here for debugging */ + nop + nop + b err_hung + +#endif /* !SDC_HARDCODED_INIT */ + -- cgit From 27801b8ab11c61b577e45742a515bb3b23b80241 Mon Sep 17 00:00:00 2001 From: roy zang Date: Thu, 2 Nov 2006 18:57:21 +0800 Subject: Add mpc7448hpc2 (mpc7448 + tsi108) board associated code support. Make ,config.mk and link file for the mpc7448hpc2 board. Signed-off-by: Alexandre Bounine Signed-off-by: Roy Zang --- board/mpc7448hpc2/Makefile | 48 +++++++++++++++ board/mpc7448hpc2/config.mk | 28 +++++++++ board/mpc7448hpc2/u-boot.lds | 136 +++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 212 insertions(+) create mode 100644 board/mpc7448hpc2/Makefile create mode 100644 board/mpc7448hpc2/config.mk create mode 100644 board/mpc7448hpc2/u-boot.lds (limited to 'board/mpc7448hpc2') diff --git a/board/mpc7448hpc2/Makefile b/board/mpc7448hpc2/Makefile new file mode 100644 index 0000000000..d5ed01f026 --- /dev/null +++ b/board/mpc7448hpc2/Makefile @@ -0,0 +1,48 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o tsi108_init.o + +SOBJS = asm_init.o + +$(LIB): .depend $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/mpc7448hpc2/config.mk b/board/mpc7448hpc2/config.mk new file mode 100644 index 0000000000..9147a5c880 --- /dev/null +++ b/board/mpc7448hpc2/config.mk @@ -0,0 +1,28 @@ +# +# Copyright (c) 2005 Freescale Semiconductor, Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# Flash address +TEXT_BASE = 0xFFF00000 +# RAM address +#TEXT_BASE = 0x00400000 + +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -maltivec -mabi=altivec -msoft-float diff --git a/board/mpc7448hpc2/u-boot.lds b/board/mpc7448hpc2/u-boot.lds new file mode 100644 index 0000000000..8f24213fc3 --- /dev/null +++ b/board/mpc7448hpc2/u-boot.lds @@ -0,0 +1,136 @@ +/* + * (C) Copyright 2001 + * Josh Huber , Mission Critical Linux, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * u-boot.lds - linker script for U-Boot on mpc7448hpc2 Board. + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/74xx_7xx/start.o (.text) + +/* store the environment in a seperate sector in the boot flash */ +/* . = env_offset; */ +/* common/environment.o(.text) */ + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} -- cgit From 87c4db09699c6b89176b31004afcb83eb1585d47 Mon Sep 17 00:00:00 2001 From: roy zang Date: Thu, 2 Nov 2006 18:59:15 +0800 Subject: Add mpc7448hpc2 (mpc7448 + tsi108) board associated code support. mpc7448hpc2 board support high level code:tsi108 init + mpc7448hpc2. Signed-off-by: Alexandre Bounine Signed-off-by: Roy Zang --- board/mpc7448hpc2/mpc7448hpc2.c | 489 +++++++++++++++++++++++++++++ board/mpc7448hpc2/tsi108_init.c | 662 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 1151 insertions(+) create mode 100644 board/mpc7448hpc2/mpc7448hpc2.c create mode 100644 board/mpc7448hpc2/tsi108_init.c (limited to 'board/mpc7448hpc2') diff --git a/board/mpc7448hpc2/mpc7448hpc2.c b/board/mpc7448hpc2/mpc7448hpc2.c new file mode 100644 index 0000000000..f90a75124a --- /dev/null +++ b/board/mpc7448hpc2/mpc7448hpc2.c @@ -0,0 +1,489 @@ +/* + * (C) Copyright 2005 Freescale Semiconductor, Inc. + * + * Roy Zang + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * modifications for the Tsi108 Emul Board by avb@Tundra + */ + +/* + * board support/init functions for the + * Freescale MPC7448 HPC2 (High-Performance Computing 2 Platform). + */ + +#include +#include <74xx_7xx.h> +#if defined(CONFIG_OF_FLAT_TREE) +#include +extern void ft_cpu_setup(void *blob, bd_t *bd); +#endif + +#undef DEBUG + +extern void flush_data_cache(void); +extern void invalidate_l1_instruction_cache(void); +extern void tsi108_init_f(void); + +int display_mem_map(void); + +void after_reloc(ulong dest_addr) +{ + DECLARE_GLOBAL_DATA_PTR; + + /* + * Jump to the main U-Boot board init code + */ + board_init_r((gd_t *) gd, dest_addr); + /* NOTREACHED */ +} + +/* + * Check Board Identity: + * + * report board type + */ + +int checkboard(void) +{ + int l_type = 0; + + printf("BOARD: %s\n", CFG_BOARD_NAME); + return (l_type); +} + +/* + * Read Processor ID: + * + * report calling processor number + */ + +int read_pid(void) +{ + return 0; /* we are on single CPU platform for a while */ +} + +long int dram_size(int board_type) +{ + return 0x20000000; /* 256M bytes */ +} + +long int initdram(int board_type) +{ + return dram_size(board_type); +} + +/* DRAM check routines copied from gw8260 */ + +#if defined (CFG_DRAM_TEST) + +/*********************************************************************/ +/* NAME: move64() - moves a double word (64-bit) */ +/* */ +/* DESCRIPTION: */ +/* this function performs a double word move from the data at */ +/* the source pointer to the location at the destination pointer. */ +/* */ +/* INPUTS: */ +/* unsigned long long *src - pointer to data to move */ +/* */ +/* OUTPUTS: */ +/* unsigned long long *dest - pointer to locate to move data */ +/* */ +/* RETURNS: */ +/* None */ +/* */ +/* RESTRICTIONS/LIMITATIONS: */ +/* May cloober fr0. */ +/* */ +/*********************************************************************/ +static void move64(unsigned long long *src, unsigned long long *dest) +{ + asm("lfd 0, 0(3)\n\t" /* fpr0 = *scr */ + "stfd 0, 0(4)" /* *dest = fpr0 */ + : : :"fr0"); /* Clobbers fr0 */ + return; +} + +#if defined (CFG_DRAM_TEST_DATA) + +unsigned long long pattern[] = { + 0xaaaaaaaaaaaaaaaaULL, + 0xccccccccccccccccULL, + 0xf0f0f0f0f0f0f0f0ULL, + 0xff00ff00ff00ff00ULL, + 0xffff0000ffff0000ULL, + 0xffffffff00000000ULL, + 0x00000000ffffffffULL, + 0x0000ffff0000ffffULL, + 0x00ff00ff00ff00ffULL, + 0x0f0f0f0f0f0f0f0fULL, + 0x3333333333333333ULL, + 0x5555555555555555ULL +}; + +/*********************************************************************/ +/* NAME: mem_test_data() - test data lines for shorts and opens */ +/* */ +/* DESCRIPTION: */ +/* Tests data lines for shorts and opens by forcing adjacent data */ +/* to opposite states. Because the data lines could be routed in */ +/* an arbitrary manner the must ensure test patterns ensure that */ +/* every case is tested. By using the following series of binary */ +/* patterns every combination of adjacent bits is test regardless */ +/* of routing. */ +/* */ +/* ...101010101010101010101010 */ +/* ...110011001100110011001100 */ +/* ...111100001111000011110000 */ +/* ...111111110000000011111111 */ +/* */ +/* Carrying this out, gives us six hex patterns as follows: */ +/* */ +/* 0xaaaaaaaaaaaaaaaa */ +/* 0xcccccccccccccccc */ +/* 0xf0f0f0f0f0f0f0f0 */ +/* 0xff00ff00ff00ff00 */ +/* 0xffff0000ffff0000 */ +/* 0xffffffff00000000 */ +/* */ +/* The number test patterns will always be given by: */ +/* */ +/* log(base 2)(number data bits) = log2 (64) = 6 */ +/* */ +/* To test for short and opens to other signals on our boards. we */ +/* simply */ +/* test with the 1's complemnt of the paterns as well. */ +/* */ +/* OUTPUTS: */ +/* Displays failing test pattern */ +/* */ +/* RETURNS: */ +/* 0 - Passed test */ +/* 1 - Failed test */ +/* */ +/* RESTRICTIONS/LIMITATIONS: */ +/* Assumes only one one SDRAM bank */ +/* */ +/*********************************************************************/ +int mem_test_data(void) +{ + unsigned long long *pmem = (unsigned long long *)CFG_MEMTEST_START; + unsigned long long temp64; + int num_patterns = sizeof(pattern) / sizeof(pattern[0]); + int i; + unsigned int hi, lo; + + for (i = 0; i < num_patterns; i++) { + move64(&(pattern[i]), pmem); + move64(pmem, &temp64); + + /* hi = (temp64>>32) & 0xffffffff; */ + /* lo = temp64 & 0xffffffff; */ + /* printf("\ntemp64 = 0x%08x%08x", hi, lo); */ + + hi = (pattern[i] >> 32) & 0xffffffff; + lo = pattern[i] & 0xffffffff; + /* printf("\npattern[%d] = 0x%08x%08x", i, hi, lo); */ + + if (temp64 != pattern[i]) { + printf("\n Data Test Failed, pattern 0x%08x%08x", + hi, lo); + return 1; + } + } + + return 0; +} +#endif /* CFG_DRAM_TEST_DATA */ + +#if defined (CFG_DRAM_TEST_ADDRESS) +/*********************************************************************/ +/* NAME: mem_test_address() - test address lines */ +/* */ +/* DESCRIPTION: */ +/* This function performs a test to verify that each word im */ +/* memory is uniquly addressable. The test sequence is as follows: */ +/* */ +/* 1) write the address of each word to each word. */ +/* 2) verify that each location equals its address */ +/* */ +/* OUTPUTS: */ +/* Displays failing test pattern and address */ +/* */ +/* RETURNS: */ +/* 0 - Passed test */ +/* 1 - Failed test */ +/* */ +/* RESTRICTIONS/LIMITATIONS: */ +/* */ +/* */ +/*********************************************************************/ +int mem_test_address(void) +{ + volatile unsigned int *pmem = + (volatile unsigned int *)CFG_MEMTEST_START; + const unsigned int size = (CFG_MEMTEST_END - CFG_MEMTEST_START) / 4; + unsigned int i; + + /* write address to each location */ + for (i = 0; i < size; i++) { + pmem[i] = i; + } + + /* verify each loaction */ + for (i = 0; i < size; i++) { + if (pmem[i] != i) { + printf("\n Address Test Failed at 0x%x", i); + return 1; + } + } + return 0; +} +#endif /* CFG_DRAM_TEST_ADDRESS */ + +#if defined (CFG_DRAM_TEST_WALK) +/*********************************************************************/ +/* NAME: mem_march() - memory march */ +/* */ +/* DESCRIPTION: */ +/* Marches up through memory. At each location verifies rmask if */ +/* read = 1. At each location write wmask if write = 1. Displays */ +/* failing address and pattern. */ +/* */ +/* INPUTS: */ +/* volatile unsigned long long * base - start address of test */ +/* unsigned int size - number of dwords(64-bit) to test */ +/* unsigned long long rmask - read verify mask */ +/* unsigned long long wmask - wrtie verify mask */ +/* short read - verifies rmask if read = 1 */ +/* short write - writes wmask if write = 1 */ +/* */ +/* OUTPUTS: */ +/* Displays failing test pattern and address */ +/* */ +/* RETURNS: */ +/* 0 - Passed test */ +/* 1 - Failed test */ +/* */ +/* RESTRICTIONS/LIMITATIONS: */ +/* */ +/* */ +/*********************************************************************/ +int mem_march(volatile unsigned long long *base, + unsigned int size, + unsigned long long rmask, + unsigned long long wmask, short read, short write) +{ + unsigned int i; + unsigned long long temp; + unsigned int hitemp, lotemp, himask, lomask; + + for (i = 0; i < size; i++) { + if (read != 0) { + /* temp = base[i]; */ + move64((unsigned long long *)&(base[i]), &temp); + if (rmask != temp) { + hitemp = (temp >> 32) & 0xffffffff; + lotemp = temp & 0xffffffff; + himask = (rmask >> 32) & 0xffffffff; + lomask = rmask & 0xffffffff; + + printf("\n Walking one's test failed: \ + address = 0x%08x," "\n\texpected \ + 0x%08x%08x, found 0x%08x%08x", i << 3,\ + himask, lomask, hitemp, lotemp); + return 1; + } + } + if (write != 0) { + /* base[i] = wmask; */ + move64(&wmask, (unsigned long long *)&(base[i])); + } + } + return 0; +} +#endif /* CFG_DRAM_TEST_WALK */ + +/*********************************************************************/ +/* NAME: mem_test_walk() - a simple walking ones test */ +/* */ +/* DESCRIPTION: */ +/* Performs a walking ones through entire physical memory. The */ +/* test uses as series of memory marches, mem_march(), to verify */ +/* and write the test patterns to memory. The test sequence is as */ +/* follows: */ +/* 1) march writing 0000...0001 */ +/* 2) march verifying 0000...0001 , writing 0000...0010 */ +/* 3) repeat step 2 shifting masks left 1 bit each time unitl */ +/* the write mask equals 1000...0000 */ +/* 4) march verifying 1000...0000 */ +/* The test fails if any of the memory marches return a failure. */ +/* */ +/* OUTPUTS: */ +/* Displays which pass on the memory test is executing */ +/* */ +/* RETURNS: */ +/* 0 - Passed test */ +/* 1 - Failed test */ +/* */ +/* RESTRICTIONS/LIMITATIONS: */ +/* */ +/* */ +/*********************************************************************/ +int mem_test_walk(void) +{ + unsigned long long mask; + volatile unsigned long long *pmem = + (volatile unsigned long long *)CFG_MEMTEST_START; + const unsigned long size = (CFG_MEMTEST_END - CFG_MEMTEST_START) / 8; + + unsigned int i; + + mask = 0x01; + + printf("Initial Pass"); + mem_march(pmem, size, 0x0, 0x1, 0, 1); + + printf("\b\b\b\b\b\b\b\b\b\b\b\b"); + printf(" "); + printf(" "); + printf("\b\b\b\b\b\b\b\b\b\b\b\b"); + + for (i = 0; i < 63; i++) { + printf("Pass %2d", i + 2); + if (mem_march(pmem, size, mask, mask << 1, 1, 1) != 0) { + /*printf("mask: 0x%x, pass: %d, ", mask, i); */ + return 1; + } + mask = mask << 1; + printf("\b\b\b\b\b\b\b"); + } + + printf("Last Pass"); + if (mem_march(pmem, size, 0, mask, 0, 1) != 0) { + /* printf("mask: 0x%x", mask); */ + return 1; + } + printf("\b\b\b\b\b\b\b\b\b"); + printf(" "); + printf("\b\b\b\b\b\b\b\b\b"); + + return 0; +} + +/*********************************************************************/ +/* NAME: testdram() - calls any enabled memory tests */ +/* */ +/* DESCRIPTION: */ +/* Runs memory tests if the environment test variables are set to */ +/* 'y'. */ +/* */ +/* INPUTS: */ +/* testdramdata - If set to 'y', data test is run. */ +/* testdramaddress - If set to 'y', address test is run. */ +/* testdramwalk - If set to 'y', walking ones test is run */ +/* */ +/* OUTPUTS: */ +/* None */ +/* */ +/* RETURNS: */ +/* 0 - Passed test */ +/* 1 - Failed test */ +/* */ +/* RESTRICTIONS/LIMITATIONS: */ +/* */ +/* */ +/*********************************************************************/ +int testdram(void) +{ + char *s; + int rundata, runaddress, runwalk; + + s = getenv("testdramdata"); + rundata = (s && (*s == 'y')) ? 1 : 0; + s = getenv("testdramaddress"); + runaddress = (s && (*s == 'y')) ? 1 : 0; + s = getenv("testdramwalk"); + runwalk = (s && (*s == 'y')) ? 1 : 0; + +/* rundata = 1; */ +/* runaddress = 0; */ +/* runwalk = 0; */ + + if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) { + printf("Testing RAM from 0x%08x to 0x%08x ... \ + (don't panic... that will take a moment !!!!)\n", \ + CFG_MEMTEST_START, CFG_MEMTEST_END); + } +#ifdef CFG_DRAM_TEST_DATA + if (rundata == 1) { + printf("Test DATA ... "); + if (mem_test_data () == 1) { + printf("failed \n"); + return 1; + } else + printf("ok \n"); + } +#endif +#ifdef CFG_DRAM_TEST_ADDRESS + if (runaddress == 1) { + printf("Test ADDRESS ... "); + if (mem_test_address () == 1) { + printf("failed \n"); + return 1; + } else + printf("ok \n"); + } +#endif +#ifdef CFG_DRAM_TEST_WALK + if (runwalk == 1) { + printf("Test WALKING ONEs ... "); + if (mem_test_walk() == 1) { + printf("failed \n"); + return 1; + } else + printf("ok \n"); + } +#endif + if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) { + printf("passed\n"); + } + return 0; + +} +#endif /* CFG_DRAM_TEST */ + +#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) +void +ft_board_setup(void *blob, bd_t *bd) +{ + u32 *p; + int len; + + ft_cpu_setup(blob, bd); + + p = ft_get_prop(blob, "/memory/reg", &len); + if (p != NULL) { + *p++ = cpu_to_be32(bd->bi_memstart); + *p = cpu_to_be32(bd->bi_memsize); + } +} +#endif diff --git a/board/mpc7448hpc2/tsi108_init.c b/board/mpc7448hpc2/tsi108_init.c new file mode 100644 index 0000000000..6f517f5a2e --- /dev/null +++ b/board/mpc7448hpc2/tsi108_init.c @@ -0,0 +1,662 @@ +/***************************************************************************** + * (C) Copyright 2003; Tundra Semiconductor Corp. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + *****************************************************************************/ + +/*---------------------------------------------------------------------------- + * FILENAME: tsi108_init.c + * + * Originator: Alex Bounine + * + * DESCRIPTION: + * Initialization code for the Tundra Tsi108 bridge chip + *---------------------------------------------------------------------------*/ + +#include +#include <74xx_7xx.h> +#include +#include +#include +#include + +extern void mpicInit(int verbose); + +/* + * Configuration Options + */ + +typedef struct { + ulong upper; + ulong lower; +} PB2OCN_LUT_ENTRY; + +PB2OCN_LUT_ENTRY pb2ocn_lut1[32] = { + /* 0 - 7 */ + {0x00000000, 0x00000201}, /* PBA=0xE000_0000 -> PCI/X (Byte-Swap) */ + {0x00000000, 0x00000201}, /* PBA=0xE100_0000 -> PCI/X (Byte-Swap) */ + {0x00000000, 0x00000201}, /* PBA=0xE200_0000 -> PCI/X (Byte-Swap) */ + {0x00000000, 0x00000201}, /* PBA=0xE300_0000 -> PCI/X (Byte-Swap) */ + {0x00000000, 0x00000201}, /* PBA=0xE400_0000 -> PCI/X (Byte-Swap) */ + {0x00000000, 0x00000201}, /* PBA=0xE500_0000 -> PCI/X (Byte-Swap) */ + {0x00000000, 0x00000201}, /* PBA=0xE600_0000 -> PCI/X (Byte-Swap) */ + {0x00000000, 0x00000201}, /* PBA=0xE700_0000 -> PCI/X (Byte-Swap) */ + + /* 8 - 15 */ + {0x00000000, 0x00000201}, /* PBA=0xE800_0000 -> PCI/X (Byte-Swap) */ + {0x00000000, 0x00000201}, /* PBA=0xE900_0000 -> PCI/X (Byte-Swap) */ + {0x00000000, 0x00000201}, /* PBA=0xEA00_0000 -> PCI/X (Byte-Swap) */ + {0x00000000, 0x00000201}, /* PBA=0xEB00_0000 -> PCI/X (Byte-Swap) */ + {0x00000000, 0x00000201}, /* PBA=0xEC00_0000 -> PCI/X (Byte-Swap) */ + {0x00000000, 0x00000201}, /* PBA=0xED00_0000 -> PCI/X (Byte-Swap) */ + {0x00000000, 0x00000201}, /* PBA=0xEE00_0000 -> PCI/X (Byte-Swap) */ + {0x00000000, 0x00000201}, /* PBA=0xEF00_0000 -> PCI/X (Byte-Swap) */ + + /* 16 - 23 */ + {0x00000000, 0x00000201}, /* PBA=0xF000_0000 -> PCI/X (Byte-Swap) */ + {0x00000000, 0x00000201}, /* PBA=0xF100_0000 -> PCI/X (Byte-Swap) */ + {0x00000000, 0x00000201}, /* PBA=0xF200_0000 -> PCI/X (Byte-Swap) */ + {0x00000000, 0x00000201}, /* PBA=0xF300_0000 -> PCI/X (Byte-Swap) */ + {0x00000000, 0x00000201}, /* PBA=0xF400_0000 -> PCI/X (Byte-Swap) */ + {0x00000000, 0x00000201}, /* PBA=0xF500_0000 -> PCI/X (Byte-Swap) */ + {0x00000000, 0x00000201}, /* PBA=0xF600_0000 -> PCI/X (Byte-Swap) */ + {0x00000000, 0x00000201}, /* PBA=0xF700_0000 -> PCI/X (Byte-Swap) */ + /* 24 - 31 */ + {0x00000000, 0x00000201}, /* PBA=0xF800_0000 -> PCI/X (Byte-Swap) */ + {0x00000000, 0x00000201}, /* PBA=0xF900_0000 -> PCI/X (Byte-Swap) */ + {0x00000000, 0x00000201}, /* PBA=0xFA00_0000 -> PCI/X PCI I/O (Byte-Swap) */ + {0x00000000, 0x00000201}, /* PBA=0xFB00_0000 -> PCI/X PCI Config (Byte-Swap) */ + + {0x00000000, 0x02000240}, /* PBA=0xFC00_0000 -> HLP */ + {0x00000000, 0x01000240}, /* PBA=0xFD00_0000 -> HLP */ + {0x00000000, 0x03000240}, /* PBA=0xFE00_0000 -> HLP */ + {0x00000000, 0x00000240} /* PBA=0xFF00_0000 -> HLP : (Translation Enabled + Byte-Swap)*/ +}; + +#ifdef CFG_CLK_SPREAD +typedef struct { + ulong ctrl0; + ulong ctrl1; +} PLL_CTRL_SET; + +/* + * Clock Generator SPLL0 initialization values + * PLL0 configuration table for various PB_CLKO freq. + * Uses pre-calculated values for Fs = 30 kHz, D = 0.5% + * Fout depends on required PB_CLKO. Based on Fref = 33 MHz + */ + +static PLL_CTRL_SET pll0_config[8] = { + {0x00000000, 0x00000000}, /* 0: bypass */ + {0x00000000, 0x00000000}, /* 1: reserved */ + {0x00430044, 0x00000043}, /* 2: CG_PB_CLKO = 183 MHz */ + {0x005c0044, 0x00000039}, /* 3: CG_PB_CLKO = 100 MHz */ + {0x005c0044, 0x00000039}, /* 4: CG_PB_CLKO = 133 MHz */ + {0x004a0044, 0x00000040}, /* 5: CG_PB_CLKO = 167 MHz */ + {0x005c0044, 0x00000039}, /* 6: CG_PB_CLKO = 200 MHz */ + {0x004f0044, 0x0000003e} /* 7: CG_PB_CLKO = 233 MHz */ +}; +#endif /* CFG_CLK_SPREAD */ + +/* + * Prosessor Bus Clock (in MHz) defined by CG_PB_SELECT + * (based on recommended Tsi108 reference clock 33MHz) + */ +static int pb_clk_sel[8] = { 0, 0, 183, 100, 133, 167, 200, 233 }; + +/* + * get_board_bus_clk() + * + * returns the bus clock in Hz. + */ +unsigned long get_board_bus_clk(void) +{ + ulong i; + + /* Detect PB clock freq. */ + i = in32(CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PWRUP_STATUS); + i = (i >> 16) & 0x07; /* Get PB PLL multiplier */ + + return pb_clk_sel[i] * 1000000; +} + +/* + * board_early_init_f() + * + * board-specific initialization executed from flash + */ + +int board_early_init_f(void) +{ + DECLARE_GLOBAL_DATA_PTR; + ulong i; + + gd->mem_clk = 0; + i = in32(CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PWRUP_STATUS); + i = (i >> 20) & 0x07; + switch (i) { + case 0: + printf("Using external clock\n"); + break; + case 1: + gd->mem_clk = gd->bus_clk; + break; + case 4: + case 5: + case 6: + gd->mem_clk = pb_clk_sel[i] * 1000000; + break; + default: + printf("Invalid DDR2 clock setting\n"); + return -1; + } + printf("BUS! %d MHz\n", get_board_bus_clk() / 1000000); + printf("MEM! %d MHz\n", gd->mem_clk / 1000000); + return 0; +} + +/* + * board_early_init_r() - Tsi108 initialization function executed right after + * relocation. Contains code that cannot be executed from flash. + */ + +int board_early_init_r(void) +{ + ulong temp, i; + ulong reg_val; + volatile ulong *reg_ptr; + + reg_ptr = + (ulong *) (CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + 0x900); + + for (i = 0; i < 32; i++) { + *reg_ptr++ = 0x00000201; /* SWAP ENABLED */ + *reg_ptr++ = 0x00; + } + + __asm__ __volatile__("eieio"); + __asm__ __volatile__("sync"); + + /* Setup PB_OCN_BAR2: size 256B + ENable @ 0x0_80000000 */ + + out32(CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR2, + 0x80000001); + __asm__ __volatile__("sync"); + + /* Make sure that OCN_BAR2 decoder is set (to allow following immediate + * read from SDRAM) + */ + + temp = in32(CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR2); + __asm__ __volatile__("sync"); + + /* + * Remap PB_OCN_BAR1 to accomodate PCI-bus aperture and EPROM into the + * processor bus address space. Immediately after reset LUT and address + * translation are disabled for this BAR. Now we have to initialize LUT + * and switch from the BOOT mode to the normal operation mode. + * + * The aperture defined by PB_OCN_BAR1 startes at address 0xE0000000 + * and covers 512MB of address space. To allow larger aperture we also + * have to relocate register window of Tsi108 + * + * Initialize LUT (32-entries) prior switching PB_OCN_BAR1 from BOOT + * mode. + * + * initialize pointer to LUT associated with PB_OCN_BAR1 + */ + reg_ptr = + (ulong *) (CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + 0x800); + + for (i = 0; i < 32; i++) { + *reg_ptr++ = pb2ocn_lut1[i].lower; + *reg_ptr++ = pb2ocn_lut1[i].upper; + } + + __asm__ __volatile__("sync"); + + /* Base addresses for Cs0, CS1, CS2, CS3 */ + + out32(CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_ADDR, + 0x00000000); + __asm__ __volatile__("sync"); + + out32(CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_ADDR, + 0x00100000); + __asm__ __volatile__("sync"); + + out32(CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_ADDR, + 0x00200000); + __asm__ __volatile__("sync"); + + out32(CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_ADDR, + 0x00300000); + __asm__ __volatile__("sync"); + + /* Masks for HLP banks */ + + out32(CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_MASK, + 0xFFF00000); + __asm__ __volatile__("sync"); + + out32(CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_MASK, + 0xFFF00000); + __asm__ __volatile__("sync"); + + out32(CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_MASK, + 0xFFF00000); + __asm__ __volatile__("sync"); + + out32(CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_MASK, + 0xFFF00000); + __asm__ __volatile__("sync"); + + /* Set CTRL0 values for banks */ + + out32(CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_CTRL0, + 0x7FFC44C2); + __asm__ __volatile__("sync"); + + out32(CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_CTRL0, + 0x7FFC44C0); + __asm__ __volatile__("sync"); + + out32(CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_CTRL0, + 0x7FFC44C0); + __asm__ __volatile__("sync"); + + out32(CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_CTRL0, + 0x7FFC44C2); + __asm__ __volatile__("sync"); + + /* Set banks to latched mode, enabled, and other default settings */ + + out32(CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_CTRL1, + 0x7C0F2000); + __asm__ __volatile__("sync"); + + out32(CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_CTRL1, + 0x7C0F2000); + __asm__ __volatile__("sync"); + + out32(CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_CTRL1, + 0x7C0F2000); + __asm__ __volatile__("sync"); + + out32(CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_CTRL1, + 0x7C0F2000); + __asm__ __volatile__("sync"); + + /* + * Set new value for PB_OCN_BAR1: switch from BOOT to LUT mode. + * value for PB_OCN_BAR1: (BA-0xE000_0000 + size 512MB + ENable) + */ + out32(CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR1, + 0xE0000011); + __asm__ __volatile__("sync"); + + /* Make sure that OCN_BAR2 decoder is set (to allow following + * immediate read from SDRAM) + */ + + temp = in32(CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR1); + __asm__ __volatile__("sync"); + + /* + * SRI: At this point we have enabled the HLP banks. That means we can + * now read from the NVRAM and initialize the environment variables. + * We will over-ride the env_init called in board_init_f + * This is really a work-around because, the HLP bank 1 + * where NVRAM resides is not visible during board_init_f + * (lib_ppc/board.c) + * Alternatively, we could use the I2C EEPROM at start-up to configure + * and enable all HLP banks and not just HLP 0 as is being done for + * Taiga Rev. 2. + */ + + env_init(); + +#ifndef DISABLE_PBM + + /* + * For IBM processors we have to set Address-Only commands generated + * by PBM that are different from ones set after reset. + */ + + temp = get_cpu_type(); + + if ((CPU_750FX == temp) || (CPU_750GX == temp)) { + out32(CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_MCMD, + 0x00009955); + } +#endif /* DISABLE_PBM */ + +#ifdef CONFIG_PCI + /* + * Initialize PCI/X block + */ + + /* Map PCI/X Configuration Space (16MB @ 0x0_FE000000) */ + out32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_BAR0_UPPER, + 0); + __asm__ __volatile__("sync"); + + out32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_BAR0, + 0xFB000001); + __asm__ __volatile__("sync"); + + /* Set Bus Number for the attached PCI/X bus (we will use 0 for NB) */ + + temp = + in32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PCIX_STAT); + + temp &= ~0xFF00; /* Clear the BUS_NUM field */ + + out32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PCIX_STAT, + temp); + + /* Map PCI/X IO Space (64KB @ 0x0_FD000000) takes one 16MB LUT entry */ + + out32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_IO_UPPER, + 0); + __asm__ __volatile__("sync"); + + /* This register is on the PCI side to interpret the address it receives + * and maps it as a IO address. + */ + + out32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_IO, + 0xFA000001); + __asm__ __volatile__("sync"); + + /* + * Map PCI/X Memory Space + * + * Transactions directed from OCM to PCI Memory Space are directed + * from PB to PCI + * unchanged (as defined by PB_OCN_BAR1,2 and LUT settings). + * If address remapping is required the corresponding PCI_PFAB_MEM32 + * and PCI_PFAB_PFMx register groups have to be configured. + * + * Map the path from the PCI/X bus into the system memory + * + * The memory mapped window assotiated with PCI P2O_BAR2 provides + * access to the system memory without address remapping. + * All system memory is opened for accesses initiated by PCI/X bus + * masters. + * + * Initialize LUT associated with PCI P2O_BAR2 + * + * set pointer to LUT associated with PCI P2O_BAR2 + */ + + reg_ptr = + (ulong *) (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + 0x500); + +#ifdef DISABLE_PBM + + /* In case when PBM is disabled (no HW supported cache snoopng on PB) + * P2O_BAR2 is directly mapped into the system memory without address + * translation. + */ + + reg_val = 0x00000004; /* SDRAM port + NO Addr_Translation */ + + for (i = 0; i < 32; i++) { + *reg_ptr++ = reg_val; /* P2O_BAR2_LUTx */ + *reg_ptr++ = 0; /* P2O_BAR2_LUT_UPPERx */ + } + + /* value for PCI BAR2 (size = 512MB, Enabled, No Addr. Translation) */ + reg_val = 0x00007500; +#else + + reg_val = 0x00000002; /* Destination port = PBM */ + + for (i = 0; i < 32; i++) { + *reg_ptr++ = reg_val; /* P2O_BAR2_LUTx */ +/* P2O_BAR2_LUT_UPPERx : Set data swapping mode for PBM (byte swapping) */ + *reg_ptr++ = 0x40000000; +/* offset = 16MB, address translation is enabled to allow byte swapping */ + reg_val += 0x01000000; + } + +/* value for PCI BAR2 (size = 512MB, Enabled, Address Translation Enabled) */ + reg_val = 0x00007100; +#endif + + __asm__ __volatile__("eieio"); + __asm__ __volatile__("sync"); + + out32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_PAGE_SIZES, + reg_val); + __asm__ __volatile__("sync"); + + /* Set 64-bit PCI bus address for system memory + * ( 0 is the best choice for easy mapping) + */ + + out32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR2, + 0x00000000); + out32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR2_UPPER, + 0x00000000); + __asm__ __volatile__("sync"); + +#ifndef DISABLE_PBM + /* + * The memory mapped window assotiated with PCI P2O_BAR3 provides + * access to the system memory using SDRAM OCN port and address + * translation. This is alternative way to access SDRAM from PCI + * required for Tsi108 emulation testing. + * All system memory is opened for accesses initiated by + * PCI/X bus masters. + * + * Initialize LUT associated with PCI P2O_BAR3 + * + * set pointer to LUT associated with PCI P2O_BAR3 + */ + reg_ptr = + (ulong *) (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + 0x600); + + reg_val = 0x00000004; /* Destination port = SDC */ + + for (i = 0; i < 32; i++) { + *reg_ptr++ = reg_val; /* P2O_BAR3_LUTx */ + +/* P2O_BAR3_LUT_UPPERx : Set data swapping mode for PBM (byte swapping) */ + *reg_ptr++ = 0; + +/* offset = 16MB, address translation is enabled to allow byte swapping */ + reg_val += 0x01000000; + } + + __asm__ __volatile__("eieio"); + __asm__ __volatile__("sync"); + + /* Configure PCI P2O_BAR3 (size = 512MB, Enabled) */ + + reg_val = + in32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + + PCI_P2O_PAGE_SIZES); + reg_val &= ~0x00FF; + reg_val |= 0x0071; + out32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_PAGE_SIZES, + reg_val); + __asm__ __volatile__("sync"); + + /* Set 64-bit base PCI bus address for window (0x20000000) */ + + out32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR3_UPPER, + 0x00000000); + out32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR3, + 0x20000000); + __asm__ __volatile__("sync"); + +#endif /* !DISABLE_PBM */ + +#ifdef ENABLE_PCI_CSR_BAR + /* open if required access to Tsi108 CSRs from the PCI/X bus */ + /* enable BAR0 on the PCI/X bus */ + reg_val = + in32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_MISC_CSR); + reg_val |= 0x02; + out32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_MISC_CSR, + reg_val); + __asm__ __volatile__("sync"); + + out32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR0_UPPER, + 0x00000000); + out32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR0, + CFG_TSI108_CSR_BASE); + __asm__ __volatile__("sync"); + +#endif + + /* + * Finally enable PCI/X Bus Master and Memory Space access + */ + + reg_val = in32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_CSR); + reg_val |= 0x06; + out32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_CSR, reg_val); + __asm__ __volatile__("sync"); + +#endif /* CONFIG_PCI */ + + /* + * Initialize MPIC outputs (interrupt pins): + * Interrupt routing on the Grendel Emul. Board: + * PB_INT[0] -> INT (CPU0) + * PB_INT[1] -> INT (CPU1) + * PB_INT[2] -> MCP (CPU0) + * PB_INT[3] -> MCP (CPU1) + * Set interrupt controller outputs as Level_Sensitive/Active_Low + */ + out32(CFG_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(0), 0x02); + out32(CFG_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(1), 0x02); + out32(CFG_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(2), 0x02); + out32(CFG_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(3), 0x02); + __asm__ __volatile__("sync"); + + /* + * Ensure that Machine Check exception is enabled + * We need it to support PCI Bus probing (configuration reads) + */ + + reg_val = mfmsr(); + mtmsr(reg_val | MSR_ME); + + return 0; +} + +/* + * Needed to print out L2 cache info + * used in the misc_init_r function + */ + +unsigned long get_l2cr(void) +{ + unsigned long l2controlreg; + asm volatile ("mfspr %0, 1017":"=r" (l2controlreg):); + return l2controlreg; +} + +/* + * misc_init_r() + * + * various things to do after relocation + * + */ + +int misc_init_r(void) +{ + DECLARE_GLOBAL_DATA_PTR; +#ifdef CFG_CLK_SPREAD /* Initialize Spread-Spectrum Clock generation */ + ulong i; + + /* Ensure that Spread-Spectrum is disabled */ + out32(CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL0, 0); + out32(CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0, 0); + + /* Initialize PLL1: CG_PCI_CLK , internal OCN_CLK + * Uses pre-calculated value for Fout = 800 MHz, Fs = 30 kHz, D = 0.5% + */ + + out32(CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0, 0x002e0044); /* D = 0.25% */ + out32(CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL1, 0x00000039); /* BWADJ */ + + /* Initialize PLL0: CG_PB_CLKO */ + /* Detect PB clock freq. */ + i = in32(CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PWRUP_STATUS); + i = (i >> 16) & 0x07; /* Get PB PLL multiplier */ + + out32(CFG_TSI108_CSR_BASE + + TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL0, pll0_config[i].ctrl0); + out32(CFG_TSI108_CSR_BASE + + TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL1, pll0_config[i].ctrl1); + + /* Wait and set SSEN for both PLL0 and 1 */ + udelay(1000); + out32(CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0, 0x802e0044); /* D=0.25% */ + out32(CFG_TSI108_CSR_BASE + + TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL0, + 0x80000000 | pll0_config[i].ctrl0); +#endif /* CFG_CLK_SPREAD */ + +#ifdef CFG_L2 + l2cache_enable(); +#endif + printf("BUS: %d MHz\n", gd->bus_clk / 1000000); + printf("MEM: %d MHz\n", gd->mem_clk / 1000000); + + /* + * All the information needed to print the cache details is avaiblable + * at this point i.e. above call to l2cache_enable is the very last + * thing done with regards to enabling diabling the cache. + * So this seems like a good place to print all this information + */ + + printf("CACHE: "); + switch (get_cpu_type()) { + case CPU_7447A: + printf("L1 Instruction cache - 32KB 8-way"); + (get_hid0() & (1 << 15)) ? printf(" ENABLED\n") : + printf(" DISABLED\n"); + printf(" L1 Data cache - 32KB 8-way"); + (get_hid0() & (1 << 14)) ? printf(" ENABLED\n") : + printf(" DISABLED\n"); + printf(" Unified L2 cache - 512KB 8-way"); + (get_l2cr() & (1 << 31)) ? printf(" ENABLED\n") : + printf(" DISABLED\n"); + printf("\n"); + break; + + case CPU_7448: + printf("L1 Instruction cache - 32KB 8-way"); + (get_hid0() & (1 << 15)) ? printf(" ENABLED\n") : + printf(" DISABLED\n"); + printf(" L1 Data cache - 32KB 8-way"); + (get_hid0() & (1 << 14)) ? printf(" ENABLED\n") : + printf(" DISABLED\n"); + printf(" Unified L2 cache - 1MB 8-way"); + (get_l2cr() & (1 << 31)) ? printf(" ENABLED\n") : + printf(" DISABLED\n"); + break; + default: + break; + } + return 0; +} -- cgit From 99c09c4dec34f77c243bf51bea532e3f339410ad Mon Sep 17 00:00:00 2001 From: roy zang Date: Fri, 3 Nov 2006 13:07:36 +0800 Subject: Change the TEXT_BASE from 0xFFF00000 to 0xFF000000. Both work. 0xFF000000 seems more reasonable. --- board/mpc7448hpc2/config.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'board/mpc7448hpc2') diff --git a/board/mpc7448hpc2/config.mk b/board/mpc7448hpc2/config.mk index 9147a5c880..2e58858c4f 100644 --- a/board/mpc7448hpc2/config.mk +++ b/board/mpc7448hpc2/config.mk @@ -21,7 +21,7 @@ # # Flash address -TEXT_BASE = 0xFFF00000 +TEXT_BASE = 0xFF000000 # RAM address #TEXT_BASE = 0x00400000 -- cgit From ee311214e0d216f904feea269599d0934bf71f23 Mon Sep 17 00:00:00 2001 From: roy zang Date: Fri, 1 Dec 2006 11:47:36 +0800 Subject: Clean up the code according to codestyle: (1) remove some C++ comments. (2) remove trailing white space. (3) remove trailing empty line. (4) Indentation by table. (5) remove {} in one line condition. (6) add space before '(' in function call. Remove some weird printf () output. Add necessary comments. Modified Makefile to support building in a separate directory. --- board/mpc7448hpc2/Makefile | 20 +- board/mpc7448hpc2/asm_init.S | 1143 +++++++++++++++++++-------------------- board/mpc7448hpc2/mpc7448hpc2.c | 152 +++--- board/mpc7448hpc2/tsi108_init.c | 421 +++++++------- 4 files changed, 851 insertions(+), 885 deletions(-) (limited to 'board/mpc7448hpc2') diff --git a/board/mpc7448hpc2/Makefile b/board/mpc7448hpc2/Makefile index d5ed01f026..e3d757d5dd 100644 --- a/board/mpc7448hpc2/Makefile +++ b/board/mpc7448hpc2/Makefile @@ -23,26 +23,30 @@ include $(TOPDIR)/config.mk -LIB = lib$(BOARD).a +LIB = $(obj)lib$(BOARD).a -OBJS = $(BOARD).o tsi108_init.o +COBJS := $(BOARD).o tsi108_init.o +SOBJS := asm_init.o -SOBJS = asm_init.o +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) -$(LIB): .depend $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) $(SOBJS) +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) clean: rm -f $(SOBJS) $(OBJS) +.PHONY: distclean distclean: clean rm -f $(LIB) core *.bak .depend ######################################################################### -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ +# defines $(obj).depend target +include $(SRCTREE)/rules.mk -sinclude .depend +sinclude ($obj).depend ######################################################################### diff --git a/board/mpc7448hpc2/asm_init.S b/board/mpc7448hpc2/asm_init.S index 8c15a3d497..a7a40a134c 100644 --- a/board/mpc7448hpc2/asm_init.S +++ b/board/mpc7448hpc2/asm_init.S @@ -1,10 +1,10 @@ -/***************************************************************************** +/* * (C) Copyright 2004-05; Tundra Semiconductor Corp. - * + * * Added automatic detect of SDC settings * Copyright (c) 2005 Freescale Semiconductor, Inc. * Maintainer tie-fei.zang@freescale.com - * + * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of @@ -19,9 +19,9 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA - ****************************************************************************/ + */ -/*---------------------------------------------------------------------------- +/* * FILENAME: asm_init.s * * Originator: Alex Bounine @@ -29,7 +29,7 @@ * DESCRIPTION: * Initialization code for the Tundra Tsi108 bridge chip * - *---------------------------------------------------------------------------*/ + */ #include #include @@ -40,15 +40,15 @@ #include -/*=========================================================================== +/* * Build Configuration Options */ -/* #define DISABLE_PBM disables usage of PB Master */ -/* #define SDC_HARDCODED_INIT config SDRAM controller with hardcoded values */ -/* #define SDC_AUTOPRECH_EN enable SDRAM auto precharge */ +/* #define DISABLE_PBM disables usage of PB Master */ +/* #define SDC_HARDCODED_INIT config SDRAM controller with hardcoded values */ +/* #define SDC_AUTOPRECH_EN enable SDRAM auto precharge */ -/* =========================================================================== +/* * Hardcoded SDC settings */ @@ -56,571 +56,543 @@ /* Micron MT9HTF6472AY-40EA1 : Unbuffered, 512MB, 400, CL3, Single Rank */ -#define VAL_SD_REFRESH (0x61A) -#define VAL_SD_TIMING (0x0308336b) -#define VAL_SD_D0_CTRL (0x07100021) /* auto-precharge disabled */ -#define VAL_SD_D0_BAR (0x0FE00000) /* 512MB @ 0x00000000 */ -#define VAL_SD_D1_CTRL (0x07100021) /* auto-precharge disabled */ -#define VAL_SD_D1_BAR (0x0FE00200) /* 512MB @ 0x20000000 */ +#define VAL_SD_REFRESH (0x61A) +#define VAL_SD_TIMING (0x0308336b) +#define VAL_SD_D0_CTRL (0x07100021) /* auto-precharge disabled */ +#define VAL_SD_D0_BAR (0x0FE00000) /* 512MB @ 0x00000000 */ +#define VAL_SD_D1_CTRL (0x07100021) /* auto-precharge disabled */ +#define VAL_SD_D1_BAR (0x0FE00200) /* 512MB @ 0x20000000 */ #endif /* SDC_HARDCODED_INIT */ -/*--------------------------------------------------------------------------- +/* CPU Configuration: CPU Address and Data Parity enables. #define CPU_AP #define CPU_DP +*/ -=========================================================================== - Macros - - !!! Attention !!! Macros LOAD_PTR, LOAD_U32 and LOAD_MEM defined below are - expected to work correctly for the CSR space within 32KB range. - - LOAD_PTR and LOAD_U32 - load specified register with a 32 bit constant. - These macros are absolutely identical except their names. This difference - is provided intentionally for better readable code. - -------------------------------------------------------------------------*/ +/* + * Macros + * !!! Attention !!! Macros LOAD_PTR, LOAD_U32 and LOAD_MEM defined below are + * expected to work correctly for the CSR space within 32KB range. + * + * LOAD_PTR and LOAD_U32 - load specified register with a 32 bit constant. + * These macros are absolutely identical except their names. This difference + * is provided intentionally for better readable code. + */ #define LOAD_PTR(reg,const32) \ - addis reg,r0,const32@h; ori reg,reg,const32@l + addis reg,r0,const32@h; ori reg,reg,const32@l #define LOAD_U32(reg,const32) \ - addis reg,r0,const32@h; ori reg,reg,const32@l + addis reg,r0,const32@h; ori reg,reg,const32@l -/* LOADMEM initializes a register with the contents of a specified 32-bit memory - location, usually a CSR value.*/ +/* LOADMEM initializes a register with the contents of a specified 32-bit + * memory location, usually a CSR value. + */ #define LOAD_MEM(reg,addr32) \ - addis reg,r0,addr32@ha; lwz reg,addr32@l(reg) + addis reg,r0,addr32@ha; lwz reg,addr32@l(reg) #ifndef SDC_HARDCODED_INIT sdc_clk_sync: /* MHz: 0,0,183,100,133,167,200,233 */ - .long 0,0, 6, 10, 8, 6, 5, 4 /* nSec */ + .long 0, 0, 6, 10, 8, 6, 5, 4 /* nSec */ #endif -/*=========================================================================== - board_asm_init() - early initialization function. Coded to be portable to - dual-CPU configuration. - Checks CPU number and performs board HW initialization if called for CPU0. - - Registers used: r3,r4,r5,r6,r19,r29 -=========================================================================== - ---------------------------------------------------------------------------- - NOTE: For dual-CPU configuration only CPU0 is allowed to configure Tsi108 - and the rest of the board. Current implementation demonstrates two - possible ways to identify CPU number: - - for MPC74xx platform: uses MSSCR0[ID] bit as defined in UM. - - for PPC750FX/GX boards: uses WHO_AM_I bit reported by Tsi108. ----------------------------------------------------------------------------*/ +/* + * board_asm_init() - early initialization function. Coded to be portable to + * dual-CPU configuration. + * Checks CPU number and performs board HW initialization if called for CPU0. + * Registers used: r3,r4,r5,r6,r19,r29 + * + * NOTE: For dual-CPU configuration only CPU0 is allowed to configure Tsi108 + * and the rest of the board. Current implementation demonstrates two + * possible ways to identify CPU number: + * - for MPC74xx platform: uses MSSCR0[ID] bit as defined in UM. + * - for PPC750FX/GX boards: uses WHO_AM_I bit reported by Tsi108. + */ - .globl board_asm_init + .globl board_asm_init board_asm_init: + mflr r19 /* Save LR to be able return later. */ + bl icache_enable /* Enable icache to reduce reads from flash. */ - mflr r19 /* Save LR to be able return later. */ - - bl icache_enable /* Enable icache to reduce reads from flash. */ +/* Initialize pointer to Tsi108 register space */ - /* Initialize pointer to Tsi108 register space - -------------------------------------------------------------------------*/ + LOAD_PTR(r29,CFG_TSI108_CSR_RST_BASE)/* r29 - pointer to tsi108 CSR space */ + ori r4,r29,TSI108_PB_REG_OFFSET - LOAD_PTR(r29,CFG_TSI108_CSR_RST_BASE)/* r29 - pointer to tsi108 CSR space */ - ori r4,r29,TSI108_PB_REG_OFFSET +/* Check Processor Version Number */ - /*------------------------------------------------------------------------- - Check Processor Version Number */ + mfspr r3, PVR + rlwinm r3,r3,16,16,23 /* get ((Processor Version Number) & 0xFF00) */ - mfspr r3, PVR - rlwinm r3,r3,16,16,23 /* get ((Processor Version Number) & 0xFF00) */ + cmpli 0,0,r3,0x8000 /* MPC74xx */ + bne cont_brd_init - cmpli 0,0,r3,0x8000 /* MPC74xx */ - bne cont_brd_init - - /* ------------------------------------------ - For MPC744x/5x enable extended BATs[4-7] - Sri: Set HIGH_BAT_EN and XBSEN, and SPD =1 - to disable prefetch - */ - - mfspr r5, HID0 - oris r5, r5, 0x0080 /* Set HID0[HIGH_BAT_EN] bit #8 */ - ori r5, r5, 0x0380 /* Set SPD,XBSEN,SGE bits #22,23,24 */ - mtspr HID0, r5 - isync - sync + /* + * For MPC744x/5x enable extended BATs[4-7] + * Sri: Set HIGH_BAT_EN and XBSEN, and SPD =1 + * to disable prefetch + */ - /* Adding code to disable external interventions in MPX bus mode */ - mfspr r3, 1014 - oris r3, r3, 0x0100 /* Set the EIDIS bit in MSSCR0: bit 7 */ - mtspr 1014, r3 - isync - sync + mfspr r5, HID0 + oris r5, r5, 0x0080 /* Set HID0[HIGH_BAT_EN] bit #8 */ + ori r5, r5, 0x0380 /* Set SPD,XBSEN,SGE bits #22,23,24 */ + mtspr HID0, r5 + isync + sync - /* Sri: code to enable FP unit */ - mfmsr r3 - ori r3, r3, 0x2000 - mtmsr r3 - isync - sync + /* Adding code to disable external interventions in MPX bus mode */ + mfspr r3, 1014 + oris r3, r3, 0x0100 /* Set the EIDIS bit in MSSCR0: bit 7 */ + mtspr 1014, r3 + isync + sync -#if(1) /* def CONFIG_DUAL_CPU - ------------------------------------------------------------------------- - For MPC74xx processor, use MSSCR0[ID] bit to identify CPU number. - */ + /* Sri: code to enable FP unit */ + mfmsr r3 + ori r3, r3, 0x2000 + mtmsr r3 + isync + sync - mfspr r3,1014 /* read MSSCR0 */ - rlwinm. r3,r3,27,31,31 /* get processor ID number */ - mtspr SPRN_PIR,r3 /* Save CPU ID */ - sync - bne init_done - b do_tsi108_init + /* def CONFIG_DUAL_CPU + * For MPC74xx processor, use MSSCR0[ID] bit to identify CPU number. + */ +#if(1) + mfspr r3,1014 /* read MSSCR0 */ + rlwinm. r3,r3,27,31,31 /* get processor ID number */ + mtspr SPRN_PIR,r3 /* Save CPU ID */ + sync + bne init_done + b do_tsi108_init cont_brd_init: - /* An alternative method of checking the processor number (in addition - to configuration using MSSCR0[ID] bit on MPC74xx). - Good for IBM PPC750FX/GX. - */ - - lwz r3,PB_BUS_MS_SELECT(r4) /* read PB_ID register */ - rlwinm. r3,r3,24,31,31 /* get processor ID number */ - - bne init_done + /* An alternative method of checking the processor number (in addition + * to configuration using MSSCR0[ID] bit on MPC74xx). + * Good for IBM PPC750FX/GX. + */ + lwz r3,PB_BUS_MS_SELECT(r4) /* read PB_ID register */ + rlwinm. r3,r3,24,31,31 /* get processor ID number */ + bne init_done #else cont_brd_init: #endif /* CONFIG_DUAL_CPU */ - /* Initialize Tsi108 chip - --------------------------------------------------------------------------- - */ + /* Initialize Tsi108 chip */ do_tsi108_init: - /*-------------------------------------------------------------------------- - Adjust HLP/Flash parameters. By default after reset the HLP port is set - to support slow devices. Better performance can be achived when an optimal - parameters are used for specific EPROM device. - NOTE: This should be performed ASAP for the emulation platform because - it has 5MHz HLP clocking. - */ + /* + * Adjust HLP/Flash parameters. By default after reset the HLP port is + * set to support slow devices. Better performance can be achived when + * an optimal parameters are used for specific EPROM device. + * NOTE: This should be performed ASAP for the emulation platform + * because it has 5MHz HLP clocking. + */ #ifdef CONFIG_TSI108EMU - ori r4,r29,TSI108_HLP_REG_OFFSET - LOAD_U32(r5,0x434422c0) - stw r5,0x08(r4) /* set HLP B0_CTRL0 */ - sync - LOAD_U32(r5,0xd0012000) - stw r5,0x0c(r4) /* set HLP B0_CTRL1 */ - sync + ori r4,r29,TSI108_HLP_REG_OFFSET + LOAD_U32(r5,0x434422c0) + stw r5,0x08(r4) /* set HLP B0_CTRL0 */ + sync + LOAD_U32(r5,0xd0012000) + stw r5,0x0c(r4) /* set HLP B0_CTRL1 */ + sync #endif - /* ------------------------------------------------------------------------- - * Initialize PB interface. - */ + /* Initialize PB interface. */ - ori r4,r29,TSI108_PB_REG_OFFSET + ori r4,r29,TSI108_PB_REG_OFFSET #if (CFG_TSI108_CSR_BASE != CFG_TSI108_CSR_RST_BASE) - /* Relocate (if required) Tsi108 registers. Set new value for PB_REG_BAR: - * Note we are in the 32-bit address mode. - */ - LOAD_U32(r5,(CFG_TSI108_CSR_BASE | 0x01)) /* value for PB_REG_BAR: BA + EN*/ - stw r5,PB_REG_BAR(r4) - andis. r29,r5,0xFFFF - sync - - ori r4,r29,TSI108_PB_REG_OFFSET + /* Relocate (if required) Tsi108 registers. Set new value for + * PB_REG_BAR: + * Note we are in the 32-bit address mode. + */ + LOAD_U32(r5,(CFG_TSI108_CSR_BASE | 0x01)) /* PB_REG_BAR: BA + EN */ + stw r5,PB_REG_BAR(r4) + andis. r29,r5,0xFFFF + sync + ori r4,r29,TSI108_PB_REG_OFFSET #endif - /* Set PB Slave configuration register */ + /* Set PB Slave configuration register */ -/* LOAD_U32(r5,0x000024C7) value for PB_SCR: TEA enabled,AACK delay = 7 */ - LOAD_U32(r5,0x00002481) /* value for PB_SCR: TEA enabled,AACK delay = 1 */ - lwz r3, PB_RSR(r4) /* get PB bus mode */ - xori r3,r3,0x0001 /* mask PB_BMODE: r3 -> (0 = 60X, 1 = MPX) */ - rlwimi r5,r3,14,17,17 /* for MPX: set DTI_MODE bit */ - stw r5,PB_SCR(r4) - sync + LOAD_U32(r5,0x00002481) /* PB_SCR: TEA enabled,AACK delay = 1 */ + lwz r3, PB_RSR(r4) /* get PB bus mode */ + xori r3,r3,0x0001 /* mask PB_BMODE: r3 -> (0 = 60X, 1 = MPX) */ + rlwimi r5,r3,14,17,17 /* for MPX: set DTI_MODE bit */ + stw r5,PB_SCR(r4) + sync - /* Configure PB Arbiter */ + /* Configure PB Arbiter */ - lwz r5,PB_ARB_CTRL(r4) /* Read PB Arbiter Control Register */ - li r3, 0x00F0 /* ARB_PIPELINE_DEP mask */ + lwz r5,PB_ARB_CTRL(r4) /* Read PB Arbiter Control Register */ + li r3, 0x00F0 /* ARB_PIPELINE_DEP mask */ #ifdef DISABLE_PBM - ori r3,r3,0x1000 /* add PBM_EN to clear (enabled by default) */ + ori r3,r3,0x1000 /* add PBM_EN to clear (enabled by default) */ #endif - andc r5,r5,r3 /* Clear the masked bit fields */ -/* ori r5,r5,0x0040 Set pipeline depth 4 - ori r5,r5,0x0080 Set pipeline depth 8 - ori r5,r5,0x0020 !!!avb Testing: set pipeline depth 2 */ - ori r5,r5,0x0001 - stw r5,PB_ARB_CTRL(r4) - -#if (0) /* currently using the default settings for PBM after reset */ - LOAD_U32(r5,0x) /* value for PB_MCR */ - stw r5,PB_MCR(r4) - sync - - LOAD_U32(r5,0x) /* value for PB_MCMD */ - stw r5,PB_MCMD(r4) - sync + andc r5,r5,r3 /* Clear the masked bit fields */ + ori r5,r5,0x0001 /* Set pipeline depth */ + stw r5,PB_ARB_CTRL(r4) + +#if (0) /* currently using the default settings for PBM after reset */ + LOAD_U32(r5,0x) /* value for PB_MCR */ + stw r5,PB_MCR(r4) + sync + + LOAD_U32(r5,0x) /* value for PB_MCMD */ + stw r5,PB_MCMD(r4) + sync #endif -/* Disable or enable PVT based on processor bus frequency - 1. Read CG_PWRUP_STATUS register field bits 18,17,16 - 2. See if the value is < or > 133mhz (18:16 = 100) - 3. If > enable PVT - */ + /* Disable or enable PVT based on processor bus frequency + * 1. Read CG_PWRUP_STATUS register field bits 18,17,16 + * 2. See if the value is < or > 133mhz (18:16 = 100) + * 3. If > enable PVT + */ - LOAD_U32(r3,0xC0002234) - lwz r3,0(r3) - rlwinm r3,r3,16,29,31 + LOAD_U32(r3,0xC0002234) + lwz r3,0(r3) + rlwinm r3,r3,16,29,31 - cmpi 0,0,r3,0x0004 - bgt sdc_init + cmpi 0,0,r3,0x0004 + bgt sdc_init #ifndef CONFIG_TSI108EMU - /* FIXME: Disable PB calibration control for any real Tsi108 board */ - li r5,0x0101 /* disable calibration control */ - stw r5,PB_PVT_CTRL2(r4) - sync + /* FIXME: Disable PB calibration control for any real Tsi108 board */ + li r5,0x0101 /* disable calibration control */ + stw r5,PB_PVT_CTRL2(r4) + sync #endif -/*--------------------------------------------------------------------------- - Initialize SDRAM controller. -----------------------------------------------------------------------------*/ + /* Initialize SDRAM controller. */ sdc_init: #ifndef SDC_HARDCODED_INIT - /* get SDC clock prior doing sdram controller autoconfig */ - ori r4,r29,TSI108_CLK_REG_OFFSET /* r4 - ptr to CG registers */ - lwz r3, CG_PWRUP_STATUS(r4) /* get CG configuration */ - rlwinm r3,r3,12,29,31 /* r3 - SD clk */ - lis r5,sdc_clk_sync@h - ori r5,r5,sdc_clk_sync@l - /* Sri: At this point check if r3 = 001. If yes, - * the memory frequency should be same as the - * MPX bus frequency - */ - cmpi 0,0,r3,0x0001 - bne get_nsec - lwz r6, CG_PWRUP_STATUS(r4) - rlwinm r6,r6,16,29,31 - mr r3,r6 + /* get SDC clock prior doing sdram controller autoconfig */ + ori r4,r29,TSI108_CLK_REG_OFFSET /* r4 - ptr to CG registers */ + lwz r3, CG_PWRUP_STATUS(r4) /* get CG configuration */ + rlwinm r3,r3,12,29,31 /* r3 - SD clk */ + lis r5,sdc_clk_sync@h + ori r5,r5,sdc_clk_sync@l + /* Sri: At this point check if r3 = 001. If yes, + * the memory frequency should be same as the + * MPX bus frequency + */ + cmpi 0,0,r3,0x0001 + bne get_nsec + lwz r6, CG_PWRUP_STATUS(r4) + rlwinm r6,r6,16,29,31 + mr r3,r6 get_nsec: - rlwinm r3,r3,2,0,31 - lwzx r9,r5,r3 /* get SD clk rate in nSec */ - /* ATTN: r9 will be used by SPD routine */ + rlwinm r3,r3,2,0,31 + lwzx r9,r5,r3 /* get SD clk rate in nSec */ + /* ATTN: r9 will be used by SPD routine */ #endif /* !SDC_HARDCODED_INIT */ - ori r4,r29,TSI108_SD_REG_OFFSET /* r4 - ptr to SDRAM registers */ + ori r4,r29,TSI108_SD_REG_OFFSET /* r4 - ptr to SDRAM registers */ - /* Initialize SDRAM controller. SDRAM Size = 512MB, One DIMM. */ + /* Initialize SDRAM controller. SDRAM Size = 512MB, One DIMM. */ - LOAD_U32(r5,0x00) - stw r5,SD_INT_ENABLE(r4) /* Ensure that interrupts are disabled */ + LOAD_U32(r5,0x00) + stw r5,SD_INT_ENABLE(r4) /* Ensure that interrupts are disabled */ #ifdef ENABLE_SDRAM_ECC - li r5, 0x01 + li r5, 0x01 #endif /* ENABLE_SDRAM_ECC */ - stw r5,SD_ECC_CTRL(r4) /* Enable/Disable ECC */ - sync + stw r5,SD_ECC_CTRL(r4) /* Enable/Disable ECC */ + sync #ifdef SDC_HARDCODED_INIT /* config sdram controller with hardcoded values */ - /* First read the CG_PWRUP_STATUS register to get the - memory speed from bits 22,21,20 */ - - LOAD_U32(r3,0xC0002234) - lwz r3,0(r3) - rlwinm r3,r3,12,29,31 + /* First read the CG_PWRUP_STATUS register to get the + * memory speed from bits 22,21,20 + */ - /* Now first check for 166, then 200, or default */ + LOAD_U32(r3,0xC0002234) + lwz r3,0(r3) + rlwinm r3,r3,12,29,31 - cmpi 0,0,r3,0x0005 - bne check_for_200mhz + /* Now first check for 166, then 200, or default */ - /* set values for 166 Mhz memory speed */ + cmpi 0,0,r3,0x0005 + bne check_for_200mhz - /* Set refresh rate and timing parameters */ - LOAD_U32(r5,0x00000515) - stw r5,SD_REFRESH(r4) - LOAD_U32(r5,0x03073368) - stw r5,SD_TIMING(r4) - sync + /* set values for 166 Mhz memory speed + * Set refresh rate and timing parameters + */ + LOAD_U32(r5,0x00000515) + stw r5,SD_REFRESH(r4) + LOAD_U32(r5,0x03073368) + stw r5,SD_TIMING(r4) + sync - /* Initialize DIMM0 control and BAR registers */ - LOAD_U32(r5,VAL_SD_D0_CTRL) /* auto-precharge disabled */ + /* Initialize DIMM0 control and BAR registers */ + LOAD_U32(r5,VAL_SD_D0_CTRL) /* auto-precharge disabled */ #ifdef SDC_AUTOPRECH_EN - oris r5,r5,0x0001 /* set auto precharge EN bit */ + oris r5,r5,0x0001 /* set auto precharge EN bit */ #endif - stw r5,SD_D0_CTRL(r4) - LOAD_U32(r5,VAL_SD_D0_BAR) - stw r5,SD_D0_BAR(r4) - sync - - /* Initialize DIMM1 control and BAR registers - * (same as dimm 0, next 512MB, disabled) - */ - LOAD_U32(r5,VAL_SD_D1_CTRL) /* auto-precharge disabled */ + stw r5,SD_D0_CTRL(r4) + LOAD_U32(r5,VAL_SD_D0_BAR) + stw r5,SD_D0_BAR(r4) + sync + + /* Initialize DIMM1 control and BAR registers + * (same as dimm 0, next 512MB, disabled) + */ + LOAD_U32(r5,VAL_SD_D1_CTRL) /* auto-precharge disabled */ #ifdef SDC_AUTOPRECH_EN - oris r5,r5,0x0001 /* set auto precharge EN bit */ + oris r5,r5,0x0001 /* set auto precharge EN bit */ #endif - stw r5,SD_D1_CTRL(r4) - LOAD_U32(r5,VAL_SD_D1_BAR) - stw r5,SD_D1_BAR(r4) - sync + stw r5,SD_D1_CTRL(r4) + LOAD_U32(r5,VAL_SD_D1_BAR) + stw r5,SD_D1_BAR(r4) + sync - b sdc_init_done + b sdc_init_done check_for_200mhz: - cmpi 0,0,r3,0x0006 - bne set_default_values + cmpi 0,0,r3,0x0006 + bne set_default_values - /* set values for 200Mhz memory speed */ - - /* Set refresh rate and timing parameters */ - LOAD_U32(r5,0x0000061a) - stw r5,SD_REFRESH(r4) - LOAD_U32(r5,0x03083348) - stw r5,SD_TIMING(r4) - sync + /* set values for 200Mhz memory speed + * Set refresh rate and timing parameters + */ + LOAD_U32(r5,0x0000061a) + stw r5,SD_REFRESH(r4) + LOAD_U32(r5,0x03083348) + stw r5,SD_TIMING(r4) + sync - /* Initialize DIMM0 control and BAR registers */ - LOAD_U32(r5,VAL_SD_D0_CTRL) /* auto-precharge disabled */ + /* Initialize DIMM0 control and BAR registers */ + LOAD_U32(r5,VAL_SD_D0_CTRL) /* auto-precharge disabled */ #ifdef SDC_AUTOPRECH_EN - oris r5,r5,0x0001 /* set auto precharge EN bit */ + oris r5,r5,0x0001 /* set auto precharge EN bit */ #endif - stw r5,SD_D0_CTRL(r4) - LOAD_U32(r5,VAL_SD_D0_BAR) - stw r5,SD_D0_BAR(r4) - sync - - /* Initialize DIMM1 control and BAR registers - * (same as dimm 0, next 512MB, disabled) - */ - LOAD_U32(r5,VAL_SD_D1_CTRL) /* auto-precharge disabled */ + stw r5,SD_D0_CTRL(r4) + LOAD_U32(r5,VAL_SD_D0_BAR) + stw r5,SD_D0_BAR(r4) + sync + + /* Initialize DIMM1 control and BAR registers + * (same as dimm 0, next 512MB, disabled) + */ + LOAD_U32(r5,VAL_SD_D1_CTRL) /* auto-precharge disabled */ #ifdef SDC_AUTOPRECH_EN - oris r5,r5,0x0001 /* set auto precharge EN bit */ + oris r5,r5,0x0001 /* set auto precharge EN bit */ #endif - stw r5,SD_D1_CTRL(r4) - LOAD_U32(r5,VAL_SD_D1_BAR) - stw r5,SD_D1_BAR(r4) - sync + stw r5,SD_D1_CTRL(r4) + LOAD_U32(r5,VAL_SD_D1_BAR) + stw r5,SD_D1_BAR(r4) + sync - b sdc_init_done + b sdc_init_done set_default_values: - /* Set refresh rate and timing parameters */ - LOAD_U32(r5,VAL_SD_REFRESH) - stw r5,SD_REFRESH(r4) - LOAD_U32(r5,VAL_SD_TIMING) - stw r5,SD_TIMING(r4) - sync + /* Set refresh rate and timing parameters */ + LOAD_U32(r5,VAL_SD_REFRESH) + stw r5,SD_REFRESH(r4) + LOAD_U32(r5,VAL_SD_TIMING) + stw r5,SD_TIMING(r4) + sync - /* Initialize DIMM0 control and BAR registers */ - LOAD_U32(r5,VAL_SD_D0_CTRL) /* auto-precharge disabled */ + /* Initialize DIMM0 control and BAR registers */ + LOAD_U32(r5,VAL_SD_D0_CTRL) /* auto-precharge disabled */ #ifdef SDC_AUTOPRECH_EN - oris r5,r5,0x0001 /* set auto precharge EN bit */ + oris r5,r5,0x0001 /* set auto precharge EN bit */ #endif - stw r5,SD_D0_CTRL(r4) - LOAD_U32(r5,VAL_SD_D0_BAR) - stw r5,SD_D0_BAR(r4) - sync - - /* Initialize DIMM1 control and BAR registers - * (same as dimm 0, next 512MB, disabled) - */ - LOAD_U32(r5,VAL_SD_D1_CTRL) /* auto-precharge disabled */ + stw r5,SD_D0_CTRL(r4) + LOAD_U32(r5,VAL_SD_D0_BAR) + stw r5,SD_D0_BAR(r4) + sync + + /* Initialize DIMM1 control and BAR registers + * (same as dimm 0, next 512MB, disabled) + */ + LOAD_U32(r5,VAL_SD_D1_CTRL) /* auto-precharge disabled */ #ifdef SDC_AUTOPRECH_EN - oris r5,r5,0x0001 /* set auto precharge EN bit */ + oris r5,r5,0x0001 /* set auto precharge EN bit */ #endif - stw r5,SD_D1_CTRL(r4) - LOAD_U32(r5,VAL_SD_D1_BAR) - stw r5,SD_D1_BAR(r4) - sync - + stw r5,SD_D1_CTRL(r4) + LOAD_U32(r5,VAL_SD_D1_BAR) + stw r5,SD_D1_BAR(r4) + sync #else /* !SDC_HARDCODED_INIT */ - - bl tsi108_sdram_spd /* automatically detect SDC settings */ - + bl tsi108_sdram_spd /* automatically detect SDC settings */ #endif /* SDC_HARDCODED_INIT */ sdc_init_done: #ifdef DISABLE_PBM - LOAD_U32(r5,0x00000030) /* PB_EN + OCN_EN */ + LOAD_U32(r5,0x00000030) /* PB_EN + OCN_EN */ #else - LOAD_U32(r5,0x00000230) /* PB_EN + OCN_EN + PB/OCN=80/20 */ + LOAD_U32(r5,0x00000230) /* PB_EN + OCN_EN + PB/OCN=80/20 */ #endif /* DISABLE_PBM */ #ifdef CONFIG_TSI108EMU - oris r5,r5,0x0010 /* set EMULATION_MODE bit */ + oris r5,r5,0x0010 /* set EMULATION_MODE bit */ #endif - stw r5,SD_CTRL(r4) - eieio - sync + stw r5,SD_CTRL(r4) + eieio + sync - /* Enable SDRAM access */ + /* Enable SDRAM access */ - oris r5,r5,0x8000 /* start SDC: set SD_CTRL[ENABLE] bit */ - stw r5,SD_CTRL(r4) - sync + oris r5,r5,0x8000 /* start SDC: set SD_CTRL[ENABLE] bit */ + stw r5,SD_CTRL(r4) + sync wait_init_complete: - lwz r5,SD_STATUS(r4) - andi. r5,r5,0x0001 - beq wait_init_complete /* wait until SDRAM initialization is complete */ - -/*--------------------------------------------------------------------------- - Map SDRAM into the processor bus address space ----------------------------------------------------------------------------*/ + lwz r5,SD_STATUS(r4) + andi. r5,r5,0x0001 + /* wait until SDRAM initialization is complete */ + beq wait_init_complete - ori r4,r29,TSI108_PB_REG_OFFSET + /* Map SDRAM into the processor bus address space */ - /* Setup BARs associated with direct path PB<->SDRAM */ + ori r4,r29,TSI108_PB_REG_OFFSET - /* PB_SDRAM_BAR1: - provides a direct path to the main system memory (cacheable SDRAM) */ + /* Setup BARs associated with direct path PB<->SDRAM */ - LOAD_U32(r5, 0x00000011) /* BA=0,Size=512MB, ENable, No Addr.Translation */ - stw r5,PB_SDRAM_BAR1(r4) - sync + /* PB_SDRAM_BAR1: + * provides a direct path to the main system memory (cacheable SDRAM) + */ - /* Make sure that PB_SDRAM_BAR1 decoder is set - (to allow following immediate read from SDRAM) */ - lwz r5,PB_SDRAM_BAR1(r4) - sync + /* BA=0,Size=512MB, ENable, No Addr.Translation */ + LOAD_U32(r5, 0x00000011) + stw r5,PB_SDRAM_BAR1(r4) + sync - /* PB_SDRAM_BAR2: - provides non-cacheable alias (via the direct path) to main system memory. - Size = 512MB, ENable, Addr.Translation - ON, - BA = 0x0_40000000, TA = 0x0_00000000 */ + /* Make sure that PB_SDRAM_BAR1 decoder is set + * (to allow following immediate read from SDRAM) + */ + lwz r5,PB_SDRAM_BAR1(r4) + sync - LOAD_U32(r5, 0x40010011) - stw r5,PB_SDRAM_BAR2(r4) - sync + /* PB_SDRAM_BAR2: + * provides non-cacheable alias (via the direct path) to main + * system memory. + * Size = 512MB, ENable, Addr.Translation - ON, + * BA = 0x0_40000000, TA = 0x0_00000000 + */ - /* Make sure that PB_SDRAM_BAR2 decoder is set - (to allow following immediate read from SDRAM) */ - lwz r5,PB_SDRAM_BAR2(r4) - sync + LOAD_U32(r5, 0x40010011) + stw r5,PB_SDRAM_BAR2(r4) + sync + /* Make sure that PB_SDRAM_BAR2 decoder is set + * (to allow following immediate read from SDRAM) + */ + lwz r5,PB_SDRAM_BAR2(r4) + sync init_done: - /* All done. Restore LR and return. */ - mtlr r19 - blr + /* All done. Restore LR and return. */ + mtlr r19 + blr #if (0) -/*=========================================================================== - init_cpu1 - - This routine enables CPU1 on the dual-processor system. -===========================================================================*/ + /* + * init_cpu1 + * This routine enables CPU1 on the dual-processor system. + * Now there is only one processor in the system + */ - .global enable_cpu1 + .global enable_cpu1 enable_cpu1: - lis r3,Tsi108_Base@ha /* Get Grendel CSR Base Addr */ - addi r3,r3,Tsi108_Base@l - lwz r3,0(r3) /* R3 = CSR Base Addr */ - ori r4,r3,TSI108_PB_REG_OFFSET - lwz r3,PB_ARB_CTRL(r4) /* Read PB Arbiter Control Register */ - ori r3,r3,0x0200 /* Set M1_EN bit */ - stw r3,PB_ARB_CTRL(r4) + lis r3,Tsi108_Base@ha /* Get Grendel CSR Base Addr */ + addi r3,r3,Tsi108_Base@l + lwz r3,0(r3) /* R3 = CSR Base Addr */ + ori r4,r3,TSI108_PB_REG_OFFSET + lwz r3,PB_ARB_CTRL(r4) /* Read PB Arbiter Control Register */ + ori r3,r3,0x0200 /* Set M1_EN bit */ + stw r3,PB_ARB_CTRL(r4) - blr + blr #endif -/*=========================================================================== - enable_EI - - Enable CPU core external interrupt -===========================================================================*/ + /* + * enable_EI + * Enable CPU core external interrupt + */ - .global enable_EI + .global enable_EI enable_EI: - mfmsr r3 - ori r3,r3,0x8000 /* set EE bit */ - mtmsr r3 - blr - -/*=========================================================================== - disable_EI + mfmsr r3 + ori r3,r3,0x8000 /* set EE bit */ + mtmsr r3 + blr - Disable CPU core external interrupt -===========================================================================*/ + /* + * disable_EI + * Disable CPU core external interrupt + */ - .global disable_EI + .global disable_EI disable_EI: - mfmsr r3 - li r4,-32768 /* aka "li r4,0x8000" */ - andc r3,r3,r4 /* clear EE bit */ - mtmsr r3 - blr + mfmsr r3 + li r4,-32768 /* aka "li r4,0x8000" */ + andc r3,r3,r4 /* clear EE bit */ + mtmsr r3 + blr #ifdef ENABLE_SDRAM_ECC -/*=========================================================================== - enable_ECC + /* enables SDRAM ECC */ - enables SDRAM ECC -===========================================================================*/ - - .global enable_ECC + .global enable_ECC enable_ECC: - ori r4,r29,TSI108_SD_REG_OFFSET - lwz r3,SD_ECC_CTRL(r4) /* Read SDRAM ECC Control Register */ - ori r3,r3,0x0001 /* Set ECC_EN bit */ - stw r3,SD_ECC_CTRL(r4) - blr - -/*=========================================================================== - clear_ECC_err + ori r4,r29,TSI108_SD_REG_OFFSET + lwz r3,SD_ECC_CTRL(r4) /* Read SDRAM ECC Control Register */ + ori r3,r3,0x0001 /* Set ECC_EN bit */ + stw r3,SD_ECC_CTRL(r4) + blr - Clears all pending SDRAM ECC errors - (normally after SDRAM scrubbing/initialization) -===========================================================================*/ + /* + * clear_ECC_err + * Clears all pending SDRAM ECC errors + * (normally after SDRAM scrubbing/initialization) + */ - .global clear_ECC_err + .global clear_ECC_err clear_ECC_err: - ori r4,r29,TSI108_SD_REG_OFFSET -/* lwz r3,SD_INT_STATUS(r4) Read SDRAM ECC Control Register */ - ori r3,r0,0x0030 /* ECC_UE_INT + ECC_CE_INT bits */ - stw r3,SD_INT_STATUS(r4) - blr + ori r4,r29,TSI108_SD_REG_OFFSET + ori r3,r0,0x0030 /* ECC_UE_INT + ECC_CE_INT bits */ + stw r3,SD_INT_STATUS(r4) + blr #endif /* ENABLE_SDRAM_ECC */ #ifndef SDC_HARDCODED_INIT -/******************************************************************** - * SDRAM SPD Support - */ - + /* SDRAM SPD Support */ #define SD_I2C_CTRL1 (0x400) #define SD_I2C_CTRL2 (0x404) #define SD_I2C_RD_DATA (0x408) -#define SD_I2C_WR_DATA (0x40C) +#define SD_I2C_WR_DATA (0x40C) -/* - * SDRAM SPD Support Macros - */ + /* + * SDRAM SPD Support Macros + */ #define SPD_DIMM0 (0x00000100) -#define SPD_DIMM1 (0x00000200) /* SPD_DIMM1 was 0x00000000 */ +#define SPD_DIMM1 (0x00000200) /* SPD_DIMM1 was 0x00000000 */ #define SPD_RDIMM (0x01) #define SPD_UDIMM (0x02) @@ -651,30 +623,30 @@ clear_ECC_err: * r10 - number of DDR slot where first SPD device is detected */ -#define READ_SPD(byte_num) \ - addis r3, 0, byte_num@l;\ - or r3, r3, r10;\ - ori r3, r3, 0x0A;\ - stw r3, SD_I2C_CTRL1(r4);\ - li r3, I2C_CNTRL2_START;\ - stw r3, SD_I2C_CTRL2(r4);\ - eieio;\ - sync;\ - li r3, 0x100;\ -1: ;\ - addic. r3, r3, -1;\ - bne 1b;\ -2: ;\ - lwz r5, SD_I2C_CTRL2(r4);\ - rlwinm. r3,r5,0,23,23;\ - bne 2b;\ - rlwinm. r3,r5,0,3,3;\ - lwz r3, SD_I2C_RD_DATA(r4) +#define READ_SPD(byte_num) \ + addis r3, 0, byte_num@l; \ + or r3, r3, r10; \ + ori r3, r3, 0x0A; \ + stw r3, SD_I2C_CTRL1(r4); \ + li r3, I2C_CNTRL2_START; \ + stw r3, SD_I2C_CTRL2(r4); \ + eieio; \ + sync; \ + li r3, 0x100; \ +1:; \ + addic. r3, r3, -1; \ + bne 1b; \ +2:; \ + lwz r5, SD_I2C_CTRL2(r4); \ + rlwinm. r3,r5,0,23,23; \ + bne 2b; \ + rlwinm. r3,r5,0,3,3; \ + lwz r3,SD_I2C_RD_DATA(r4) #define SPD_MIN_RFRSH (0x80) #define SPD_MAX_RFRSH (0x85) -refresh_rates: /* in nSec */ +refresh_rates: /* in nSec */ .long 15625 /* Normal (0x80) */ .long 3900 /* Reduced 0.25x (0x81) */ .long 7800 /* Reduced 0.5x (0x82) */ @@ -682,274 +654,265 @@ refresh_rates: /* in nSec */ .long 62500 /* Extended 4x (0x84) */ .long 125000 /* Extended 8x (0x85) */ -/*=========================================================================== +/* * tsi108_sdram_spd * * Inittializes SDRAM Controller using DDR2 DIMM Serial Presence Detect data * Uses registers: r4 - SDC base address (not changed) * r9 - SDC clocking period in nSec * Changes registers: r3,r5,r6,r7,r8,r10,r11 - *==========================================================================*/ + */ tsi108_sdram_spd: - li r10,SPD_DIMM0 + li r10,SPD_DIMM0 xor r11,r11,r11 /* DIMM Base Address: starts from 0 */ do_first_dimm: - /************************************** - * Program Refresh Rate Register - */ + /* Program Refresh Rate Register */ + + READ_SPD(12) /* get Refresh Rate */ + beq check_next_slot + li r5, ERR_RFRSH_RATE + cmpi 0,0,r3,SPD_MIN_RFRSH + ble spd_fail + cmpi 0,0,r3,SPD_MAX_RFRSH + bgt spd_fail + addi r3,r3,-SPD_MIN_RFRSH + rlwinm r3,r3,2,0,31 + lis r5,refresh_rates@h + ori r5,r5,refresh_rates@l + lwzx r5,r5,r3 /* get refresh rate in nSec */ + divwu r5,r5,r9 /* calculate # of SDC clocks */ + stw r5,SD_REFRESH(r4) /* Set refresh rate */ + sync - READ_SPD(12) /* get Refresh Rate */ - beq check_next_slot - li r5, ERR_RFRSH_RATE - cmpi 0,0,r3,SPD_MIN_RFRSH - ble spd_fail - cmpi 0,0,r3,SPD_MAX_RFRSH - bgt spd_fail - addi r3,r3,-SPD_MIN_RFRSH - rlwinm r3,r3,2,0,31 - lis r5,refresh_rates@h - ori r5,r5,refresh_rates@l - lwzx r5,r5,r3 /* get refresh rate in nSec */ - divwu r5,r5,r9 /* calculate # of SDC clocks */ - stw r5,SD_REFRESH(r4) /* Set refresh rate */ - sync - - /************************************** - * Program SD Timing Register - */ + /* Program SD Timing Register */ - li r7, 0 /* clear r7 prior parameter collection */ + li r7, 0 /* clear r7 prior parameter collection */ - READ_SPD(20) /* get DIMM type: Registered or Unbuffered */ + READ_SPD(20) /* get DIMM type: Registered or Unbuffered */ beq spd_read_fail - li r5, ERR_DIMM_TYPE - cmpi 0,0,r3,SPD_UDIMM - beq do_cl - cmpi 0,0,r3,SPD_RDIMM - bne spd_fail - oris r7,r7,0x1000 /* set SD_TIMING[DIMM_TYPE] bit */ + li r5, ERR_DIMM_TYPE + cmpi 0,0,r3,SPD_UDIMM + beq do_cl + cmpi 0,0,r3,SPD_RDIMM + bne spd_fail + oris r7,r7,0x1000 /* set SD_TIMING[DIMM_TYPE] bit */ do_cl: - READ_SPD(18) /* Get CAS Latency */ + READ_SPD(18) /* Get CAS Latency */ beq spd_read_fail - li r5,ERR_CL_VALUE - andi. r6,r3,SPD_CAS_3 - beq cl_4 - li r6,3 - b set_cl + li r5,ERR_CL_VALUE + andi. r6,r3,SPD_CAS_3 + beq cl_4 + li r6,3 + b set_cl cl_4: - andi. r6,r3,SPD_CAS_4 - beq cl_5 - li r6,4 - b set_cl + andi. r6,r3,SPD_CAS_4 + beq cl_5 + li r6,4 + b set_cl cl_5: - andi. r6,r3,SPD_CAS_5 - beq spd_fail - li r6,5 + andi. r6,r3,SPD_CAS_5 + beq spd_fail + li r6,5 set_cl: - rlwimi r7,r6,24,5,7 + rlwimi r7,r6,24,5,7 - READ_SPD(30) /* Get tRAS */ + READ_SPD(30) /* Get tRAS */ beq spd_read_fail - divwu r6,r3,r9 - mullw r8,r6,r9 - subf. r8,r8,r3 + divwu r6,r3,r9 + mullw r8,r6,r9 + subf. r8,r8,r3 beq set_tras - addi r6,r6,1 + addi r6,r6,1 set_tras: li r5,ERR_TRAS_FAIL - cmpi 0,0,r6,0x0F /* max supported value */ - bgt spd_fail - rlwimi r7,r6,16,12,15 + cmpi 0,0,r6,0x0F /* max supported value */ + bgt spd_fail + rlwimi r7,r6,16,12,15 READ_SPD(29) /* Get tRCD */ beq spd_read_fail - rlwinm r3,r3,30,2,31/* right shift tRCD by 2 bits as per DDR2 spec */ - divwu r6,r3,r9 - mullw r8,r6,r9 - subf. r8,r8,r3 + /* right shift tRCD by 2 bits as per DDR2 spec */ + rlwinm r3,r3,30,2,31 + divwu r6,r3,r9 + mullw r8,r6,r9 + subf. r8,r8,r3 beq set_trcd - addi r6,r6,1 + addi r6,r6,1 set_trcd: - li r5,ERR_TRCD_FAIL - cmpi 0,0,r6,0x07 /* max supported value */ - bgt spd_fail - rlwimi r7,r6,12,17,19 + li r5,ERR_TRCD_FAIL + cmpi 0,0,r6,0x07 /* max supported value */ + bgt spd_fail + rlwimi r7,r6,12,17,19 READ_SPD(27) /* Get tRP value */ beq spd_read_fail - rlwinm r3,r3,30,2,31 /* right shift tRP by 2 bits as per DDR2 spec */ - divwu r6,r3,r9 - mullw r8,r6,r9 - subf. r8,r8,r3 + rlwinm r3,r3,30,2,31 /* right shift tRP by 2 bits as per DDR2 spec */ + divwu r6,r3,r9 + mullw r8,r6,r9 + subf. r8,r8,r3 beq set_trp - addi r6,r6,1 + addi r6,r6,1 set_trp: - li r5,ERR_TRP_FAIL - cmpi 0,0,r6,0x07 /* max supported value */ - bgt spd_fail - rlwimi r7,r6,8,21,23 + li r5,ERR_TRP_FAIL + cmpi 0,0,r6,0x07 /* max supported value */ + bgt spd_fail + rlwimi r7,r6,8,21,23 READ_SPD(36) /* Get tWR value */ beq spd_read_fail - rlwinm r3,r3,30,2,31 /* right shift tWR by 2 bits as per DDR2 spec */ - divwu r6,r3,r9 - mullw r8,r6,r9 - subf. r8,r8,r3 + rlwinm r3,r3,30,2,31 /* right shift tWR by 2 bits as per DDR2 spec */ + divwu r6,r3,r9 + mullw r8,r6,r9 + subf. r8,r8,r3 beq set_twr - addi r6,r6,1 + addi r6,r6,1 set_twr: - addi r6,r6,-1 /* Tsi108 SDC always gives one extra clock */ - li r5,ERR_TWR_FAIL - cmpi 0,0,r6,0x07 /* max supported value */ - bgt spd_fail - rlwimi r7,r6,5,24,26 + addi r6,r6,-1 /* Tsi108 SDC always gives one extra clock */ + li r5,ERR_TWR_FAIL + cmpi 0,0,r6,0x07 /* max supported value */ + bgt spd_fail + rlwimi r7,r6,5,24,26 READ_SPD(42) /* Get tRFC */ beq spd_read_fail - li r5, ERR_TRFC_FAIL + li r5, ERR_TRFC_FAIL /* Tsi108 spec: tRFC=(tRFC + 1)/2 */ - addi r3,r3,1 - rlwinm. r3,r3,31,1,31 /* divide by 2 */ - beq spd_fail - divwu r6,r3,r9 - mullw r8,r6,r9 - subf. r8,r8,r3 + addi r3,r3,1 + rlwinm. r3,r3,31,1,31 /* divide by 2 */ + beq spd_fail + divwu r6,r3,r9 + mullw r8,r6,r9 + subf. r8,r8,r3 beq set_trfc - addi r6,r6,1 + addi r6,r6,1 set_trfc: - cmpi 0,0,r6,0x1F /* max supported value */ - bgt spd_fail - rlwimi r7,r6,0,27,31 + cmpi 0,0,r6,0x1F /* max supported value */ + bgt spd_fail + rlwimi r7,r6,0,27,31 stw r7,SD_TIMING(r4) sync - /*===================================================================== + /* * The following two registers are set on per-DIMM basis. * The SD_REFRESH and SD_TIMING settings are common for both DIMMS - *===================================================================== */ do_each_dimm: - /***************************************** - * Program SDRAM DIMM Control Register - */ + /* Program SDRAM DIMM Control Register */ - li r7, 0 /* clear r7 prior parameter collection */ + li r7, 0 /* clear r7 prior parameter collection */ READ_SPD(13) /* Get Primary SDRAM Width */ beq spd_read_fail - cmpi 0,0,r3,4 /* Check for 4-bit SDRAM */ - beq do_nbank - oris r7,r7,0x0010 /* Set MEM_WIDTH bit */ + cmpi 0,0,r3,4 /* Check for 4-bit SDRAM */ + beq do_nbank + oris r7,r7,0x0010 /* Set MEM_WIDTH bit */ do_nbank: READ_SPD(17) /* Get Number of banks on SDRAM device */ beq spd_read_fail /* Grendel only distinguish betw. 4 or 8-bank memory parts */ - li r5,ERR_UNKNOWN_PART /* non-supported memory part */ - cmpi 0,0,r3,4 - beq do_nrank - cmpi 0,0,r3,8 - bne spd_fail - ori r7,r7,0x1000 + li r5,ERR_UNKNOWN_PART /* non-supported memory part */ + cmpi 0,0,r3,4 + beq do_nrank + cmpi 0,0,r3,8 + bne spd_fail + ori r7,r7,0x1000 do_nrank: - READ_SPD(5) /* Get # of Ranks */ + READ_SPD(5) /* Get # of Ranks */ beq spd_read_fail - li r5,ERR_NRANK_INVALID - andi. r6,r3,0x7 /* Use bits [2..0] only */ - beq do_addr_mode - cmpi 0,0,r6,1 - bgt spd_fail - rlwimi r7,r6,8,23,23 + li r5,ERR_NRANK_INVALID + andi. r6,r3,0x7 /* Use bits [2..0] only */ + beq do_addr_mode + cmpi 0,0,r6,1 + bgt spd_fail + rlwimi r7,r6,8,23,23 do_addr_mode: - READ_SPD(4) /* Get # of Column Addresses */ + READ_SPD(4) /* Get # of Column Addresses */ beq spd_read_fail - li r5, ERR_ADDR_MODE - andi. r3,r3,0x0f /* cut off reserved bits */ - cmpi 0,0,r3,8 - ble spd_fail - cmpi 0,0,r3,15 - bgt spd_fail - addi r6,r3,-8 /* calculate ADDR_MODE parameter */ - rlwimi r7,r6,4,24,27 /* set ADDR_MODE field */ + li r5, ERR_ADDR_MODE + andi. r3,r3,0x0f /* cut off reserved bits */ + cmpi 0,0,r3,8 + ble spd_fail + cmpi 0,0,r3,15 + bgt spd_fail + addi r6,r3,-8 /* calculate ADDR_MODE parameter */ + rlwimi r7,r6,4,24,27 /* set ADDR_MODE field */ set_dimm_ctrl: #ifdef SDC_AUTOPRECH_EN - oris r7,r7,0x0001 /* set auto precharge EN bit */ + oris r7,r7,0x0001 /* set auto precharge EN bit */ #endif - ori r7,r7,1 /* set ENABLE bit */ - cmpi 0,0,r10,SPD_DIMM0 - bne 1f - stw r7,SD_D0_CTRL(r4) + ori r7,r7,1 /* set ENABLE bit */ + cmpi 0,0,r10,SPD_DIMM0 + bne 1f + stw r7,SD_D0_CTRL(r4) sync - b set_dimm_bar + b set_dimm_bar 1: - stw r7,SD_D1_CTRL(r4) + stw r7,SD_D1_CTRL(r4) sync - /******************************************** - * Program SDRAM DIMMx Base Address Register - */ + /* Program SDRAM DIMMx Base Address Register */ set_dimm_bar: READ_SPD(5) /* get # of Ranks */ beq spd_read_fail - andi.r7,r3,0x7 - addi r7,r7,1 - READ_SPD(31) /* Read DIMM rank density */ + andi. r7,r3,0x7 + addi r7,r7,1 + READ_SPD(31) /* Read DIMM rank density */ beq spd_read_fail - rlwinm r5,r3,27,29,31 - rlwinm r6,r3,3,24,28 - or r5,r6,r5 /* r5 = Normalized Rank Density byte */ - lis r8, 0x0080 /* 128MB >> 4 */ - mullw r8,r8,r5 /* r8 = (rank_size >> 4) */ - mullw r8,r8,r7 /* r8 = (DIMM_size >> 4) */ - neg r7,r8 - rlwinm r7,r7,28,4,31 - or r7,r7,r11 /* set ADDR field */ - rlwinm r8,r8,12,20,31 - add r11,r11,r8 /* set Base Addr for next DIMM */ - - cmpi 0,0,r10,SPD_DIMM0 - bne set_dimm1_size - stw r7,SD_D0_BAR(r4) - sync - li r10,SPD_DIMM1 + rlwinm r5,r3,27,29,31 + rlwinm r6,r3,3,24,28 + or r5,r6,r5 /* r5 = Normalized Rank Density byte */ + lis r8, 0x0080 /* 128MB >> 4 */ + mullw r8,r8,r5 /* r8 = (rank_size >> 4) */ + mullw r8,r8,r7 /* r8 = (DIMM_size >> 4) */ + neg r7,r8 + rlwinm r7,r7,28,4,31 + or r7,r7,r11 /* set ADDR field */ + rlwinm r8,r8,12,20,31 + add r11,r11,r8 /* set Base Addr for next DIMM */ + + cmpi 0,0,r10,SPD_DIMM0 + bne set_dimm1_size + stw r7,SD_D0_BAR(r4) + sync + li r10,SPD_DIMM1 READ_SPD(0) bne do_each_dimm b spd_done set_dimm1_size: - stw r7,SD_D1_BAR(r4) + stw r7,SD_D1_BAR(r4) sync spd_done: blr check_next_slot: - cmpi 0,0,r10,SPD_DIMM1 - beq spd_read_fail - li r10,SPD_DIMM1 - b do_first_dimm + cmpi 0,0,r10,SPD_DIMM1 + beq spd_read_fail + li r10,SPD_DIMM1 + b do_first_dimm spd_read_fail: ori r3,r0,0xdead - b err_hung + b err_hung spd_fail: li r3,0x0bad sync -err_hung: /* hang here for debugging */ - nop - nop - b err_hung +err_hung: /* hang here for debugging */ + nop + nop + b err_hung #endif /* !SDC_HARDCODED_INIT */ - diff --git a/board/mpc7448hpc2/mpc7448hpc2.c b/board/mpc7448hpc2/mpc7448hpc2.c index f90a75124a..4d221e7a69 100644 --- a/board/mpc7448hpc2/mpc7448hpc2.c +++ b/board/mpc7448hpc2/mpc7448hpc2.c @@ -25,7 +25,7 @@ */ /* - * board support/init functions for the + * board support/init functions for the * Freescale MPC7448 HPC2 (High-Performance Computing 2 Platform). */ @@ -33,39 +33,38 @@ #include <74xx_7xx.h> #if defined(CONFIG_OF_FLAT_TREE) #include -extern void ft_cpu_setup(void *blob, bd_t *bd); +extern void ft_cpu_setup (void *blob, bd_t *bd); #endif #undef DEBUG -extern void flush_data_cache(void); -extern void invalidate_l1_instruction_cache(void); -extern void tsi108_init_f(void); +extern void flush_data_cache (void); +extern void invalidate_l1_instruction_cache (void); +extern void tsi108_init_f (void); -int display_mem_map(void); +int display_mem_map (void); -void after_reloc(ulong dest_addr) +void after_reloc (ulong dest_addr) { DECLARE_GLOBAL_DATA_PTR; /* * Jump to the main U-Boot board init code */ - board_init_r((gd_t *) gd, dest_addr); + board_init_r ((gd_t *) gd, dest_addr); /* NOTREACHED */ } /* * Check Board Identity: - * * report board type */ -int checkboard(void) +int checkboard (void) { int l_type = 0; - printf("BOARD: %s\n", CFG_BOARD_NAME); + printf ("BOARD: %s\n", CFG_BOARD_NAME); return (l_type); } @@ -75,19 +74,19 @@ int checkboard(void) * report calling processor number */ -int read_pid(void) +int read_pid (void) { return 0; /* we are on single CPU platform for a while */ } -long int dram_size(int board_type) +long int dram_size (int board_type) { return 0x20000000; /* 256M bytes */ } -long int initdram(int board_type) +long int initdram (int board_type) { - return dram_size(board_type); + return dram_size (board_type); } /* DRAM check routines copied from gw8260 */ @@ -114,11 +113,11 @@ long int initdram(int board_type) /* May cloober fr0. */ /* */ /*********************************************************************/ -static void move64(unsigned long long *src, unsigned long long *dest) +static void move64 (unsigned long long *src, unsigned long long *dest) { - asm("lfd 0, 0(3)\n\t" /* fpr0 = *scr */ - "stfd 0, 0(4)" /* *dest = fpr0 */ - : : :"fr0"); /* Clobbers fr0 */ + asm ("lfd 0, 0(3)\n\t" /* fpr0 = *scr */ + "stfd 0, 0(4)" /* *dest = fpr0 */ + : : :"fr0"); /* Clobbers fr0 */ return; } @@ -183,28 +182,28 @@ unsigned long long pattern[] = { /* Assumes only one one SDRAM bank */ /* */ /*********************************************************************/ -int mem_test_data(void) +int mem_test_data (void) { unsigned long long *pmem = (unsigned long long *)CFG_MEMTEST_START; unsigned long long temp64; - int num_patterns = sizeof(pattern) / sizeof(pattern[0]); + int num_patterns = sizeof (pattern) / sizeof (pattern[0]); int i; unsigned int hi, lo; for (i = 0; i < num_patterns; i++) { - move64(&(pattern[i]), pmem); - move64(pmem, &temp64); + move64 (&(pattern[i]), pmem); + move64 (pmem, &temp64); - /* hi = (temp64>>32) & 0xffffffff; */ - /* lo = temp64 & 0xffffffff; */ - /* printf("\ntemp64 = 0x%08x%08x", hi, lo); */ + /* hi = (temp64>>32) & 0xffffffff; */ + /* lo = temp64 & 0xffffffff; */ + /* printf ("\ntemp64 = 0x%08x%08x", hi, lo); */ hi = (pattern[i] >> 32) & 0xffffffff; lo = pattern[i] & 0xffffffff; - /* printf("\npattern[%d] = 0x%08x%08x", i, hi, lo); */ + /* printf ("\npattern[%d] = 0x%08x%08x", i, hi, lo); */ if (temp64 != pattern[i]) { - printf("\n Data Test Failed, pattern 0x%08x%08x", + printf ("\n Data Test Failed, pattern 0x%08x%08x", hi, lo); return 1; } @@ -236,7 +235,7 @@ int mem_test_data(void) /* */ /* */ /*********************************************************************/ -int mem_test_address(void) +int mem_test_address (void) { volatile unsigned int *pmem = (volatile unsigned int *)CFG_MEMTEST_START; @@ -251,13 +250,13 @@ int mem_test_address(void) /* verify each loaction */ for (i = 0; i < size; i++) { if (pmem[i] != i) { - printf("\n Address Test Failed at 0x%x", i); + printf ("\n Address Test Failed at 0x%x", i); return 1; } } return 0; } -#endif /* CFG_DRAM_TEST_ADDRESS */ +#endif /* CFG_DRAM_TEST_ADDRESS */ #if defined (CFG_DRAM_TEST_WALK) /*********************************************************************/ @@ -287,7 +286,7 @@ int mem_test_address(void) /* */ /* */ /*********************************************************************/ -int mem_march(volatile unsigned long long *base, +int mem_march (volatile unsigned long long *base, unsigned int size, unsigned long long rmask, unsigned long long wmask, short read, short write) @@ -299,14 +298,14 @@ int mem_march(volatile unsigned long long *base, for (i = 0; i < size; i++) { if (read != 0) { /* temp = base[i]; */ - move64((unsigned long long *)&(base[i]), &temp); + move64 ((unsigned long long *)&(base[i]), &temp); if (rmask != temp) { hitemp = (temp >> 32) & 0xffffffff; lotemp = temp & 0xffffffff; himask = (rmask >> 32) & 0xffffffff; lomask = rmask & 0xffffffff; - printf("\n Walking one's test failed: \ + printf ("\n Walking one's test failed: \ address = 0x%08x," "\n\texpected \ 0x%08x%08x, found 0x%08x%08x", i << 3,\ himask, lomask, hitemp, lotemp); @@ -315,12 +314,12 @@ int mem_march(volatile unsigned long long *base, } if (write != 0) { /* base[i] = wmask; */ - move64(&wmask, (unsigned long long *)&(base[i])); + move64 (&wmask, (unsigned long long *)&(base[i])); } } return 0; } -#endif /* CFG_DRAM_TEST_WALK */ +#endif /* CFG_DRAM_TEST_WALK */ /*********************************************************************/ /* NAME: mem_test_walk() - a simple walking ones test */ @@ -348,7 +347,7 @@ int mem_march(volatile unsigned long long *base, /* */ /* */ /*********************************************************************/ -int mem_test_walk(void) +int mem_test_walk (void) { unsigned long long mask; volatile unsigned long long *pmem = @@ -359,32 +358,31 @@ int mem_test_walk(void) mask = 0x01; - printf("Initial Pass"); - mem_march(pmem, size, 0x0, 0x1, 0, 1); + printf ("Initial Pass"); + mem_march (pmem, size, 0x0, 0x1, 0, 1); - printf("\b\b\b\b\b\b\b\b\b\b\b\b"); - printf(" "); - printf(" "); - printf("\b\b\b\b\b\b\b\b\b\b\b\b"); + printf ("\b\b\b\b\b\b\b\b\b\b\b\b"); + printf (" "); + printf (" "); + printf ("\b\b\b\b\b\b\b\b\b\b\b\b"); for (i = 0; i < 63; i++) { - printf("Pass %2d", i + 2); - if (mem_march(pmem, size, mask, mask << 1, 1, 1) != 0) { - /*printf("mask: 0x%x, pass: %d, ", mask, i); */ + printf ("Pass %2d", i + 2); + if (mem_march(pmem, size, mask, mask << 1, 1, 1) != 0) + /*printf ("mask: 0x%x, pass: %d, ", mask, i); */ return 1; - } mask = mask << 1; - printf("\b\b\b\b\b\b\b"); + printf ("\b\b\b\b\b\b\b"); } - printf("Last Pass"); + printf ("Last Pass"); if (mem_march(pmem, size, 0, mask, 0, 1) != 0) { - /* printf("mask: 0x%x", mask); */ + /* printf ("mask: 0x%x", mask); */ return 1; } - printf("\b\b\b\b\b\b\b\b\b"); - printf(" "); - printf("\b\b\b\b\b\b\b\b\b"); + printf ("\b\b\b\b\b\b\b\b\b"); + printf (" "); + printf ("\b\b\b\b\b\b\b\b\b"); return 0; } @@ -412,60 +410,58 @@ int mem_test_walk(void) /* */ /* */ /*********************************************************************/ -int testdram(void) +int testdram (void) { char *s; int rundata, runaddress, runwalk; - s = getenv("testdramdata"); + s = getenv ("testdramdata"); rundata = (s && (*s == 'y')) ? 1 : 0; - s = getenv("testdramaddress"); + s = getenv ("testdramaddress"); runaddress = (s && (*s == 'y')) ? 1 : 0; - s = getenv("testdramwalk"); + s = getenv ("testdramwalk"); runwalk = (s && (*s == 'y')) ? 1 : 0; /* rundata = 1; */ /* runaddress = 0; */ /* runwalk = 0; */ - if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) { - printf("Testing RAM from 0x%08x to 0x%08x ... \ + if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) + printf ("Testing RAM from 0x%08x to 0x%08x ... \ (don't panic... that will take a moment !!!!)\n", \ CFG_MEMTEST_START, CFG_MEMTEST_END); - } #ifdef CFG_DRAM_TEST_DATA if (rundata == 1) { - printf("Test DATA ... "); + printf ("Test DATA ... "); if (mem_test_data () == 1) { - printf("failed \n"); + printf ("failed \n"); return 1; } else - printf("ok \n"); + printf ("ok \n"); } #endif #ifdef CFG_DRAM_TEST_ADDRESS if (runaddress == 1) { - printf("Test ADDRESS ... "); + printf ("Test ADDRESS ... "); if (mem_test_address () == 1) { - printf("failed \n"); + printf ("failed \n"); return 1; } else - printf("ok \n"); + printf ("ok \n"); } #endif #ifdef CFG_DRAM_TEST_WALK if (runwalk == 1) { - printf("Test WALKING ONEs ... "); - if (mem_test_walk() == 1) { - printf("failed \n"); + printf ("Test WALKING ONEs ... "); + if (mem_test_walk () == 1) { + printf ("failed \n"); return 1; } else - printf("ok \n"); + printf ("ok \n"); } #endif - if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) { - printf("passed\n"); - } + if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) + printf ("passed\n"); return 0; } @@ -473,17 +469,17 @@ int testdram(void) #if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) void -ft_board_setup(void *blob, bd_t *bd) +ft_board_setup (void *blob, bd_t *bd) { u32 *p; int len; - ft_cpu_setup(blob, bd); + ft_cpu_setup (blob, bd); - p = ft_get_prop(blob, "/memory/reg", &len); + p = ft_get_prop (blob, "/memory/reg", &len); if (p != NULL) { - *p++ = cpu_to_be32(bd->bi_memstart); - *p = cpu_to_be32(bd->bi_memsize); + *p++ = cpu_to_be32 (bd->bi_memstart); + *p = cpu_to_be32 (bd->bi_memsize); } } #endif diff --git a/board/mpc7448hpc2/tsi108_init.c b/board/mpc7448hpc2/tsi108_init.c index 6f517f5a2e..fdb53653d1 100644 --- a/board/mpc7448hpc2/tsi108_init.c +++ b/board/mpc7448hpc2/tsi108_init.c @@ -1,6 +1,6 @@ /***************************************************************************** * (C) Copyright 2003; Tundra Semiconductor Corp. - * + * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of @@ -33,7 +33,7 @@ #include #include -extern void mpicInit(int verbose); +extern void mpicInit (int verbose); /* * Configuration Options @@ -118,11 +118,11 @@ static PLL_CTRL_SET pll0_config[8] = { static int pb_clk_sel[8] = { 0, 0, 183, 100, 133, 167, 200, 233 }; /* - * get_board_bus_clk() + * get_board_bus_clk () * * returns the bus clock in Hz. */ -unsigned long get_board_bus_clk(void) +unsigned long get_board_bus_clk (void) { ulong i; @@ -134,37 +134,38 @@ unsigned long get_board_bus_clk(void) } /* - * board_early_init_f() + * board_early_init_f () * * board-specific initialization executed from flash */ -int board_early_init_f(void) +int board_early_init_f (void) { DECLARE_GLOBAL_DATA_PTR; ulong i; gd->mem_clk = 0; - i = in32(CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PWRUP_STATUS); - i = (i >> 20) & 0x07; + i = in32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + + CG_PWRUP_STATUS); + i = (i >> 20) & 0x07; /* value of SW4[4:7] */ switch (i) { - case 0: - printf("Using external clock\n"); + case 0: /* external clock */ + printf ("Using external clock\n"); break; - case 1: + case 1: /* system clock */ gd->mem_clk = gd->bus_clk; break; - case 4: - case 5: - case 6: + case 4: /* 133 MHz */ + case 5: /* 166 MHz */ + case 6: /* 200 MHz */ gd->mem_clk = pb_clk_sel[i] * 1000000; break; default: - printf("Invalid DDR2 clock setting\n"); + printf ("Invalid DDR2 clock setting\n"); return -1; } - printf("BUS! %d MHz\n", get_board_bus_clk() / 1000000); - printf("MEM! %d MHz\n", gd->mem_clk / 1000000); + printf ("BUS: %d MHz\n", get_board_bus_clk() / 1000000); + printf ("MEM: %d MHz\n", gd->mem_clk / 1000000); return 0; } @@ -173,175 +174,174 @@ int board_early_init_f(void) * relocation. Contains code that cannot be executed from flash. */ -int board_early_init_r(void) +int board_early_init_r (void) { ulong temp, i; ulong reg_val; volatile ulong *reg_ptr; reg_ptr = - (ulong *) (CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + 0x900); + (ulong *) (CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + 0x900); for (i = 0; i < 32; i++) { *reg_ptr++ = 0x00000201; /* SWAP ENABLED */ *reg_ptr++ = 0x00; } - __asm__ __volatile__("eieio"); - __asm__ __volatile__("sync"); + __asm__ __volatile__ ("eieio"); + __asm__ __volatile__ ("sync"); /* Setup PB_OCN_BAR2: size 256B + ENable @ 0x0_80000000 */ - out32(CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR2, - 0x80000001); - __asm__ __volatile__("sync"); + out32 (CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR2, + 0x80000001); + __asm__ __volatile__ ("sync"); /* Make sure that OCN_BAR2 decoder is set (to allow following immediate - * read from SDRAM) + * read from SDRAM) */ temp = in32(CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR2); - __asm__ __volatile__("sync"); + __asm__ __volatile__ ("sync"); /* * Remap PB_OCN_BAR1 to accomodate PCI-bus aperture and EPROM into the * processor bus address space. Immediately after reset LUT and address * translation are disabled for this BAR. Now we have to initialize LUT * and switch from the BOOT mode to the normal operation mode. - * + * * The aperture defined by PB_OCN_BAR1 startes at address 0xE0000000 - * and covers 512MB of address space. To allow larger aperture we also + * and covers 512MB of address space. To allow larger aperture we also * have to relocate register window of Tsi108 * - * Initialize LUT (32-entries) prior switching PB_OCN_BAR1 from BOOT + * Initialize LUT (32-entries) prior switching PB_OCN_BAR1 from BOOT * mode. - * + * * initialize pointer to LUT associated with PB_OCN_BAR1 */ reg_ptr = - (ulong *) (CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + 0x800); + (ulong *) (CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + 0x800); for (i = 0; i < 32; i++) { *reg_ptr++ = pb2ocn_lut1[i].lower; *reg_ptr++ = pb2ocn_lut1[i].upper; } - __asm__ __volatile__("sync"); + __asm__ __volatile__ ("sync"); /* Base addresses for Cs0, CS1, CS2, CS3 */ - out32(CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_ADDR, - 0x00000000); - __asm__ __volatile__("sync"); + out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_ADDR, + 0x00000000); + __asm__ __volatile__ ("sync"); - out32(CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_ADDR, - 0x00100000); - __asm__ __volatile__("sync"); + out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_ADDR, + 0x00100000); + __asm__ __volatile__ ("sync"); - out32(CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_ADDR, - 0x00200000); - __asm__ __volatile__("sync"); + out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_ADDR, + 0x00200000); + __asm__ __volatile__ ("sync"); - out32(CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_ADDR, - 0x00300000); - __asm__ __volatile__("sync"); + out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_ADDR, + 0x00300000); + __asm__ __volatile__ ("sync"); /* Masks for HLP banks */ - out32(CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_MASK, - 0xFFF00000); - __asm__ __volatile__("sync"); + out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_MASK, + 0xFFF00000); + __asm__ __volatile__ ("sync"); - out32(CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_MASK, - 0xFFF00000); - __asm__ __volatile__("sync"); + out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_MASK, + 0xFFF00000); + __asm__ __volatile__ ("sync"); - out32(CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_MASK, - 0xFFF00000); - __asm__ __volatile__("sync"); + out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_MASK, + 0xFFF00000); + __asm__ __volatile__ ("sync"); - out32(CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_MASK, - 0xFFF00000); - __asm__ __volatile__("sync"); + out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_MASK, + 0xFFF00000); + __asm__ __volatile__ ("sync"); /* Set CTRL0 values for banks */ - out32(CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_CTRL0, - 0x7FFC44C2); - __asm__ __volatile__("sync"); + out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_CTRL0, + 0x7FFC44C2); + __asm__ __volatile__ ("sync"); - out32(CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_CTRL0, - 0x7FFC44C0); - __asm__ __volatile__("sync"); + out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_CTRL0, + 0x7FFC44C0); + __asm__ __volatile__ ("sync"); - out32(CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_CTRL0, - 0x7FFC44C0); - __asm__ __volatile__("sync"); + out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_CTRL0, + 0x7FFC44C0); + __asm__ __volatile__ ("sync"); - out32(CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_CTRL0, - 0x7FFC44C2); - __asm__ __volatile__("sync"); + out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_CTRL0, + 0x7FFC44C2); + __asm__ __volatile__ ("sync"); /* Set banks to latched mode, enabled, and other default settings */ - out32(CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_CTRL1, - 0x7C0F2000); - __asm__ __volatile__("sync"); + out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_CTRL1, + 0x7C0F2000); + __asm__ __volatile__ ("sync"); - out32(CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_CTRL1, - 0x7C0F2000); - __asm__ __volatile__("sync"); + out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_CTRL1, + 0x7C0F2000); + __asm__ __volatile__ ("sync"); - out32(CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_CTRL1, - 0x7C0F2000); - __asm__ __volatile__("sync"); + out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_CTRL1, + 0x7C0F2000); + __asm__ __volatile__ ("sync"); - out32(CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_CTRL1, - 0x7C0F2000); - __asm__ __volatile__("sync"); + out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_CTRL1, + 0x7C0F2000); + __asm__ __volatile__ ("sync"); /* * Set new value for PB_OCN_BAR1: switch from BOOT to LUT mode. * value for PB_OCN_BAR1: (BA-0xE000_0000 + size 512MB + ENable) */ - out32(CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR1, - 0xE0000011); - __asm__ __volatile__("sync"); + out32 (CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR1, + 0xE0000011); + __asm__ __volatile__ ("sync"); - /* Make sure that OCN_BAR2 decoder is set (to allow following - * immediate read from SDRAM) + /* Make sure that OCN_BAR2 decoder is set (to allow following + * immediate read from SDRAM) */ - + temp = in32(CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR1); - __asm__ __volatile__("sync"); + __asm__ __volatile__ ("sync"); /* * SRI: At this point we have enabled the HLP banks. That means we can * now read from the NVRAM and initialize the environment variables. * We will over-ride the env_init called in board_init_f * This is really a work-around because, the HLP bank 1 - * where NVRAM resides is not visible during board_init_f + * where NVRAM resides is not visible during board_init_f * (lib_ppc/board.c) * Alternatively, we could use the I2C EEPROM at start-up to configure * and enable all HLP banks and not just HLP 0 as is being done for * Taiga Rev. 2. */ - env_init(); + env_init (); #ifndef DISABLE_PBM /* - * For IBM processors we have to set Address-Only commands generated + * For IBM processors we have to set Address-Only commands generated * by PBM that are different from ones set after reset. */ - temp = get_cpu_type(); + temp = get_cpu_type (); - if ((CPU_750FX == temp) || (CPU_750GX == temp)) { - out32(CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_MCMD, - 0x00009955); - } + if ((CPU_750FX == temp) || (CPU_750GX == temp)) + out32 (CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_MCMD, + 0x00009955); #endif /* DISABLE_PBM */ #ifdef CONFIG_PCI @@ -350,42 +350,42 @@ int board_early_init_r(void) */ /* Map PCI/X Configuration Space (16MB @ 0x0_FE000000) */ - out32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_BAR0_UPPER, - 0); - __asm__ __volatile__("sync"); + out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + + PCI_PFAB_BAR0_UPPER, 0); + __asm__ __volatile__ ("sync"); - out32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_BAR0, - 0xFB000001); - __asm__ __volatile__("sync"); + out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_BAR0, + 0xFB000001); + __asm__ __volatile__ ("sync"); /* Set Bus Number for the attached PCI/X bus (we will use 0 for NB) */ - temp = - in32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PCIX_STAT); + temp = in32(CFG_TSI108_CSR_BASE + + TSI108_PCI_REG_OFFSET + PCI_PCIX_STAT); temp &= ~0xFF00; /* Clear the BUS_NUM field */ - out32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PCIX_STAT, - temp); + out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PCIX_STAT, + temp); /* Map PCI/X IO Space (64KB @ 0x0_FD000000) takes one 16MB LUT entry */ - out32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_IO_UPPER, - 0); - __asm__ __volatile__("sync"); + out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_IO_UPPER, + 0); + __asm__ __volatile__ ("sync"); /* This register is on the PCI side to interpret the address it receives - * and maps it as a IO address. + * and maps it as a IO address. */ - out32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_IO, - 0xFA000001); - __asm__ __volatile__("sync"); + out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_IO, + 0xFA000001); + __asm__ __volatile__ ("sync"); /* * Map PCI/X Memory Space * - * Transactions directed from OCM to PCI Memory Space are directed + * Transactions directed from OCM to PCI Memory Space are directed * from PB to PCI * unchanged (as defined by PB_OCN_BAR1,2 and LUT settings). * If address remapping is required the corresponding PCI_PFAB_MEM32 @@ -393,7 +393,7 @@ int board_early_init_r(void) * * Map the path from the PCI/X bus into the system memory * - * The memory mapped window assotiated with PCI P2O_BAR2 provides + * The memory mapped window assotiated with PCI P2O_BAR2 provides * access to the system memory without address remapping. * All system memory is opened for accesses initiated by PCI/X bus * masters. @@ -404,13 +404,13 @@ int board_early_init_r(void) */ reg_ptr = - (ulong *) (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + 0x500); + (ulong *) (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + 0x500); #ifdef DISABLE_PBM - /* In case when PBM is disabled (no HW supported cache snoopng on PB) - * P2O_BAR2 is directly mapped into the system memory without address - * translation. + /* In case when PBM is disabled (no HW supported cache snoopng on PB) + * P2O_BAR2 is directly mapped into the system memory without address + * translation. */ reg_val = 0x00000004; /* SDRAM port + NO Addr_Translation */ @@ -438,30 +438,30 @@ int board_early_init_r(void) reg_val = 0x00007100; #endif - __asm__ __volatile__("eieio"); - __asm__ __volatile__("sync"); + __asm__ __volatile__ ("eieio"); + __asm__ __volatile__ ("sync"); - out32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_PAGE_SIZES, - reg_val); - __asm__ __volatile__("sync"); + out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_PAGE_SIZES, + reg_val); + __asm__ __volatile__ ("sync"); - /* Set 64-bit PCI bus address for system memory - * ( 0 is the best choice for easy mapping) + /* Set 64-bit PCI bus address for system memory + * ( 0 is the best choice for easy mapping) */ - out32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR2, - 0x00000000); - out32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR2_UPPER, - 0x00000000); - __asm__ __volatile__("sync"); + out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR2, + 0x00000000); + out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR2_UPPER, + 0x00000000); + __asm__ __volatile__ ("sync"); #ifndef DISABLE_PBM /* - * The memory mapped window assotiated with PCI P2O_BAR3 provides - * access to the system memory using SDRAM OCN port and address - * translation. This is alternative way to access SDRAM from PCI + * The memory mapped window assotiated with PCI P2O_BAR3 provides + * access to the system memory using SDRAM OCN port and address + * translation. This is alternative way to access SDRAM from PCI * required for Tsi108 emulation testing. - * All system memory is opened for accesses initiated by + * All system memory is opened for accesses initiated by * PCI/X bus masters. * * Initialize LUT associated with PCI P2O_BAR3 @@ -469,7 +469,7 @@ int board_early_init_r(void) * set pointer to LUT associated with PCI P2O_BAR3 */ reg_ptr = - (ulong *) (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + 0x600); + (ulong *) (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + 0x600); reg_val = 0x00000004; /* Destination port = SDC */ @@ -483,45 +483,45 @@ int board_early_init_r(void) reg_val += 0x01000000; } - __asm__ __volatile__("eieio"); - __asm__ __volatile__("sync"); + __asm__ __volatile__ ("eieio"); + __asm__ __volatile__ ("sync"); /* Configure PCI P2O_BAR3 (size = 512MB, Enabled) */ reg_val = - in32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + + in32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_PAGE_SIZES); reg_val &= ~0x00FF; reg_val |= 0x0071; - out32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_PAGE_SIZES, - reg_val); - __asm__ __volatile__("sync"); + out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_PAGE_SIZES, + reg_val); + __asm__ __volatile__ ("sync"); /* Set 64-bit base PCI bus address for window (0x20000000) */ - out32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR3_UPPER, - 0x00000000); - out32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR3, - 0x20000000); - __asm__ __volatile__("sync"); + out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR3_UPPER, + 0x00000000); + out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR3, + 0x20000000); + __asm__ __volatile__ ("sync"); #endif /* !DISABLE_PBM */ #ifdef ENABLE_PCI_CSR_BAR /* open if required access to Tsi108 CSRs from the PCI/X bus */ /* enable BAR0 on the PCI/X bus */ - reg_val = - in32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_MISC_CSR); + reg_val = in32(CFG_TSI108_CSR_BASE + + TSI108_PCI_REG_OFFSET + PCI_MISC_CSR); reg_val |= 0x02; - out32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_MISC_CSR, - reg_val); - __asm__ __volatile__("sync"); + out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_MISC_CSR, + reg_val); + __asm__ __volatile__ ("sync"); - out32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR0_UPPER, - 0x00000000); - out32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR0, - CFG_TSI108_CSR_BASE); - __asm__ __volatile__("sync"); + out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR0_UPPER, + 0x00000000); + out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR0, + CFG_TSI108_CSR_BASE); + __asm__ __volatile__ ("sync"); #endif @@ -531,32 +531,32 @@ int board_early_init_r(void) reg_val = in32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_CSR); reg_val |= 0x06; - out32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_CSR, reg_val); - __asm__ __volatile__("sync"); + out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_CSR, reg_val); + __asm__ __volatile__ ("sync"); #endif /* CONFIG_PCI */ /* * Initialize MPIC outputs (interrupt pins): * Interrupt routing on the Grendel Emul. Board: - * PB_INT[0] -> INT (CPU0) - * PB_INT[1] -> INT (CPU1) - * PB_INT[2] -> MCP (CPU0) - * PB_INT[3] -> MCP (CPU1) + * PB_INT[0] -> INT (CPU0) + * PB_INT[1] -> INT (CPU1) + * PB_INT[2] -> MCP (CPU0) + * PB_INT[3] -> MCP (CPU1) * Set interrupt controller outputs as Level_Sensitive/Active_Low */ - out32(CFG_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(0), 0x02); - out32(CFG_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(1), 0x02); - out32(CFG_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(2), 0x02); - out32(CFG_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(3), 0x02); - __asm__ __volatile__("sync"); + out32 (CFG_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(0), 0x02); + out32 (CFG_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(1), 0x02); + out32 (CFG_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(2), 0x02); + out32 (CFG_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(3), 0x02); + __asm__ __volatile__ ("sync"); /* * Ensure that Machine Check exception is enabled * We need it to support PCI Bus probing (configuration reads) */ - reg_val = mfmsr(); + reg_val = mfmsr (); mtmsr(reg_val | MSR_ME); return 0; @@ -567,7 +567,7 @@ int board_early_init_r(void) * used in the misc_init_r function */ -unsigned long get_l2cr(void) +unsigned long get_l2cr (void) { unsigned long l2controlreg; asm volatile ("mfspr %0, 1017":"=r" (l2controlreg):); @@ -581,79 +581,82 @@ unsigned long get_l2cr(void) * */ -int misc_init_r(void) +int misc_init_r (void) { DECLARE_GLOBAL_DATA_PTR; #ifdef CFG_CLK_SPREAD /* Initialize Spread-Spectrum Clock generation */ ulong i; /* Ensure that Spread-Spectrum is disabled */ - out32(CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL0, 0); - out32(CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0, 0); + out32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL0, 0); + out32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0, 0); /* Initialize PLL1: CG_PCI_CLK , internal OCN_CLK * Uses pre-calculated value for Fout = 800 MHz, Fs = 30 kHz, D = 0.5% */ - out32(CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0, 0x002e0044); /* D = 0.25% */ - out32(CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL1, 0x00000039); /* BWADJ */ + out32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0, + 0x002e0044); /* D = 0.25% */ + out32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL1, + 0x00000039); /* BWADJ */ /* Initialize PLL0: CG_PB_CLKO */ /* Detect PB clock freq. */ i = in32(CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PWRUP_STATUS); i = (i >> 16) & 0x07; /* Get PB PLL multiplier */ - out32(CFG_TSI108_CSR_BASE + - TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL0, pll0_config[i].ctrl0); - out32(CFG_TSI108_CSR_BASE + - TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL1, pll0_config[i].ctrl1); + out32 (CFG_TSI108_CSR_BASE + + TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL0, pll0_config[i].ctrl0); + out32 (CFG_TSI108_CSR_BASE + + TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL1, pll0_config[i].ctrl1); /* Wait and set SSEN for both PLL0 and 1 */ - udelay(1000); - out32(CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0, 0x802e0044); /* D=0.25% */ - out32(CFG_TSI108_CSR_BASE + - TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL0, - 0x80000000 | pll0_config[i].ctrl0); + udelay (1000); + out32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0, + 0x802e0044); /* D=0.25% */ + out32 (CFG_TSI108_CSR_BASE + + TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL0, + 0x80000000 | pll0_config[i].ctrl0); #endif /* CFG_CLK_SPREAD */ #ifdef CFG_L2 - l2cache_enable(); + l2cache_enable (); #endif - printf("BUS: %d MHz\n", gd->bus_clk / 1000000); - printf("MEM: %d MHz\n", gd->mem_clk / 1000000); + printf ("BUS: %d MHz\n", gd->bus_clk / 1000000); + printf ("MEM: %d MHz\n", gd->mem_clk / 1000000); /* - * All the information needed to print the cache details is avaiblable - * at this point i.e. above call to l2cache_enable is the very last - * thing done with regards to enabling diabling the cache. + * All the information needed to print the cache details is avaiblable + * at this point i.e. above call to l2cache_enable is the very last + * thing done with regards to enabling diabling the cache. * So this seems like a good place to print all this information */ - printf("CACHE: "); + printf ("CACHE: "); switch (get_cpu_type()) { case CPU_7447A: - printf("L1 Instruction cache - 32KB 8-way"); - (get_hid0() & (1 << 15)) ? printf(" ENABLED\n") : - printf(" DISABLED\n"); - printf(" L1 Data cache - 32KB 8-way"); - (get_hid0() & (1 << 14)) ? printf(" ENABLED\n") : - printf(" DISABLED\n"); - printf(" Unified L2 cache - 512KB 8-way"); - (get_l2cr() & (1 << 31)) ? printf(" ENABLED\n") : - printf(" DISABLED\n"); - printf("\n"); + printf ("L1 Instruction cache - 32KB 8-way"); + (get_hid0 () & (1 << 15)) ? printf (" ENABLED\n") : + printf (" DISABLED\n"); + printf ("L1 Data cache - 32KB 8-way"); + (get_hid0 () & (1 << 14)) ? printf (" ENABLED\n") : + printf (" DISABLED\n"); + printf ("Unified L2 cache - 512KB 8-way"); + (get_l2cr () & (1 << 31)) ? printf (" ENABLED\n") : + printf (" DISABLED\n"); + printf ("\n"); break; case CPU_7448: - printf("L1 Instruction cache - 32KB 8-way"); - (get_hid0() & (1 << 15)) ? printf(" ENABLED\n") : - printf(" DISABLED\n"); - printf(" L1 Data cache - 32KB 8-way"); - (get_hid0() & (1 << 14)) ? printf(" ENABLED\n") : - printf(" DISABLED\n"); - printf(" Unified L2 cache - 1MB 8-way"); - (get_l2cr() & (1 << 31)) ? printf(" ENABLED\n") : - printf(" DISABLED\n"); + printf ("L1 Instruction cache - 32KB 8-way"); + (get_hid0 () & (1 << 15)) ? printf (" ENABLED\n") : + printf (" DISABLED\n"); + printf ("L1 Data cache - 32KB 8-way"); + (get_hid0 () & (1 << 14)) ? printf (" ENABLED\n") : + printf (" DISABLED\n"); + printf ("Unified L2 cache - 1MB 8-way"); + (get_l2cr () & (1 << 31)) ? printf (" ENABLED\n") : + printf (" DISABLED\n"); break; default: break; -- cgit From 6f12c61cf31ed73d72ddfcfc712a854a3a177aaf Mon Sep 17 00:00:00 2001 From: roy zang Date: Mon, 4 Dec 2006 14:33:08 +0800 Subject: Remove the duplicate memory test code for mpc744ihpc2 board. If a memory test is needed, please use the functions in post/memory.c or memtest command. Signed-off-by: Roy Zang --- board/mpc7448hpc2/mpc7448hpc2.c | 378 ---------------------------------------- 1 file changed, 378 deletions(-) (limited to 'board/mpc7448hpc2') diff --git a/board/mpc7448hpc2/mpc7448hpc2.c b/board/mpc7448hpc2/mpc7448hpc2.c index 4d221e7a69..d4a047c1d6 100644 --- a/board/mpc7448hpc2/mpc7448hpc2.c +++ b/board/mpc7448hpc2/mpc7448hpc2.c @@ -89,384 +89,6 @@ long int initdram (int board_type) return dram_size (board_type); } -/* DRAM check routines copied from gw8260 */ - -#if defined (CFG_DRAM_TEST) - -/*********************************************************************/ -/* NAME: move64() - moves a double word (64-bit) */ -/* */ -/* DESCRIPTION: */ -/* this function performs a double word move from the data at */ -/* the source pointer to the location at the destination pointer. */ -/* */ -/* INPUTS: */ -/* unsigned long long *src - pointer to data to move */ -/* */ -/* OUTPUTS: */ -/* unsigned long long *dest - pointer to locate to move data */ -/* */ -/* RETURNS: */ -/* None */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* May cloober fr0. */ -/* */ -/*********************************************************************/ -static void move64 (unsigned long long *src, unsigned long long *dest) -{ - asm ("lfd 0, 0(3)\n\t" /* fpr0 = *scr */ - "stfd 0, 0(4)" /* *dest = fpr0 */ - : : :"fr0"); /* Clobbers fr0 */ - return; -} - -#if defined (CFG_DRAM_TEST_DATA) - -unsigned long long pattern[] = { - 0xaaaaaaaaaaaaaaaaULL, - 0xccccccccccccccccULL, - 0xf0f0f0f0f0f0f0f0ULL, - 0xff00ff00ff00ff00ULL, - 0xffff0000ffff0000ULL, - 0xffffffff00000000ULL, - 0x00000000ffffffffULL, - 0x0000ffff0000ffffULL, - 0x00ff00ff00ff00ffULL, - 0x0f0f0f0f0f0f0f0fULL, - 0x3333333333333333ULL, - 0x5555555555555555ULL -}; - -/*********************************************************************/ -/* NAME: mem_test_data() - test data lines for shorts and opens */ -/* */ -/* DESCRIPTION: */ -/* Tests data lines for shorts and opens by forcing adjacent data */ -/* to opposite states. Because the data lines could be routed in */ -/* an arbitrary manner the must ensure test patterns ensure that */ -/* every case is tested. By using the following series of binary */ -/* patterns every combination of adjacent bits is test regardless */ -/* of routing. */ -/* */ -/* ...101010101010101010101010 */ -/* ...110011001100110011001100 */ -/* ...111100001111000011110000 */ -/* ...111111110000000011111111 */ -/* */ -/* Carrying this out, gives us six hex patterns as follows: */ -/* */ -/* 0xaaaaaaaaaaaaaaaa */ -/* 0xcccccccccccccccc */ -/* 0xf0f0f0f0f0f0f0f0 */ -/* 0xff00ff00ff00ff00 */ -/* 0xffff0000ffff0000 */ -/* 0xffffffff00000000 */ -/* */ -/* The number test patterns will always be given by: */ -/* */ -/* log(base 2)(number data bits) = log2 (64) = 6 */ -/* */ -/* To test for short and opens to other signals on our boards. we */ -/* simply */ -/* test with the 1's complemnt of the paterns as well. */ -/* */ -/* OUTPUTS: */ -/* Displays failing test pattern */ -/* */ -/* RETURNS: */ -/* 0 - Passed test */ -/* 1 - Failed test */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* Assumes only one one SDRAM bank */ -/* */ -/*********************************************************************/ -int mem_test_data (void) -{ - unsigned long long *pmem = (unsigned long long *)CFG_MEMTEST_START; - unsigned long long temp64; - int num_patterns = sizeof (pattern) / sizeof (pattern[0]); - int i; - unsigned int hi, lo; - - for (i = 0; i < num_patterns; i++) { - move64 (&(pattern[i]), pmem); - move64 (pmem, &temp64); - - /* hi = (temp64>>32) & 0xffffffff; */ - /* lo = temp64 & 0xffffffff; */ - /* printf ("\ntemp64 = 0x%08x%08x", hi, lo); */ - - hi = (pattern[i] >> 32) & 0xffffffff; - lo = pattern[i] & 0xffffffff; - /* printf ("\npattern[%d] = 0x%08x%08x", i, hi, lo); */ - - if (temp64 != pattern[i]) { - printf ("\n Data Test Failed, pattern 0x%08x%08x", - hi, lo); - return 1; - } - } - - return 0; -} -#endif /* CFG_DRAM_TEST_DATA */ - -#if defined (CFG_DRAM_TEST_ADDRESS) -/*********************************************************************/ -/* NAME: mem_test_address() - test address lines */ -/* */ -/* DESCRIPTION: */ -/* This function performs a test to verify that each word im */ -/* memory is uniquly addressable. The test sequence is as follows: */ -/* */ -/* 1) write the address of each word to each word. */ -/* 2) verify that each location equals its address */ -/* */ -/* OUTPUTS: */ -/* Displays failing test pattern and address */ -/* */ -/* RETURNS: */ -/* 0 - Passed test */ -/* 1 - Failed test */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* */ -/* */ -/*********************************************************************/ -int mem_test_address (void) -{ - volatile unsigned int *pmem = - (volatile unsigned int *)CFG_MEMTEST_START; - const unsigned int size = (CFG_MEMTEST_END - CFG_MEMTEST_START) / 4; - unsigned int i; - - /* write address to each location */ - for (i = 0; i < size; i++) { - pmem[i] = i; - } - - /* verify each loaction */ - for (i = 0; i < size; i++) { - if (pmem[i] != i) { - printf ("\n Address Test Failed at 0x%x", i); - return 1; - } - } - return 0; -} -#endif /* CFG_DRAM_TEST_ADDRESS */ - -#if defined (CFG_DRAM_TEST_WALK) -/*********************************************************************/ -/* NAME: mem_march() - memory march */ -/* */ -/* DESCRIPTION: */ -/* Marches up through memory. At each location verifies rmask if */ -/* read = 1. At each location write wmask if write = 1. Displays */ -/* failing address and pattern. */ -/* */ -/* INPUTS: */ -/* volatile unsigned long long * base - start address of test */ -/* unsigned int size - number of dwords(64-bit) to test */ -/* unsigned long long rmask - read verify mask */ -/* unsigned long long wmask - wrtie verify mask */ -/* short read - verifies rmask if read = 1 */ -/* short write - writes wmask if write = 1 */ -/* */ -/* OUTPUTS: */ -/* Displays failing test pattern and address */ -/* */ -/* RETURNS: */ -/* 0 - Passed test */ -/* 1 - Failed test */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* */ -/* */ -/*********************************************************************/ -int mem_march (volatile unsigned long long *base, - unsigned int size, - unsigned long long rmask, - unsigned long long wmask, short read, short write) -{ - unsigned int i; - unsigned long long temp; - unsigned int hitemp, lotemp, himask, lomask; - - for (i = 0; i < size; i++) { - if (read != 0) { - /* temp = base[i]; */ - move64 ((unsigned long long *)&(base[i]), &temp); - if (rmask != temp) { - hitemp = (temp >> 32) & 0xffffffff; - lotemp = temp & 0xffffffff; - himask = (rmask >> 32) & 0xffffffff; - lomask = rmask & 0xffffffff; - - printf ("\n Walking one's test failed: \ - address = 0x%08x," "\n\texpected \ - 0x%08x%08x, found 0x%08x%08x", i << 3,\ - himask, lomask, hitemp, lotemp); - return 1; - } - } - if (write != 0) { - /* base[i] = wmask; */ - move64 (&wmask, (unsigned long long *)&(base[i])); - } - } - return 0; -} -#endif /* CFG_DRAM_TEST_WALK */ - -/*********************************************************************/ -/* NAME: mem_test_walk() - a simple walking ones test */ -/* */ -/* DESCRIPTION: */ -/* Performs a walking ones through entire physical memory. The */ -/* test uses as series of memory marches, mem_march(), to verify */ -/* and write the test patterns to memory. The test sequence is as */ -/* follows: */ -/* 1) march writing 0000...0001 */ -/* 2) march verifying 0000...0001 , writing 0000...0010 */ -/* 3) repeat step 2 shifting masks left 1 bit each time unitl */ -/* the write mask equals 1000...0000 */ -/* 4) march verifying 1000...0000 */ -/* The test fails if any of the memory marches return a failure. */ -/* */ -/* OUTPUTS: */ -/* Displays which pass on the memory test is executing */ -/* */ -/* RETURNS: */ -/* 0 - Passed test */ -/* 1 - Failed test */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* */ -/* */ -/*********************************************************************/ -int mem_test_walk (void) -{ - unsigned long long mask; - volatile unsigned long long *pmem = - (volatile unsigned long long *)CFG_MEMTEST_START; - const unsigned long size = (CFG_MEMTEST_END - CFG_MEMTEST_START) / 8; - - unsigned int i; - - mask = 0x01; - - printf ("Initial Pass"); - mem_march (pmem, size, 0x0, 0x1, 0, 1); - - printf ("\b\b\b\b\b\b\b\b\b\b\b\b"); - printf (" "); - printf (" "); - printf ("\b\b\b\b\b\b\b\b\b\b\b\b"); - - for (i = 0; i < 63; i++) { - printf ("Pass %2d", i + 2); - if (mem_march(pmem, size, mask, mask << 1, 1, 1) != 0) - /*printf ("mask: 0x%x, pass: %d, ", mask, i); */ - return 1; - mask = mask << 1; - printf ("\b\b\b\b\b\b\b"); - } - - printf ("Last Pass"); - if (mem_march(pmem, size, 0, mask, 0, 1) != 0) { - /* printf ("mask: 0x%x", mask); */ - return 1; - } - printf ("\b\b\b\b\b\b\b\b\b"); - printf (" "); - printf ("\b\b\b\b\b\b\b\b\b"); - - return 0; -} - -/*********************************************************************/ -/* NAME: testdram() - calls any enabled memory tests */ -/* */ -/* DESCRIPTION: */ -/* Runs memory tests if the environment test variables are set to */ -/* 'y'. */ -/* */ -/* INPUTS: */ -/* testdramdata - If set to 'y', data test is run. */ -/* testdramaddress - If set to 'y', address test is run. */ -/* testdramwalk - If set to 'y', walking ones test is run */ -/* */ -/* OUTPUTS: */ -/* None */ -/* */ -/* RETURNS: */ -/* 0 - Passed test */ -/* 1 - Failed test */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* */ -/* */ -/*********************************************************************/ -int testdram (void) -{ - char *s; - int rundata, runaddress, runwalk; - - s = getenv ("testdramdata"); - rundata = (s && (*s == 'y')) ? 1 : 0; - s = getenv ("testdramaddress"); - runaddress = (s && (*s == 'y')) ? 1 : 0; - s = getenv ("testdramwalk"); - runwalk = (s && (*s == 'y')) ? 1 : 0; - -/* rundata = 1; */ -/* runaddress = 0; */ -/* runwalk = 0; */ - - if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) - printf ("Testing RAM from 0x%08x to 0x%08x ... \ - (don't panic... that will take a moment !!!!)\n", \ - CFG_MEMTEST_START, CFG_MEMTEST_END); -#ifdef CFG_DRAM_TEST_DATA - if (rundata == 1) { - printf ("Test DATA ... "); - if (mem_test_data () == 1) { - printf ("failed \n"); - return 1; - } else - printf ("ok \n"); - } -#endif -#ifdef CFG_DRAM_TEST_ADDRESS - if (runaddress == 1) { - printf ("Test ADDRESS ... "); - if (mem_test_address () == 1) { - printf ("failed \n"); - return 1; - } else - printf ("ok \n"); - } -#endif -#ifdef CFG_DRAM_TEST_WALK - if (runwalk == 1) { - printf ("Test WALKING ONEs ... "); - if (mem_test_walk () == 1) { - printf ("failed \n"); - return 1; - } else - printf ("ok \n"); - } -#endif - if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) - printf ("passed\n"); - return 0; - -} -#endif /* CFG_DRAM_TEST */ - #if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) void ft_board_setup (void *blob, bd_t *bd) -- cgit From 9d27b3a0685ff99fc477983f315c04d49f657a8a Mon Sep 17 00:00:00 2001 From: roy zang Date: Mon, 4 Dec 2006 17:56:59 +0800 Subject: Slight code clean up. Add comments, delete duplicate define and remove spaces. Signed-off-by: Roy Zang --- board/mpc7448hpc2/tsi108_init.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'board/mpc7448hpc2') diff --git a/board/mpc7448hpc2/tsi108_init.c b/board/mpc7448hpc2/tsi108_init.c index fdb53653d1..e3b09cfad3 100644 --- a/board/mpc7448hpc2/tsi108_init.c +++ b/board/mpc7448hpc2/tsi108_init.c @@ -147,7 +147,7 @@ int board_early_init_f (void) gd->mem_clk = 0; i = in32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PWRUP_STATUS); - i = (i >> 20) & 0x07; /* value of SW4[4:7] */ + i = (i >> 20) & 0x07; /* Get GD PLL multiplier */ switch (i) { case 0: /* external clock */ printf ("Using external clock\n"); @@ -229,7 +229,7 @@ int board_early_init_r (void) __asm__ __volatile__ ("sync"); - /* Base addresses for Cs0, CS1, CS2, CS3 */ + /* Base addresses for CS0, CS1, CS2, CS3 */ out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_ADDR, 0x00000000); -- cgit From 647d3c3eed0da1d1505eecabe0b0fab96f956e68 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Sun, 4 Mar 2007 01:36:05 +0100 Subject: Some code cleanup. --- board/mpc7448hpc2/mpc7448hpc2.c | 2 +- board/mpc7448hpc2/tsi108_init.c | 24 ++++++++++++------------ 2 files changed, 13 insertions(+), 13 deletions(-) (limited to 'board/mpc7448hpc2') diff --git a/board/mpc7448hpc2/mpc7448hpc2.c b/board/mpc7448hpc2/mpc7448hpc2.c index d4a047c1d6..63c99de175 100644 --- a/board/mpc7448hpc2/mpc7448hpc2.c +++ b/board/mpc7448hpc2/mpc7448hpc2.c @@ -47,7 +47,7 @@ int display_mem_map (void); void after_reloc (ulong dest_addr) { DECLARE_GLOBAL_DATA_PTR; - + /* * Jump to the main U-Boot board init code */ diff --git a/board/mpc7448hpc2/tsi108_init.c b/board/mpc7448hpc2/tsi108_init.c index e3b09cfad3..8a7efef772 100644 --- a/board/mpc7448hpc2/tsi108_init.c +++ b/board/mpc7448hpc2/tsi108_init.c @@ -179,7 +179,7 @@ int board_early_init_r (void) ulong temp, i; ulong reg_val; volatile ulong *reg_ptr; - + reg_ptr = (ulong *) (CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + 0x900); @@ -300,7 +300,7 @@ int board_early_init_r (void) out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_CTRL1, 0x7C0F2000); __asm__ __volatile__ ("sync"); - + /* * Set new value for PB_OCN_BAR1: switch from BOOT to LUT mode. * value for PB_OCN_BAR1: (BA-0xE000_0000 + size 512MB + ENable) @@ -312,7 +312,7 @@ int board_early_init_r (void) /* Make sure that OCN_BAR2 decoder is set (to allow following * immediate read from SDRAM) */ - + temp = in32(CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR1); __asm__ __volatile__ ("sync"); @@ -327,11 +327,11 @@ int board_early_init_r (void) * and enable all HLP banks and not just HLP 0 as is being done for * Taiga Rev. 2. */ - + env_init (); #ifndef DISABLE_PBM - + /* * For IBM processors we have to set Address-Only commands generated * by PBM that are different from ones set after reset. @@ -475,10 +475,10 @@ int board_early_init_r (void) for (i = 0; i < 32; i++) { *reg_ptr++ = reg_val; /* P2O_BAR3_LUTx */ - + /* P2O_BAR3_LUT_UPPERx : Set data swapping mode for PBM (byte swapping) */ - *reg_ptr++ = 0; - + *reg_ptr++ = 0; + /* offset = 16MB, address translation is enabled to allow byte swapping */ reg_val += 0x01000000; } @@ -507,7 +507,7 @@ int board_early_init_r (void) #endif /* !DISABLE_PBM */ -#ifdef ENABLE_PCI_CSR_BAR +#ifdef ENABLE_PCI_CSR_BAR /* open if required access to Tsi108 CSRs from the PCI/X bus */ /* enable BAR0 on the PCI/X bus */ reg_val = in32(CFG_TSI108_CSR_BASE + @@ -528,7 +528,7 @@ int board_early_init_r (void) /* * Finally enable PCI/X Bus Master and Memory Space access */ - + reg_val = in32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_CSR); reg_val |= 0x06; out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_CSR, reg_val); @@ -555,7 +555,7 @@ int board_early_init_r (void) * Ensure that Machine Check exception is enabled * We need it to support PCI Bus probing (configuration reads) */ - + reg_val = mfmsr (); mtmsr(reg_val | MSR_ME); @@ -631,7 +631,7 @@ int misc_init_r (void) * thing done with regards to enabling diabling the cache. * So this seems like a good place to print all this information */ - + printf ("CACHE: "); switch (get_cpu_type()) { case CPU_7447A: -- cgit