From ed3294d6d1f977c24d6289f06b186809f6380030 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 7 Jul 2020 21:07:16 +0530 Subject: arm: Remove overo board OF_CONTROL, DM_SPI and other driver model migration deadlines are expired for this board. Drop it. Cc: Ash Charles Cc: Steve Sakoman Signed-off-by: Jagan Teki --- board/overo/spl.c | 61 ------------------------------------------------------- 1 file changed, 61 deletions(-) delete mode 100644 board/overo/spl.c (limited to 'board/overo/spl.c') diff --git a/board/overo/spl.c b/board/overo/spl.c deleted file mode 100644 index 91d8091d25..0000000000 --- a/board/overo/spl.c +++ /dev/null @@ -1,61 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Maintainer : Steve Sakoman - * - * Derived from Beagle Board, 3430 SDP, and OMAP3EVM code by - * Richard Woodruff - * Syed Mohammed Khasim - * Sunil Kumar - * Shashi Ranjan - * - * (C) Copyright 2004-2008 - * Texas Instruments, - */ - -#include -#include -#include -#include -#include "overo.h" - -/* - * Routine: get_board_mem_timings - * Description: If we use SPL then there is no x-loader nor config header - * so we have to setup the DDR timings ourself on both banks. - */ -void get_board_mem_timings(struct board_sdrc_timings *timings) -{ - timings->mr = MICRON_V_MR_165; - switch (get_board_revision()) { - case REVISION_0: /* Micron 1286MB/256MB, 1/2 banks of 128MB */ - timings->mcfg = MICRON_V_MCFG_165(256 << 20); - timings->ctrla = MICRON_V_ACTIMA_165; - timings->ctrlb = MICRON_V_ACTIMB_165; - timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; - break; - case REVISION_1: /* Micron 256MB/512MB, 1/2 banks of 256MB */ - case REVISION_4: - timings->mcfg = MICRON_V_MCFG_200(256 << 20); - timings->ctrla = MICRON_V_ACTIMA_200; - timings->ctrlb = MICRON_V_ACTIMB_200; - timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; - break; - case REVISION_2: /* Hynix 256MB/512MB, 1/2 banks of 256MB */ - timings->mcfg = HYNIX_V_MCFG_200(256 << 20); - timings->ctrla = HYNIX_V_ACTIMA_200; - timings->ctrlb = HYNIX_V_ACTIMB_200; - timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; - break; - case REVISION_3: /* Micron 512MB/1024MB, 1/2 banks of 512MB */ - timings->mcfg = MCFG(512 << 20, 15); - timings->ctrla = MICRON_V_ACTIMA_200; - timings->ctrlb = MICRON_V_ACTIMB_200; - timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; - break; - default: - timings->mcfg = MICRON_V_MCFG_165(128 << 20); - timings->ctrla = MICRON_V_ACTIMA_165; - timings->ctrlb = MICRON_V_ACTIMB_165; - timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; - } -} -- cgit