From e7b860fa4dd4de736d887deca19ca540abea4239 Mon Sep 17 00:00:00 2001 From: Sanchayan Maity Date: Wed, 15 Apr 2015 16:24:26 +0530 Subject: ARM: vf610: Initial integration for Colibri VF50/VF61 This adds initial support for Colibri VF50/VF61 based on Freescale Vybrid SoC. - CPU clocked at 396/500 MHz - DDR3 at 396MHz - for VF50, use PLL2 as memory clock (synchronous mode) - for VF61, use PLL1 as memory clock (asynchronous mode) - Console on UART0 (Colibri UART_A) - Ethernet on FEC1 - PLL5 based RMII clocking (E.g. No external crystal) - UART_A and UART_C I/O muxing - Boot from NAND by default Tested on Colibri VF50/VF61 booting using serial loader over UART. Signed-off-by: Sanchayan Maity Acked-by: Stefan Agner --- board/toradex/colibri_vf/Makefile | 7 +++++++ 1 file changed, 7 insertions(+) create mode 100644 board/toradex/colibri_vf/Makefile (limited to 'board/toradex/colibri_vf/Makefile') diff --git a/board/toradex/colibri_vf/Makefile b/board/toradex/colibri_vf/Makefile new file mode 100644 index 0000000000..c7e5134ba1 --- /dev/null +++ b/board/toradex/colibri_vf/Makefile @@ -0,0 +1,7 @@ +# +# Copyright 2013 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := colibri_vf.o -- cgit