From d8d33b6d4dd2ecd2ea2a3d3ece9e22528d8fd15c Mon Sep 17 00:00:00 2001 From: Parthiban Nallathambi Date: Thu, 18 Apr 2019 00:04:09 +0200 Subject: imx: Add variscite DART-6UL Evaluation Kit Port for the DART-6UL Evaluation Kit SBC. Based on the variscite DART-6UL iMX6ULL SoM. CPU: Freescale i.MX6ULL rev1.1 900 MHz (running at 396 MHz) CPU: Commercial temperature grade (0C to 95C) at 43C Reset cause: POR Model: Variscite DART-6UL Evaluation Kit Board: Variscite DART-6UL Evaluation Kit DRAM: 512 MiB MMC: FSL_SDHC: 0, FSL_SDHC: 1 In: serial@02020000 Out: serial@02020000 Err: serial@02020000 Net: FEC0 Working: - Eth0 - i2c - MMC/SD - eMMC - USB host - UART 1 Note: LCDIF porting needs DM_VIDEO https://lists.denx.de/pipermail/u-boot/2019-April/365506.html Signed-off-by: Parthiban Nallathambi --- board/variscite/dart_6ul/MAINTAINERS | 8 ++++++++ 1 file changed, 8 insertions(+) create mode 100644 board/variscite/dart_6ul/MAINTAINERS (limited to 'board/variscite/dart_6ul/MAINTAINERS') diff --git a/board/variscite/dart_6ul/MAINTAINERS b/board/variscite/dart_6ul/MAINTAINERS new file mode 100644 index 0000000000..339f93fa66 --- /dev/null +++ b/board/variscite/dart_6ul/MAINTAINERS @@ -0,0 +1,8 @@ +MX6UL_DART BOARD +M: Parthiban Nallathambi +S: Maintained +F: arch/arm/dts/imx6ull-dart-6ul.dts +F: arch/arm/dts/imx6ull-dart-6ul.dtsi +F: board/variscite/dart_6ul/ +F: configs/variscite_dart6ul_defconfig +F: include/configs/dart_6ul.h -- cgit