From 6a994e5bb6ba0193d655e2cd67ff8d93bfe66d82 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Thu, 6 Nov 2014 15:39:28 +0900 Subject: arm: rmobile: Add support gose board The gose board has R8A7793, 1GB DDR3-SDRAM, USB, Ethernet, and more. This patch supports the following functions: - DDR3-SDRAM - SCIF - QSPI - SPI Signed-off-by: Hisashi Nakamura Signed-off-by: Nobuhiro Iwamatsu CC: Masahiro Yamada Signed-off-by: Nobuhiro Iwamatsu --- board/renesas/gose/Kconfig | 12 + board/renesas/gose/MAINTAINERS | 6 + board/renesas/gose/Makefile | 9 + board/renesas/gose/gose.c | 116 ++++ board/renesas/gose/qos.c | 1155 ++++++++++++++++++++++++++++++++++++++++ board/renesas/gose/qos.h | 12 + 6 files changed, 1310 insertions(+) create mode 100644 board/renesas/gose/Kconfig create mode 100644 board/renesas/gose/MAINTAINERS create mode 100644 board/renesas/gose/Makefile create mode 100644 board/renesas/gose/gose.c create mode 100644 board/renesas/gose/qos.c create mode 100644 board/renesas/gose/qos.h (limited to 'board') diff --git a/board/renesas/gose/Kconfig b/board/renesas/gose/Kconfig new file mode 100644 index 0000000000..930a44559e --- /dev/null +++ b/board/renesas/gose/Kconfig @@ -0,0 +1,12 @@ +if TARGET_GOSE + +config SYS_BOARD + default "gose" + +config SYS_VENDOR + default "renesas" + +config SYS_CONFIG_NAME + default "gose" + +endif diff --git a/board/renesas/gose/MAINTAINERS b/board/renesas/gose/MAINTAINERS new file mode 100644 index 0000000000..cad5be99b1 --- /dev/null +++ b/board/renesas/gose/MAINTAINERS @@ -0,0 +1,6 @@ +ALT BOARD +M: Nobuhiro Iwamatsu +S: Maintained +F: board/renesas/gose/ +F: include/configs/gose.h +F: configs/gose_defconfig diff --git a/board/renesas/gose/Makefile b/board/renesas/gose/Makefile new file mode 100644 index 0000000000..a4fb6cc43d --- /dev/null +++ b/board/renesas/gose/Makefile @@ -0,0 +1,9 @@ +# +# board/renesas/alt/Makefile +# +# Copyright (C) 2014 Renesas Electronics Corporation +# +# SPDX-License-Identifier: GPL-2.0 +# + +obj-y := gose.o qos.o diff --git a/board/renesas/gose/gose.c b/board/renesas/gose/gose.c new file mode 100644 index 0000000000..09905afc72 --- /dev/null +++ b/board/renesas/gose/gose.c @@ -0,0 +1,116 @@ +/* + * board/renesas/gose/gose.c + * + * Copyright (C) 2014 Renesas Electronics Corporation + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "qos.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define CLK2MHZ(clk) (clk / 1000 / 1000) +void s_init(void) +{ + struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE; + struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE; + u32 stc; + + /* Watchdog init */ + writel(0xA5A5A500, &rwdt->rwtcsra); + writel(0xA5A5A500, &swdt->swtcsra); + + /* CPU frequency setting. Set to 1.5GHz */ + stc = ((1500 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_BIT; + clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc); + + /* QoS */ + qos_init(); +} + +#define MSTPSR1 0xE6150038 +#define SMSTPCR1 0xE6150134 +#define TMU0_MSTP125 (1 << 25) + +#define MSTPSR7 0xE61501C4 +#define SMSTPCR7 0xE615014C +#define SCIF0_MSTP721 (1 << 21) + +#define mstp_setbits(type, addr, saddr, set) \ + out_##type((saddr), in_##type(addr) | (set)) +#define mstp_clrbits(type, addr, saddr, clear) \ + out_##type((saddr), in_##type(addr) & ~(clear)) +#define mstp_setbits_le32(addr, saddr, set) \ + mstp_setbits(le32, addr, saddr, set) +#define mstp_clrbits_le32(addr, saddr, clear) \ + mstp_clrbits(le32, addr, saddr, clear) + +int board_early_init_f(void) +{ + /* TMU0 */ + mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); + + /* SCIF0 */ + mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721); + + return 0; +} + +#define TSTR0 0x04 +#define TSTR0_STR0 0x01 +void arch_preboot_os(void) +{ + /* stop TMU0 */ + mstp_clrbits_le32(TMU_BASE + TSTR0, TMU_BASE + TSTR0, TSTR0_STR0); + /* Disable TMU0 */ + mstp_setbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); +} + +int board_init(void) +{ + /* adress of boot parameters */ + gd->bd->bi_boot_params = GOSE_SDRAM_BASE + 0x100; + + /* Init PFC controller */ + r8a7793_pinmux_init(); + + return 0; +} + +int dram_init(void) +{ + gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + + return 0; +} + +const struct rmobile_sysinfo sysinfo = { + CONFIG_RMOBILE_BOARD_STRING +}; + +void dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = GOSE_SDRAM_BASE; + gd->bd->bi_dram[0].size = GOSE_SDRAM_SIZE; +} + +void reset_cpu(ulong addr) +{ + u8 val; + + i2c_set_bus_num(2); /* PowerIC connected to ch2 */ + i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); + val |= 0x02; + i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); +} diff --git a/board/renesas/gose/qos.c b/board/renesas/gose/qos.c new file mode 100644 index 0000000000..64e52cf3a4 --- /dev/null +++ b/board/renesas/gose/qos.c @@ -0,0 +1,1155 @@ +/* + * board/renesas/gose/qos.c + * This file is gose QoS setting. + * + * Copyright (C) 2014 Renesas Electronics Corporation + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include +#include +#include + +#if defined(CONFIG_RMOBILE_EXTRAM_BOOT) +/* QoS version 0.20 */ +enum { + DBSC3_00, DBSC3_01, DBSC3_02, DBSC3_03, DBSC3_04, + DBSC3_05, DBSC3_06, DBSC3_07, DBSC3_08, DBSC3_09, + DBSC3_10, DBSC3_11, DBSC3_12, DBSC3_13, DBSC3_14, + DBSC3_15, + DBSC3_NR, +}; + +static u32 dbsc3_0_r_qos_addr[DBSC3_NR] = { + [DBSC3_00] = DBSC3_0_QOS_R0_BASE, + [DBSC3_01] = DBSC3_0_QOS_R1_BASE, + [DBSC3_02] = DBSC3_0_QOS_R2_BASE, + [DBSC3_03] = DBSC3_0_QOS_R3_BASE, + [DBSC3_04] = DBSC3_0_QOS_R4_BASE, + [DBSC3_05] = DBSC3_0_QOS_R5_BASE, + [DBSC3_06] = DBSC3_0_QOS_R6_BASE, + [DBSC3_07] = DBSC3_0_QOS_R7_BASE, + [DBSC3_08] = DBSC3_0_QOS_R8_BASE, + [DBSC3_09] = DBSC3_0_QOS_R9_BASE, + [DBSC3_10] = DBSC3_0_QOS_R10_BASE, + [DBSC3_11] = DBSC3_0_QOS_R11_BASE, + [DBSC3_12] = DBSC3_0_QOS_R12_BASE, + [DBSC3_13] = DBSC3_0_QOS_R13_BASE, + [DBSC3_14] = DBSC3_0_QOS_R14_BASE, + [DBSC3_15] = DBSC3_0_QOS_R15_BASE, +}; + +static u32 dbsc3_0_w_qos_addr[DBSC3_NR] = { + [DBSC3_00] = DBSC3_0_QOS_W0_BASE, + [DBSC3_01] = DBSC3_0_QOS_W1_BASE, + [DBSC3_02] = DBSC3_0_QOS_W2_BASE, + [DBSC3_03] = DBSC3_0_QOS_W3_BASE, + [DBSC3_04] = DBSC3_0_QOS_W4_BASE, + [DBSC3_05] = DBSC3_0_QOS_W5_BASE, + [DBSC3_06] = DBSC3_0_QOS_W6_BASE, + [DBSC3_07] = DBSC3_0_QOS_W7_BASE, + [DBSC3_08] = DBSC3_0_QOS_W8_BASE, + [DBSC3_09] = DBSC3_0_QOS_W9_BASE, + [DBSC3_10] = DBSC3_0_QOS_W10_BASE, + [DBSC3_11] = DBSC3_0_QOS_W11_BASE, + [DBSC3_12] = DBSC3_0_QOS_W12_BASE, + [DBSC3_13] = DBSC3_0_QOS_W13_BASE, + [DBSC3_14] = DBSC3_0_QOS_W14_BASE, + [DBSC3_15] = DBSC3_0_QOS_W15_BASE, +}; + +void qos_init(void) +{ + int i; + struct rcar_s3c *s3c; + struct rcar_s3c_qos *s3c_qos; + struct rcar_dbsc3_qos *qos_addr; + struct rcar_mxi *mxi; + struct rcar_mxi_qos *mxi_qos; + struct rcar_axi_qos *axi_qos; + + /* DBSC DBADJ2 */ + writel(0x20042004, DBSC3_0_DBADJ2); + + /* S3C -QoS */ + s3c = (struct rcar_s3c *)S3C_BASE; + writel(0x00000000, &s3c->s3cadsplcr); + writel(0x1F0B0908, &s3c->s3crorr); + writel(0x1F0C0A08, &s3c->s3cworr); + + /* QoS Control Registers */ + s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI0_BASE; + writel(0x00890089, &s3c_qos->s3cqos0); + writel(0x20960010, &s3c_qos->s3cqos1); + writel(0x20302030, &s3c_qos->s3cqos2); + writel(0x20AA2200, &s3c_qos->s3cqos3); + writel(0x00002032, &s3c_qos->s3cqos4); + writel(0x20960010, &s3c_qos->s3cqos5); + writel(0x20302030, &s3c_qos->s3cqos6); + writel(0x20AA2200, &s3c_qos->s3cqos7); + writel(0x00002032, &s3c_qos->s3cqos8); + + s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI1_BASE; + writel(0x00890089, &s3c_qos->s3cqos0); + writel(0x20960010, &s3c_qos->s3cqos1); + writel(0x20302030, &s3c_qos->s3cqos2); + writel(0x20AA2200, &s3c_qos->s3cqos3); + writel(0x00002032, &s3c_qos->s3cqos4); + writel(0x20960010, &s3c_qos->s3cqos5); + writel(0x20302030, &s3c_qos->s3cqos6); + writel(0x20AA2200, &s3c_qos->s3cqos7); + writel(0x00002032, &s3c_qos->s3cqos8); + + s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_MXI_BASE; + writel(0x00820082, &s3c_qos->s3cqos0); + writel(0x20960020, &s3c_qos->s3cqos1); + writel(0x20302030, &s3c_qos->s3cqos2); + writel(0x20AA20DC, &s3c_qos->s3cqos3); + writel(0x00002032, &s3c_qos->s3cqos4); + writel(0x20960020, &s3c_qos->s3cqos5); + writel(0x20302030, &s3c_qos->s3cqos6); + writel(0x20AA20DC, &s3c_qos->s3cqos7); + writel(0x00002032, &s3c_qos->s3cqos8); + + s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_AXI_BASE; + writel(0x00820082, &s3c_qos->s3cqos0); + writel(0x20960020, &s3c_qos->s3cqos1); + writel(0x20302030, &s3c_qos->s3cqos2); + writel(0x20AA20FA, &s3c_qos->s3cqos3); + writel(0x00002032, &s3c_qos->s3cqos4); + writel(0x20960020, &s3c_qos->s3cqos5); + writel(0x20302030, &s3c_qos->s3cqos6); + writel(0x20AA20FA, &s3c_qos->s3cqos7); + writel(0x00002032, &s3c_qos->s3cqos8); + + /* DBSC -QoS */ + /* DBSC0 - Read */ + for (i = DBSC3_00; i < DBSC3_NR; i++) { + qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_r_qos_addr[i]; + writel(0x00000002, &qos_addr->dblgcnt); + writel(0x00002096, &qos_addr->dbtmval0); + writel(0x00002064, &qos_addr->dbtmval1); + writel(0x00002032, &qos_addr->dbtmval2); + writel(0x00001FB0, &qos_addr->dbtmval3); + writel(0x00000001, &qos_addr->dbrqctr); + writel(0x00002078, &qos_addr->dbthres0); + writel(0x0000204B, &qos_addr->dbthres1); + writel(0x0000201E, &qos_addr->dbthres2); + writel(0x00000001, &qos_addr->dblgqon); + } + + /* DBSC0 - Write */ + for (i = DBSC3_00; i < DBSC3_NR; i++) { + qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_w_qos_addr[i]; + writel(0x00000002, &qos_addr->dblgcnt); + writel(0x00002096, &qos_addr->dbtmval0); + writel(0x00002064, &qos_addr->dbtmval1); + writel(0x00002050, &qos_addr->dbtmval2); + writel(0x0000203A, &qos_addr->dbtmval3); + writel(0x00000001, &qos_addr->dbrqctr); + writel(0x00002078, &qos_addr->dbthres0); + writel(0x0000204B, &qos_addr->dbthres1); + writel(0x0000203C, &qos_addr->dbthres2); + writel(0x00000001, &qos_addr->dblgqon); + } + + /* CCI-400 -QoS */ + writel(0x20001000, CCI_400_MAXOT_1); + writel(0x20001000, CCI_400_MAXOT_2); + writel(0x0000000C, CCI_400_QOSCNTL_1); + writel(0x0000000C, CCI_400_QOSCNTL_2); + + /* MXI -QoS */ + /* Transaction Control (MXI) */ + mxi = (struct rcar_mxi *)MXI_BASE; + writel(0x00000013, &mxi->mxrtcr); + writel(0x00000013, &mxi->mxwtcr); + writel(0x00200000, &mxi->mxs3cracr); + writel(0x00200000, &mxi->mxs3cwacr); + writel(0x00200000, &mxi->mxaxiracr); + writel(0x00200000, &mxi->mxaxiwacr); + + /* QoS Control (MXI) */ + mxi_qos = (struct rcar_mxi_qos *)MXI_QOS_BASE; + writel(0x0000000C, &mxi_qos->vspdu0); + writel(0x0000000C, &mxi_qos->vspdu1); + writel(0x0000000E, &mxi_qos->du0); + + /* AXI -QoS */ + /* Transaction Control (MXI) */ + axi_qos = (struct rcar_axi_qos *)SYS_AXI_SYX64TO128_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_AVB_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x000020A6, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_G2D_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x000020A6, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMP0_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002021, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMP1_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002037, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX0_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX1_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX2_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_LBS_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x0000214C, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUDS_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUM_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS0_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS1_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MTSB0_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002021, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MTSB1_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002021, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_PCI_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x0000214C, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_RTX_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS0_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x000020A6, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS1_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x000020A6, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB20_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB21_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB22_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB30_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x0000214C, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_AX2M_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_CC50_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002029, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_CCI_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_CS_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_DDM_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x000020A6, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_ETH_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MPXM_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_SAT0_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_SAT1_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM0_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x0000214C, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM1_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x0000214C, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_TRAB_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x000020A6, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_UDM0_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_UDM1_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + /* QoS Register (RT-AXI) */ + axi_qos = (struct rcar_axi_qos *)RT_AXI_SHX_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)RT_AXI_DBG_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)RT_AXI_RDM_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002299, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)RT_AXI_RDS_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002029, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)RT_AXI_RTX64TO128_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)RT_AXI_STPRO_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002029, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)RT_AXI_SY2RT_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + /* QoS Register (MP-AXI) */ + axi_qos = (struct rcar_axi_qos *)MP_AXI_ADSP_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002037, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS0_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002014, &axi_qos->qosctset0); + writel(0x00000040, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS1_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002014, &axi_qos->qosctset0); + writel(0x00000040, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MP_AXI_MLP_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00001FF0, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00002001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MP_AXI_MMUMP_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MP_AXI_SPU_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MP_AXI_SPUC_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x0000206E, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + /* QoS Register (SYS-AXI256) */ + axi_qos = (struct rcar_axi_qos *)SYS_AXI256_AXI128TO256_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x000020EB, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI256_SYX_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x000020EB, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MPX_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x000020EB, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MXI_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x000020EB, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + /* QoS Register (CCI-AXI) */ + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS0_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)CCI_AXI_SYX2_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUDS_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUM_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MXI_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS1_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUMP_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + /* QoS Register (Media-AXI) */ + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXR_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x000020DC, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x000020AA, &axi_qos->qosthres0); + writel(0x00002032, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXW_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x000020DC, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x000020AA, &axi_qos->qosthres0); + writel(0x00002032, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_JPR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_JPW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU1CR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU1CW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VIN0W_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00001FF0, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00002001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0R_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0W_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1R_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1W_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP1R_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP1W_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0R_BASE; + writel(0x00000003, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0W_BASE; + writel(0x00000003, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD1R_BASE; + writel(0x00000003, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD1W_BASE; + writel(0x00000003, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0R_BASE; + writel(0x00000003, &axi_qos->qosconf); + writel(0x00002063, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0W_BASE; + writel(0x00000003, &axi_qos->qosconf); + writel(0x00002063, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002073, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002073, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002073, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002073, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VPC0R_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002073, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); +} +#else /* CONFIG_RMOBILE_EXTRAM_BOOT */ +void qos_init(void) +{ +} +#endif /* CONFIG_RMOBILE_EXTRAM_BOOT */ diff --git a/board/renesas/gose/qos.h b/board/renesas/gose/qos.h new file mode 100644 index 0000000000..ffd404797d --- /dev/null +++ b/board/renesas/gose/qos.h @@ -0,0 +1,12 @@ +/* + * Copyright (C) 2014 Renesas Electronics Corporation + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef __QOS_H__ +#define __QOS_H__ + +void qos_init(void); + +#endif -- cgit From f0261243102fbc020a01178a46a52e00fc55e3d2 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Thu, 6 Nov 2014 15:42:24 +0900 Subject: arm: rmobile: gose: Add Ethernet support Gose board has one ether port, this works using sh-ether driver. This adds GPIO settings and driver settings in order to use the sh-ether. Signed-off-by: Nobuhiro Iwamatsu Signed-off-by: Nobuhiro Iwamatsu --- board/renesas/gose/gose.c | 62 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 62 insertions(+) (limited to 'board') diff --git a/board/renesas/gose/gose.c b/board/renesas/gose/gose.c index 09905afc72..2cef7019dc 100644 --- a/board/renesas/gose/gose.c +++ b/board/renesas/gose/gose.c @@ -15,6 +15,8 @@ #include #include #include +#include +#include #include #include "qos.h" @@ -47,6 +49,10 @@ void s_init(void) #define SMSTPCR7 0xE615014C #define SCIF0_MSTP721 (1 << 21) +#define MSTPSR8 0xE61509A0 +#define SMSTPCR8 0xE6150990 +#define ETHER_MSTP813 (1 << 13) + #define mstp_setbits(type, addr, saddr, set) \ out_##type((saddr), in_##type(addr) | (set)) #define mstp_clrbits(type, addr, saddr, clear) \ @@ -64,6 +70,9 @@ int board_early_init_f(void) /* SCIF0 */ mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721); + /* ETHER */ + mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813); + return 0; } @@ -77,6 +86,10 @@ void arch_preboot_os(void) mstp_setbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); } +#define PUPR5 0xE6060114 +#define PUPR5_ETH 0x3FFC0000 +#define PUPR5_ETH_MAGIC (1 << 27) + int board_init(void) { /* adress of boot parameters */ @@ -85,9 +98,58 @@ int board_init(void) /* Init PFC controller */ r8a7793_pinmux_init(); + /* ETHER Enable */ + gpio_request(GPIO_FN_ETH_CRS_DV, NULL); + gpio_request(GPIO_FN_ETH_RX_ER, NULL); + gpio_request(GPIO_FN_ETH_RXD0, NULL); + gpio_request(GPIO_FN_ETH_RXD1, NULL); + gpio_request(GPIO_FN_ETH_LINK, NULL); + gpio_request(GPIO_FN_ETH_REFCLK, NULL); + gpio_request(GPIO_FN_ETH_MDIO, NULL); + gpio_request(GPIO_FN_ETH_TXD1, NULL); + gpio_request(GPIO_FN_ETH_TX_EN, NULL); + gpio_request(GPIO_FN_ETH_TXD0, NULL); + gpio_request(GPIO_FN_ETH_MDC, NULL); + gpio_request(GPIO_FN_IRQ0, NULL); + + mstp_clrbits_le32(PUPR5, PUPR5, PUPR5_ETH & ~PUPR5_ETH_MAGIC); + gpio_request(GPIO_GP_5_22, NULL); /* PHY_RST */ + mstp_clrbits_le32(PUPR5, PUPR5, PUPR5_ETH_MAGIC); + + gpio_direction_output(GPIO_GP_5_22, 0); + mdelay(20); + gpio_set_value(GPIO_GP_5_22, 1); + udelay(1); + return 0; } +#define CXR24 0xEE7003C0 /* MAC address high register */ +#define CXR25 0xEE7003C8 /* MAC address low register */ + +int board_eth_init(bd_t *bis) +{ + int ret = -ENODEV; + u32 val; + unsigned char enetaddr[6]; + +#ifdef CONFIG_SH_ETHER + ret = sh_eth_initialize(bis); + if (!eth_getenv_enetaddr("ethaddr", enetaddr)) + return ret; + + /* Set Mac address */ + val = enetaddr[0] << 24 | enetaddr[1] << 16 | + enetaddr[2] << 8 | enetaddr[3]; + writel(val, CXR24); + + val = enetaddr[4] << 8 | enetaddr[5]; + writel(val, CXR25); +#endif + + return ret; +} + int dram_init(void) { gd->ram_size = CONFIG_SYS_SDRAM_SIZE; -- cgit From 0c4a1b0fffcb0739e5444ff0689b7c38b385d193 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Thu, 6 Nov 2014 15:43:34 +0900 Subject: arm: rmobile: koelsch: Remove board_late_init function Koelsch board does not use board_late_init function. This removes this function and define of BOARD_LATE_INIT from config. Signed-off-by: Nobuhiro Iwamatsu Signed-off-by: Nobuhiro Iwamatsu --- board/renesas/koelsch/koelsch.c | 5 ----- 1 file changed, 5 deletions(-) (limited to 'board') diff --git a/board/renesas/koelsch/koelsch.c b/board/renesas/koelsch/koelsch.c index 37202f9815..908bc607a2 100644 --- a/board/renesas/koelsch/koelsch.c +++ b/board/renesas/koelsch/koelsch.c @@ -179,11 +179,6 @@ void dram_init_banksize(void) gd->bd->bi_dram[0].size = KOELSCH_SDRAM_SIZE; } -int board_late_init(void) -{ - return 0; -} - void reset_cpu(ulong addr) { u8 val; -- cgit From 8d174996c7a23361c18f884aa759c35201e2c3eb Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Thu, 6 Nov 2014 15:43:35 +0900 Subject: arm: rmobile: lager: Remove board_late_init function Lager board does not use board_late_init function. This removes this function and define of BOARD_LATE_INIT from config. Signed-off-by: Nobuhiro Iwamatsu Signed-off-by: Nobuhiro Iwamatsu --- board/renesas/lager/lager.c | 5 ----- 1 file changed, 5 deletions(-) (limited to 'board') diff --git a/board/renesas/lager/lager.c b/board/renesas/lager/lager.c index 2bb87108f6..99a298a98b 100644 --- a/board/renesas/lager/lager.c +++ b/board/renesas/lager/lager.c @@ -180,11 +180,6 @@ void dram_init_banksize(void) gd->bd->bi_dram[0].size = LAGER_SDRAM_SIZE; } -int board_late_init(void) -{ - return 0; -} - void reset_cpu(ulong addr) { u8 val; -- cgit From 9502d03674e220d3f9efbb4420abe8d167460ba6 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Thu, 6 Nov 2014 15:43:36 +0900 Subject: arm: rmobile: alt: Remove board_late_init function Alt board does not use board_late_init function. This removes this function and define of BOARD_LATE_INIT from config. Signed-off-by: Nobuhiro Iwamatsu Signed-off-by: Nobuhiro Iwamatsu --- board/renesas/alt/alt.c | 5 ----- 1 file changed, 5 deletions(-) (limited to 'board') diff --git a/board/renesas/alt/alt.c b/board/renesas/alt/alt.c index 5c5a86f145..cf6d64c49a 100644 --- a/board/renesas/alt/alt.c +++ b/board/renesas/alt/alt.c @@ -155,11 +155,6 @@ void dram_init_banksize(void) gd->bd->bi_dram[0].size = ALT_SDRAM_SIZE; } -int board_late_init(void) -{ - return 0; -} - void reset_cpu(ulong addr) { u8 val; -- cgit From 92ef38ee0989a5d85bac48e58c9f99e2618d2072 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Mon, 10 Nov 2014 09:16:43 +0900 Subject: arm: rmobile: alt: Enable channel 1 of sh-i2c Alt board was connected Power IC to channel 1 of sh-i2c. Source code that controls this is already included, but channel 1 of sh-i2c is not enabled. This enables channel 1 of sh-i2c, and can use. Signed-off-by: Nobuhiro Iwamatsu Signed-off-by: Nobuhiro Iwamatsu --- board/renesas/alt/alt.c | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'board') diff --git a/board/renesas/alt/alt.c b/board/renesas/alt/alt.c index cf6d64c49a..083e007fcf 100644 --- a/board/renesas/alt/alt.c +++ b/board/renesas/alt/alt.c @@ -49,6 +49,10 @@ void s_init(void) #define SMSTPCR8 0xE6150990 #define ETHER_MSTP813 (1 << 13) +#define MSTPSR3 0xE6150048 +#define SMSTPCR3 0xE615013C +#define IIC1_MSTP323 (1 << 23) + #define mstp_setbits(type, addr, saddr, set) \ out_##type((saddr), in_##type(addr) | (set)) #define mstp_clrbits(type, addr, saddr, clear) \ @@ -69,6 +73,9 @@ int board_early_init_f(void) /* ETHER */ mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813); + /* IIC1 / sh-i2c ch1 */ + mstp_clrbits_le32(MSTPSR3, SMSTPCR3, IIC1_MSTP323); + return 0; } -- cgit From f063b32cf5ee45add4be6e3f3e393917489cb35a Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Mon, 10 Nov 2014 09:16:44 +0900 Subject: arm: rmobile: alt: Fix typo in comment for sh-i2c PowerIC connected to channel 1 of sh-i2c, not channel 2. Signed-off-by: Nobuhiro Iwamatsu Signed-off-by: Nobuhiro Iwamatsu --- board/renesas/alt/alt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'board') diff --git a/board/renesas/alt/alt.c b/board/renesas/alt/alt.c index 083e007fcf..68ae9372c7 100644 --- a/board/renesas/alt/alt.c +++ b/board/renesas/alt/alt.c @@ -166,7 +166,7 @@ void reset_cpu(ulong addr) { u8 val; - i2c_set_bus_num(1); /* PowerIC connected to ch3 */ + i2c_set_bus_num(1); /* PowerIC connected to ch1 */ i2c_init(400000, 0); i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); val |= 0x02; -- cgit From 46049bec07ab7b3ec5fef4d1e5247d83abd99c29 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Mon, 10 Nov 2014 09:16:45 +0900 Subject: arm: rmobile: alt: Remove i2c_init function The i2c_init function is no longer necessary. Signed-off-by: Nobuhiro Iwamatsu Signed-off-by: Nobuhiro Iwamatsu --- board/renesas/alt/alt.c | 1 - 1 file changed, 1 deletion(-) (limited to 'board') diff --git a/board/renesas/alt/alt.c b/board/renesas/alt/alt.c index 68ae9372c7..039cb376d3 100644 --- a/board/renesas/alt/alt.c +++ b/board/renesas/alt/alt.c @@ -167,7 +167,6 @@ void reset_cpu(ulong addr) u8 val; i2c_set_bus_num(1); /* PowerIC connected to ch1 */ - i2c_init(400000, 0); i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); val |= 0x02; i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); -- cgit From 4772684c70159c70a742811c14adc1f75b1b5aa1 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Mon, 10 Nov 2014 13:58:50 +0900 Subject: arm: rmobile: alt: Remove dram_init_banksize function Alt board is defined CONFIG_SYS_SDRAM_BASE, and this can use a basic function of dram_init_banksize instead. Signed-off-by: Nobuhiro Iwamatsu Signed-off-by: Nobuhiro Iwamatsu --- board/renesas/alt/alt.c | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) (limited to 'board') diff --git a/board/renesas/alt/alt.c b/board/renesas/alt/alt.c index 039cb376d3..523c5f131f 100644 --- a/board/renesas/alt/alt.c +++ b/board/renesas/alt/alt.c @@ -88,7 +88,7 @@ void arch_preboot_os(void) int board_init(void) { /* adress of boot parameters */ - gd->bd->bi_boot_params = ALT_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; /* Init PFC controller */ r8a7794_pinmux_init(); @@ -156,12 +156,6 @@ const struct rmobile_sysinfo sysinfo = { CONFIG_RMOBILE_BOARD_STRING }; -void dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = ALT_SDRAM_BASE; - gd->bd->bi_dram[0].size = ALT_SDRAM_SIZE; -} - void reset_cpu(ulong addr) { u8 val; -- cgit From 956556fb0e83a336ced39753bac19873fcb46075 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Mon, 10 Nov 2014 13:58:50 +0900 Subject: arm: rmobile: koelsch: Remove dram_init_banksize function Koesch board is defined CONFIG_SYS_SDRAM_BASE, and this can use a basic function of dram_init_banksize instead. Signed-off-by: Nobuhiro Iwamatsu Signed-off-by: Nobuhiro Iwamatsu --- board/renesas/koelsch/koelsch.c | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) (limited to 'board') diff --git a/board/renesas/koelsch/koelsch.c b/board/renesas/koelsch/koelsch.c index 908bc607a2..244bc58633 100644 --- a/board/renesas/koelsch/koelsch.c +++ b/board/renesas/koelsch/koelsch.c @@ -90,7 +90,7 @@ void arch_preboot_os(void) int board_init(void) { /* adress of boot parameters */ - gd->bd->bi_boot_params = KOELSCH_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; /* Init PFC controller */ r8a7791_pinmux_init(); @@ -173,12 +173,6 @@ const struct rmobile_sysinfo sysinfo = { CONFIG_RMOBILE_BOARD_STRING }; -void dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = KOELSCH_SDRAM_BASE; - gd->bd->bi_dram[0].size = KOELSCH_SDRAM_SIZE; -} - void reset_cpu(ulong addr) { u8 val; -- cgit From eeb266ab6c2724f82e59297d53d7ae12fc6c0236 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Mon, 10 Nov 2014 13:58:50 +0900 Subject: arm: rmobile: lager: Remove dram_init_banksize function Lager board is defined CONFIG_SYS_SDRAM_BASE, and this can use a basic function of dram_init_banksize instead. Signed-off-by: Nobuhiro Iwamatsu Signed-off-by: Nobuhiro Iwamatsu --- board/renesas/lager/lager.c | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) (limited to 'board') diff --git a/board/renesas/lager/lager.c b/board/renesas/lager/lager.c index 99a298a98b..93273b202f 100644 --- a/board/renesas/lager/lager.c +++ b/board/renesas/lager/lager.c @@ -93,7 +93,7 @@ DECLARE_GLOBAL_DATA_PTR; int board_init(void) { /* adress of boot parameters */ - gd->bd->bi_boot_params = LAGER_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; /* Init PFC controller */ r8a7790_pinmux_init(); @@ -174,12 +174,6 @@ const struct rmobile_sysinfo sysinfo = { CONFIG_RMOBILE_BOARD_STRING }; -void dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = LAGER_SDRAM_BASE; - gd->bd->bi_dram[0].size = LAGER_SDRAM_SIZE; -} - void reset_cpu(ulong addr) { u8 val; -- cgit From 5a290250f72a2eb2855ea70e9114ba63388b288a Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Mon, 10 Nov 2014 13:58:50 +0900 Subject: arm: rmobile: gose: Remove dram_init_banksize function Gose board is defined CONFIG_SYS_SDRAM_BASE, and this can use a basic function of dram_init_banksize instead. Signed-off-by: Nobuhiro Iwamatsu Signed-off-by: Nobuhiro Iwamatsu --- board/renesas/gose/gose.c | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) (limited to 'board') diff --git a/board/renesas/gose/gose.c b/board/renesas/gose/gose.c index 2cef7019dc..715fba05f7 100644 --- a/board/renesas/gose/gose.c +++ b/board/renesas/gose/gose.c @@ -93,7 +93,7 @@ void arch_preboot_os(void) int board_init(void) { /* adress of boot parameters */ - gd->bd->bi_boot_params = GOSE_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; /* Init PFC controller */ r8a7793_pinmux_init(); @@ -161,12 +161,6 @@ const struct rmobile_sysinfo sysinfo = { CONFIG_RMOBILE_BOARD_STRING }; -void dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = GOSE_SDRAM_BASE; - gd->bd->bi_dram[0].size = GOSE_SDRAM_SIZE; -} - void reset_cpu(ulong addr) { u8 val; -- cgit