From 85ec0bcc1bc40a67368461fee0435d79305168b1 Mon Sep 17 00:00:00 2001
From: wdenk <wdenk>
Date: Mon, 31 Mar 2003 16:34:49 +0000
Subject: * Patch by Arun Dharankar, 24 Mar 2003:   - add threads / scheduler
 example code

* Add patches by Robert Schwebel, 31 Mar 2003:
  - add ctrl-c support for kermit download
  - align bdinfo output on ARM

* Add CPU ID, version, and clock speed for INCA-IP
---
 board/at91rm9200dk/at91rm9200dk.c |  2 +-
 board/incaip/incaip.c             | 28 ++++++++++++++++++++++++++++
 board/incaip/memsetup.S           |  2 +-
 3 files changed, 30 insertions(+), 2 deletions(-)

(limited to 'board')

diff --git a/board/at91rm9200dk/at91rm9200dk.c b/board/at91rm9200dk/at91rm9200dk.c
index 7c3670bdf6..07def18fdc 100644
--- a/board/at91rm9200dk/at91rm9200dk.c
+++ b/board/at91rm9200dk/at91rm9200dk.c
@@ -23,7 +23,7 @@
  */
 
 #include <common.h>
-#include <AT91RM9200.h>
+#include <asm/arch/AT91RM9200.h>
 
 /* ------------------------------------------------------------------------- */
 /*
diff --git a/board/incaip/incaip.c b/board/incaip/incaip.c
index 72f1c21512..10171ddc10 100644
--- a/board/incaip/incaip.c
+++ b/board/incaip/incaip.c
@@ -27,6 +27,8 @@
 #include <asm/inca-ip.h>
 
 
+extern uint incaip_get_cpuclk(void);
+
 static ulong max_sdram_size(void)
 {
 	/* The only supported SDRAM data width is 16bit.
@@ -127,3 +129,29 @@ long int initdram(int board_type)
 	return max_size;
 }
 
+int checkboard (void)
+{
+
+	unsigned long chipid = *INCA_IP_WDT_CHIPID;
+	int part_num;
+
+	puts ("Board: INCA-IP ");
+	part_num = (chipid >> 12) & 0xffff;
+	switch (part_num) {
+	case 0xc0:
+		printf ("Standard Version, ");
+		break;
+	case 0xc1:
+		printf ("Basic Version, ");
+		break;
+	default:
+		printf ("Unknown Part Number 0x%x ", part_num);
+		break;
+	}
+
+	printf ("Chip V1.%ld, ", (chipid >> 28));
+
+	printf("CPU Speed %d MHz\n", incaip_get_cpuclk()/1000000);
+
+	return 0;
+}
diff --git a/board/incaip/memsetup.S b/board/incaip/memsetup.S
index 4faf627f07..0d4de5ad5e 100644
--- a/board/incaip/memsetup.S
+++ b/board/incaip/memsetup.S
@@ -68,7 +68,7 @@ memsetup:
 	sw	t1, EBU_ADDSEL0(t0)
 
 #if CPU_CLOCK_RATE==150000000   /* 150 MHz clock for the MIPS core */
-	li	t1, 0xE841417E
+	li	t1, 0xA841417E
 	sw	t1, EBU_BUSCON0(t0)   /* value set up by magic flash word */
 	sw	t1, EBU_BUSCON2(t0)
 #else /* 100 MHz */
-- 
cgit