From 4ea813d333feec005385f2eb602c3a676832be64 Mon Sep 17 00:00:00 2001 From: Jon Nettleton Date: Mon, 28 May 2018 19:10:30 +0300 Subject: arm: mvebu: switch clearfog to use device-tree i2c and gpio This switches the clearfog boards to use DM based gpio and i2c drivers. The io expanders are configured via their device-tree entries. Signed-off-by: Jon Nettleton [baruch: add DT i2c aliases] Signed-off-by: Baruch Siach Reviewed-by: Chris Packham Reviewed-by: Stefan Roese Signed-off-by: Stefan Roese --- board/solidrun/clearfog/clearfog.c | 22 ---------------------- 1 file changed, 22 deletions(-) (limited to 'board') diff --git a/board/solidrun/clearfog/clearfog.c b/board/solidrun/clearfog/clearfog.c index ede303d4eb..4e1386c8a2 100644 --- a/board/solidrun/clearfog/clearfog.c +++ b/board/solidrun/clearfog/clearfog.c @@ -32,22 +32,6 @@ DECLARE_GLOBAL_DATA_PTR; #define BOARD_GPP_POL_LOW 0x0 #define BOARD_GPP_POL_MID 0x0 -/* IO expander on Marvell GP board includes e.g. fan enabling */ -struct marvell_io_exp { - u8 chip; - u8 addr; - u8 val; -}; - -static struct marvell_io_exp io_exp[] = { - { 0x20, 2, 0x40 }, /* Deassert both mini pcie reset signals */ - { 0x20, 6, 0xf9 }, - { 0x20, 2, 0x46 }, /* rst signals and ena USB3 current limiter */ - { 0x20, 6, 0xb9 }, - { 0x20, 3, 0x00 }, /* Set SFP_TX_DIS to zero */ - { 0x20, 7, 0xbf }, /* Drive SFP_TX_DIS to zero */ -}; - static struct serdes_map board_serdes_map[] = { {SATA0, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0}, {SGMII1, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0}, @@ -126,8 +110,6 @@ int board_early_init_f(void) int board_init(void) { - int i; - /* Address of boot parameters */ gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; @@ -142,10 +124,6 @@ int board_init(void) setbits_le32(MVEBU_GPIO0_BASE + 0x0, BIT(19)); mdelay(10); - /* Init I2C IO expanders */ - for (i = 0; i < ARRAY_SIZE(io_exp); i++) - i2c_write(io_exp[i].chip, io_exp[i].addr, 1, &io_exp[i].val, 1); - return 0; } -- cgit From 87a62bce28a61199f7e51a39ec7f441af5a313cc Mon Sep 17 00:00:00 2001 From: Chris Packham Date: Wed, 30 May 2018 20:14:35 +1200 Subject: ARM: add SBx81LIFKW board This is a series of line cards for Allied Telesis's SBx8100 chassis switch. The CPU block is common to the SBx81GS24a, SBx81XS6, SBx81XS16 and SBx81GT40 cards collectively referred to as SBx81LIFKW in u-boot. Reviewed-by: Stefan Roese Signed-off-by: Chris Packham Signed-off-by: Stefan Roese --- board/alliedtelesis/SBx81LIFKW/Kconfig | 12 ++ board/alliedtelesis/SBx81LIFKW/MAINTAINERS | 7 ++ board/alliedtelesis/SBx81LIFKW/Makefile | 7 ++ board/alliedtelesis/SBx81LIFKW/kwbimage.cfg | 47 +++++++ board/alliedtelesis/SBx81LIFKW/sbx81lifkw.c | 187 ++++++++++++++++++++++++++++ 5 files changed, 260 insertions(+) create mode 100644 board/alliedtelesis/SBx81LIFKW/Kconfig create mode 100644 board/alliedtelesis/SBx81LIFKW/MAINTAINERS create mode 100644 board/alliedtelesis/SBx81LIFKW/Makefile create mode 100644 board/alliedtelesis/SBx81LIFKW/kwbimage.cfg create mode 100644 board/alliedtelesis/SBx81LIFKW/sbx81lifkw.c (limited to 'board') diff --git a/board/alliedtelesis/SBx81LIFKW/Kconfig b/board/alliedtelesis/SBx81LIFKW/Kconfig new file mode 100644 index 0000000000..5c2609b7f4 --- /dev/null +++ b/board/alliedtelesis/SBx81LIFKW/Kconfig @@ -0,0 +1,12 @@ +if TARGET_SBx81LIFKW + +config SYS_BOARD + default "SBx81LIFKW" + +config SYS_VENDOR + default "alliedtelesis" + +config SYS_CONFIG_NAME + default "SBx81LIFKW" + +endif diff --git a/board/alliedtelesis/SBx81LIFKW/MAINTAINERS b/board/alliedtelesis/SBx81LIFKW/MAINTAINERS new file mode 100644 index 0000000000..31ccec0e9b --- /dev/null +++ b/board/alliedtelesis/SBx81LIFKW/MAINTAINERS @@ -0,0 +1,7 @@ +SBx81LIFKW BOARD +M: Chris Packham +S: Maintained +F: board/alliedtelesis/SBx81LIFKW/ +F: include/configs/SBx81LIFKW +F: configs/SBx81LIFKW_defconfig +F: arch/arm/dts/kirkwood-atl-sbx81lifkw.dts diff --git a/board/alliedtelesis/SBx81LIFKW/Makefile b/board/alliedtelesis/SBx81LIFKW/Makefile new file mode 100644 index 0000000000..806020ed85 --- /dev/null +++ b/board/alliedtelesis/SBx81LIFKW/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2010, 2018 +# Allied Telesis +# + +obj-y += sbx81lifkw.o diff --git a/board/alliedtelesis/SBx81LIFKW/kwbimage.cfg b/board/alliedtelesis/SBx81LIFKW/kwbimage.cfg new file mode 100644 index 0000000000..9726f15e28 --- /dev/null +++ b/board/alliedtelesis/SBx81LIFKW/kwbimage.cfg @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2018 Allied Telesis +# +# Refer docs/README.kwimage for more details about how-to configure +# and create kirkwood boot image +# + +# Boot Media configurations +BOOT_FROM spi # Boot from SPI flash + +# SOC registers configuration using bootrom header extension +# Maximum KWBIMAGE_MAX_CONFIG configurations allowed +DATA 0xffd100e0 0x1b1b1b1b +DATA 0xffd20134 0xffffffff +DATA 0xffd20138 0x009fffff +DATA 0xffd20154 0x00000000 +DATA 0xffd2014c 0x00000000 +DATA 0xffd20148 0x00000001 + +# Dram initalization for 1 x x16 +# DDR II Micron part number MT47H64M16HR-3 +# MClk 333MHz, Size 128MB, ECC disable +# +DATA 0xffd01400 0x43000618 +DATA 0xffd01404 0x35143000 +DATA 0xffd01408 0x11012227 +DATA 0xffd0140c 0x00000819 +DATA 0xffd01410 0x0000000d +DATA 0xffd01414 0x00000000 +DATA 0xffd01418 0x00000000 +DATA 0xffd0141c 0x00000632 +DATA 0xffd01420 0x00000040 +DATA 0xffd01424 0x0000f07f +DATA 0xffd01500 0x00000000 # SDRAM CS[0] Base address at 0x00000000 +DATA 0xffd01504 0x07FFFFF1 # SDRAM CS[0] Size 128MiB +DATA 0xffd01508 0x10000000 +DATA 0xffd0150c 0x00FFFFF4 # SDRAM CS[1] Size, window disabled +DATA 0xffd01514 0x00FFFFF8 # SDRAM CS[2] Size, window disabled +DATA 0xffd0151c 0x00FFFFFC # SDRAM CS[3] Size, window disabled +DATA 0xffd01494 0x00030000 +DATA 0xffd01498 0x00000000 +DATA 0xffd0149c 0x0000e803 +DATA 0xffd01480 0x00000001 + +# End of Header extension +DATA 0x0 0x0 diff --git a/board/alliedtelesis/SBx81LIFKW/sbx81lifkw.c b/board/alliedtelesis/SBx81LIFKW/sbx81lifkw.c new file mode 100644 index 0000000000..3cacdc8372 --- /dev/null +++ b/board/alliedtelesis/SBx81LIFKW/sbx81lifkw.c @@ -0,0 +1,187 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2010, 2018 + * Allied Telesis + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/* Note: GPIO differences between specific boards + * + * We're trying to avoid having multiple build targets for all the Kirkwood + * based boards one area where things tend to differ is GPIO usage. For the + * most part the GPIOs driven by the bootloader are similar enough in function + * that there is no harm in driving them. + * + * XZ4 XS6 XS16 GS24A GT40 GP24A GT24A + * GPIO39 - INT(<) NC MUX_RST_N(>) NC POE_DIS_N(>) NC + */ + +#define SBX81LIFKW_OE_LOW ~(BIT(31) | BIT(30) | BIT(28) | BIT(27) | \ + BIT(18) | BIT(17) | BIT(13) | BIT(12) | \ + BIT(10)) +#define SBX81LIFKW_OE_HIGH ~(BIT(0) | BIT(1) | BIT(7)) +#define SBX81LIFKW_OE_VAL_LOW (BIT(31) | BIT(30) | BIT(28) | BIT(27)) +#define SBX81LIFKW_OE_VAL_HIGH (BIT(0) | BIT(1)) + +#define MV88E6097_RESET 27 + +DECLARE_GLOBAL_DATA_PTR; + +struct led { + u32 reg; + u32 value; + u32 mask; +}; + +struct led amber_solid = { + MVEBU_GPIO0_BASE, + BIT(10), + BIT(18) | BIT(10) +}; + +struct led green_solid = { + MVEBU_GPIO0_BASE, + BIT(18) | BIT(10), + BIT(18) | BIT(10) +}; + +struct led amber_flash = { + MVEBU_GPIO0_BASE, + 0, + BIT(18) | BIT(10) +}; + +struct led green_flash = { + MVEBU_GPIO0_BASE, + BIT(18), + BIT(18) | BIT(10) +}; + +static void status_led_set(struct led *led) +{ + clrsetbits_le32(led->reg, led->mask, led->value); +} + +int board_early_init_f(void) +{ + /* + * default gpio configuration + * There are maximum 64 gpios controlled through 2 sets of registers + * the below configuration configures mainly initial LED status + */ + mvebu_config_gpio(SBX81LIFKW_OE_VAL_LOW, + SBX81LIFKW_OE_VAL_HIGH, + SBX81LIFKW_OE_LOW, SBX81LIFKW_OE_HIGH); + + /* Multi-Purpose Pins Functionality configuration */ + static const u32 kwmpp_config[] = { + MPP0_SPI_SCn, + MPP1_SPI_MOSI, + MPP2_SPI_SCK, + MPP3_SPI_MISO, + MPP4_UART0_RXD, + MPP5_UART0_TXD, + MPP6_SYSRST_OUTn, + MPP7_PEX_RST_OUTn, + MPP8_TW_SDA, + MPP9_TW_SCK, + MPP10_GPO, + MPP11_GPIO, + MPP12_GPO, + MPP13_GPIO, + MPP14_GPIO, + MPP15_UART0_RTS, + MPP16_UART0_CTS, + MPP17_GPIO, + MPP18_GPO, + MPP19_GPO, + MPP20_GPIO, + MPP21_GPIO, + MPP22_GPIO, + MPP23_GPIO, + MPP24_GPIO, + MPP25_GPIO, + MPP26_GPIO, + MPP27_GPIO, + MPP28_GPIO, + MPP29_GPIO, + MPP30_GPIO, + MPP31_GPIO, + MPP32_GPIO, + MPP33_GPIO, + MPP34_GPIO, + MPP35_GPIO, + MPP36_GPIO, + MPP37_GPIO, + MPP38_GPIO, + MPP39_GPIO, + MPP40_GPIO, + MPP41_GPIO, + MPP42_GPIO, + MPP43_GPIO, + MPP44_GPIO, + MPP45_GPIO, + MPP46_GPIO, + MPP47_GPIO, + MPP48_GPIO, + MPP49_GPIO, + 0 + }; + + kirkwood_mpp_conf(kwmpp_config, NULL); + return 0; +} + +int board_init(void) +{ + /* Power-down unused subsystems. The required + * subsystems are: + * + * GE0 b0 + * PEX0 PHY b1 + * PEX0.0 b2 + * TSU b5 + * SDRAM b6 + * RUNIT b7 + */ + writel((BIT(0) | BIT(1) | BIT(2) | + BIT(5) | BIT(6) | BIT(7)), + KW_CPU_REG_BASE + 0x1c); + + /* address of boot parameters */ + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; + + status_led_set(&amber_solid); + + return 0; +} + +#ifdef CONFIG_MV88E61XX_SWITCH +/* Configure and enable Switch and PHY */ +void reset_phy(void) +{ + /* Ensure the 88e6097 gets at least 10ms Reset + */ + kw_gpio_set_value(MV88E6097_RESET, 0); + mdelay(20); + kw_gpio_set_value(MV88E6097_RESET, 1); + mdelay(20); +} +#endif + +#ifdef CONFIG_MISC_INIT_R +int misc_init_r(void) +{ + status_led_set(&green_flash); + + return 0; +} +#endif -- cgit From 54e3316ffa46bd81e55216cd5aa5f087e9de9f8f Mon Sep 17 00:00:00 2001 From: Chris Packham Date: Sun, 3 Jun 2018 16:21:27 +1200 Subject: ARM: kirkwood: SBx81LIFKW: Enable network hardware The SBx81LIFKW boards connect to the internal chassis management network via a Marvell 88e6097 L2 switch. The chassis connections are direct serdes on ports 8 and 9 with a RGMII interface on port 10 connected to the CPU MAC. For debugging purposes ports 0 and 1 are also taken out to headers on the board. Because the debug interfaces are sometimes connected to with straight ribbon cables we need to run them at 10Mbps. Signed-off-by: Chris Packham Reviewed-by: Stefan Roese Signed-off-by: Stefan Roese --- board/alliedtelesis/SBx81LIFKW/sbx81lifkw.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) (limited to 'board') diff --git a/board/alliedtelesis/SBx81LIFKW/sbx81lifkw.c b/board/alliedtelesis/SBx81LIFKW/sbx81lifkw.c index 3cacdc8372..e58bbf07ef 100644 --- a/board/alliedtelesis/SBx81LIFKW/sbx81lifkw.c +++ b/board/alliedtelesis/SBx81LIFKW/sbx81lifkw.c @@ -164,9 +164,15 @@ int board_init(void) return 0; } -#ifdef CONFIG_MV88E61XX_SWITCH -/* Configure and enable Switch and PHY */ +#ifdef CONFIG_RESET_PHY_R +/* automatically defined by kirkwood config.h */ void reset_phy(void) +{ +} +#endif + +#ifdef CONFIG_MV88E61XX_SWITCH +int mv88e61xx_hw_reset(struct phy_device *phydev) { /* Ensure the 88e6097 gets at least 10ms Reset */ @@ -174,6 +180,10 @@ void reset_phy(void) mdelay(20); kw_gpio_set_value(MV88E6097_RESET, 1); mdelay(20); + + phydev->advertising = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full; + + return 0; } #endif -- cgit