From 79011f358f6aab88cc8334d26d11b0ceddc176e9 Mon Sep 17 00:00:00 2001 From: Suniel Mahesh Date: Thu, 2 Apr 2020 18:22:30 +0530 Subject: rockchip: board: roc-pc-rk3399: Remove support for push button In case of a power interruption, human intervention is required which is not desirable if the device is installed at a remote location. Drop yellow LED as it is not much of use. Keep red LED(diy-led) as it is, to indicate board in full power mode. Signed-off-by: Suniel Mahesh Reviewed-by: Kever Yang --- board/firefly/roc-pc-rk3399/roc-pc-rk3399.c | 16 +--------------- 1 file changed, 1 insertion(+), 15 deletions(-) (limited to 'board') diff --git a/board/firefly/roc-pc-rk3399/roc-pc-rk3399.c b/board/firefly/roc-pc-rk3399/roc-pc-rk3399.c index de9185a7ce..0fe1914c0f 100644 --- a/board/firefly/roc-pc-rk3399/roc-pc-rk3399.c +++ b/board/firefly/roc-pc-rk3399/roc-pc-rk3399.c @@ -10,7 +10,6 @@ #include #include #include -#include #ifndef CONFIG_SPL_BUILD int board_early_init_f(void) @@ -34,26 +33,13 @@ out: #if defined(CONFIG_TPL_BUILD) -#define PMUGRF_BASE 0xff320000 #define GPIO0_BASE 0xff720000 int board_early_init_f(void) { struct rockchip_gpio_regs * const gpio0 = (void *)GPIO0_BASE; - struct rk3399_pmugrf_regs * const pmugrf = (void *)PMUGRF_BASE; - /** - * 1. Glow yellow LED, termed as low power - * 2. Poll for on board power key press - * 3. Once 2 done, off yellow and glow red LED, termed as full power - * 4. Continue booting... - */ - spl_gpio_output(gpio0, GPIO(BANK_A, 2), 1); - - spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_A, 5), GPIO_PULL_NORMAL); - while (readl(&gpio0->ext_port) & 0x20); - - spl_gpio_output(gpio0, GPIO(BANK_A, 2), 0); + /* Turn on red LED, indicating full power mode */ spl_gpio_output(gpio0, GPIO(BANK_B, 5), 1); return 0; -- cgit From 286bcdb40f11def282117e16401bb85502e426a8 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Wed, 29 Apr 2020 21:03:53 +0530 Subject: sifive: fu540: Enable spi-nor flash support HiFive Unleashed A00 support is25wp256 spi-nor flash, So enable the same and add test result log for future reference. Tested on SiFive FU540 board. Thanks to Sagar for various use cases and tests. [QUAD mode in dt with spi-tx-bus-width: <4>] pp opcode = 0x34 [QUAD MODE] read opcode = 0x6c [QUAD MODE] erase opcode = 0x21 SPI-NOR: 1. erase entire flash: Pass 2. write entire flash: Pass 3. read entire flash: Pass 4. cmp 32MiB read back data: Pass 5. MMC: Booted Linux and dtb from mmc [SPI MODE in dt with spi-tx-bus-width: <1>] pp opcode = 0x12 [SPI MODE] read opcode = 0xc [SPI MODE] erase opcode = 0x21 SPI-NOR: 1. erase entire flash: Pass 2. write entire flash: Pass 3. read entire flash: Pass 4. cmp 32MiB read back data: Pass 5. MMC: Booted Linux and dtb from mmc Signed-off-by: Jagan Teki Reviewed-by: Bin Meng Tested-by: Sagar Kadam --- board/sifive/fu540/Kconfig | 3 +++ 1 file changed, 3 insertions(+) (limited to 'board') diff --git a/board/sifive/fu540/Kconfig b/board/sifive/fu540/Kconfig index 5ca21474de..75661f35f8 100644 --- a/board/sifive/fu540/Kconfig +++ b/board/sifive/fu540/Kconfig @@ -26,6 +26,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy imply CMD_FS_GENERIC imply CMD_NET imply CMD_PING + imply CMD_SF imply CLK_SIFIVE imply CLK_SIFIVE_FU540_PRCI imply DOS_PARTITION @@ -40,6 +41,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy imply SIFIVE_SERIAL imply SPI imply SPI_SIFIVE + imply SPI_FLASH + imply SPI_FLASH_ISSI imply MMC imply MMC_SPI imply MMC_BROKEN_CD -- cgit From bab972948e152e468fa5ab34764769fc4cddcaab Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Mon, 27 Apr 2020 14:52:53 +0800 Subject: rockchip: rk3328: Add support for ROC-RK3328-CC board The ROC-RK3328-CC from Firefly and Libre Computer Project is a credit card size development board based on the Rockchip RK3328 SoC, with: - 1/2/4 GB DDR4 DRAM - eMMC connector for optional module - micro SD card slot - 1 x USB 3.0 host port - 2 x USB 2.0 host port - 1 x USB 2.0 OTG port - HDMI video output - TRRS connector with audio and composite video output - gigabit Ethernet - consumer IR receiver - debug UART pins The ROC-RK3328-CC has the enable pin of the SD card power switch tied to GPIO_0_D6. This pin also has the function SDMMC0_PWREN, which is muxed by default. SDMMC0_PWREN is an active high signal controlled by the MMC controller, however the switch enable is active low, and pulled low (enabled) by default to make things work on boot. As such, we need to mux away from SDMMC0_PWREN and use GPIO to enable power to the card. The default GPIO state for the pin is pull-down and input, which doesn't require extra configuration when paired with the external pull-down and active low switch. Deal with this by enabling regulator support in SPL, and setting "u-boot,dm-spl" for the regulator and other device nodes needed for muxing the pin. The device tree file is synced from the Linux kernel next-20200324. Signed-off-by: Chen-Yu Tsai Reviewed-by: Kever Yang --- board/rockchip/evb_rk3328/MAINTAINERS | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'board') diff --git a/board/rockchip/evb_rk3328/MAINTAINERS b/board/rockchip/evb_rk3328/MAINTAINERS index c661d2e06a..89becf41c5 100644 --- a/board/rockchip/evb_rk3328/MAINTAINERS +++ b/board/rockchip/evb_rk3328/MAINTAINERS @@ -5,6 +5,13 @@ F: board/rockchip/evb_rk3328 F: include/configs/evb_rk3328.h F: configs/evb-rk3328_defconfig +ROC-RK3328-CC +M: Loic Devulder +M: Chen-Yu Tsai +S: Maintained +F: configs/roc-cc-rk3328_defconfig +F: arch/arm/dts/rk3328-roc-cc-u-boot.dtsi + ROCK64-RK3328 M: Matwey V. Kornilov S: Maintained -- cgit From f417d71ea78be5b8d506531911b747beae87cb54 Mon Sep 17 00:00:00 2001 From: Suniel Mahesh Date: Tue, 28 Apr 2020 15:30:19 +0530 Subject: rk3399: Add ROC-RK3399-PC Mezzanine board Add Firefly ROC-RK3399-PC Mezzanine board which is an extension board on top of roc-rk3399-pc. Will drop the separate defconfig file, once we support the board detection at runtime. Signed-off-by: Suniel Mahesh Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- board/firefly/roc-pc-rk3399/MAINTAINERS | 2 ++ 1 file changed, 2 insertions(+) (limited to 'board') diff --git a/board/firefly/roc-pc-rk3399/MAINTAINERS b/board/firefly/roc-pc-rk3399/MAINTAINERS index 7564dd252d..68a5b757d1 100644 --- a/board/firefly/roc-pc-rk3399/MAINTAINERS +++ b/board/firefly/roc-pc-rk3399/MAINTAINERS @@ -1,6 +1,8 @@ ROC-RK3399-PC M: Levin Du +M: Suniel Mahesh S: Maintained F: board/firefly/roc-pc-rk3399 F: include/configs/roc-pc-rk3399.h F: configs/roc-pc-rk3399_defconfig +F: configs/roc-pc-mezzanine-rk3399_defconfig -- cgit From d597e613745155d2c48ed90617b3fce81af92fbd Mon Sep 17 00:00:00 2001 From: Deepak Das Date: Sun, 26 Apr 2020 16:11:50 +0530 Subject: rockchip: rk3399: Add Nanopi M4 2GB board support commit b2f5da9dd068 ("rockchip: rk3399: Add Nanopi M4 board support") added support for Nanopi M4 board with Dual-Channel 4GB LPDDR3-1866 RAM. This patch adds another variant of NanoPi M4 board with Dual-Channel 2GB DDR3-1866 RAM. Signed-off-by: Deepak Das --- board/rockchip/evb_rk3399/MAINTAINERS | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'board') diff --git a/board/rockchip/evb_rk3399/MAINTAINERS b/board/rockchip/evb_rk3399/MAINTAINERS index 0834254f6d..792df1087f 100644 --- a/board/rockchip/evb_rk3399/MAINTAINERS +++ b/board/rockchip/evb_rk3399/MAINTAINERS @@ -42,6 +42,13 @@ S: Maintained F: configs/nanopi-m4-rk3399_defconfig F: arch/arm/dts/rk3399-nanopi-m4-u-boot.dtsi +NANOPI-M4-2GB +M: Jagan Teki +M: Deepak Das +S: Maintained +F: configs/nanopi-m4-2gb-rk3399_defconfig +F: arch/arm/dts/rk3399-nanopi-m4-2gb-u-boot.dtsi + NANOPI-NEO4 M: Jagan Teki S: Maintained -- cgit From 74014dfcd8d990225c9ce2943a41c08896d0e7a6 Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Fri, 1 May 2020 20:04:01 +0800 Subject: dm: powerpc: P1020: add i2c DM support This supports i2c DM for SoC P1020 Signed-off-by: Biwen Li Reviewed-by: Priyanka Jain --- board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 24 +++++++++++++++++++++++- 1 file changed, 23 insertions(+), 1 deletion(-) (limited to 'board') diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c index 71fca8ca1e..f668d7efb1 100644 --- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c +++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2010-2011, 2013 Freescale Semiconductor, Inc. + * Copyright 2020 NXP */ #include @@ -227,6 +228,7 @@ int checkboard(void) struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); u8 in, out, io_config, val; + int bus_num = CONFIG_SYS_SPD_BUS_NUM; printf("Board: %s CPLD: V%d.%d PCBA: V%d.0\n", CONFIG_BOARDNAME, in_8(&cpld_data->cpld_rev_major) & 0x0F, @@ -234,7 +236,26 @@ int checkboard(void) in_8(&cpld_data->pcba_rev) & 0x0F); /* Initialize i2c early for rom_loc and flash bank information */ - i2c_set_bus_num(CONFIG_SYS_SPD_BUS_NUM); + #if defined(CONFIG_DM_I2C) + struct udevice *dev; + int ret; + + ret = i2c_get_chip_for_busnum(bus_num, CONFIG_SYS_I2C_PCA9557_ADDR, + 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", __func__, + bus_num); + return -ENXIO; + } + + if (dm_i2c_read(dev, 0, &in, 1) < 0 || + dm_i2c_read(dev, 1, &out, 1) < 0 || + dm_i2c_read(dev, 3, &io_config, 1) < 0) { + printf("Error reading i2c boot information!\n"); + return 0; /* Don't want to hang() on this error */ + } + #else /* Non DM I2C support - will be removed */ + i2c_set_bus_num(bus_num); if (i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 0, 1, &in, 1) < 0 || i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 1, 1, &out, 1) < 0 || @@ -242,6 +263,7 @@ int checkboard(void) printf("Error reading i2c boot information!\n"); return 0; /* Don't want to hang() on this error */ } + #endif val = (in & io_config) | (out & (~io_config)); -- cgit From 9e9771a6105785189828706418945748d4db89a1 Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Fri, 1 May 2020 20:04:11 +0800 Subject: dm: powerpc: T1023/T1024: add i2c DM support This supports i2c DM for SoC T1023/T1024 Signed-off-by: Biwen Li Reviewed-by: Priyanka Jain --- board/freescale/t102xqds/t102xqds.c | 95 ++++++++++++++++++++++++++++++++++++- board/freescale/t102xqds/t102xqds.h | 3 +- board/freescale/t102xrdb/t102xrdb.c | 71 +++++++++++++++++++++++++-- 3 files changed, 162 insertions(+), 7 deletions(-) (limited to 'board') diff --git a/board/freescale/t102xqds/t102xqds.c b/board/freescale/t102xqds/t102xqds.c index e42337e47a..32b4780376 100644 --- a/board/freescale/t102xqds/t102xqds.c +++ b/board/freescale/t102xqds/t102xqds.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2020 NXP */ #include @@ -75,11 +76,24 @@ int checkboard(void) return 0; } -int select_i2c_ch_pca9547(u8 ch) +int select_i2c_ch_pca9547(u8 ch, int bus_num) { int ret; +#ifdef CONFIG_DM_I2C + struct udevice *dev; + ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI, + 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", __func__, + bus_num); + return ret; + } + + ret = dm_i2c_write(dev, 0, &ch, 1); +#else ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); +#endif if (ret) { puts("PCA: failed to select proper channel\n"); return ret; @@ -191,6 +205,82 @@ void board_retimer_ds125df111_init(void) { u8 reg; +#ifdef CONFIG_DM_I2C + struct udevice *dev; + int ret, bus_num = 0; + + ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI, + 1, &dev); + if (ret) + goto failed; + + /* Retimer DS125DF111 is connected to I2C1_CH7_CH5 */ + reg = I2C_MUX_CH7; + dm_i2c_write(dev, 0, ®, 1); + + ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_SEC, + 1, &dev); + if (ret) + goto failed; + + reg = I2C_MUX_CH5; + dm_i2c_write(dev, 0, ®, 1); + + /* Access to Control/Shared register */ + ret = i2c_get_chip_for_busnum(bus_num, I2C_RETIMER_ADDR, + 1, &dev); + if (ret) + goto failed; + reg = 0x0; + dm_i2c_write(dev, 0xff, ®, 1); + + /* Read device revision and ID */ + dm_i2c_read(dev, 1, ®, 1); + debug("Retimer version id = 0x%x\n", reg); + + /* Enable Broadcast */ + reg = 0x0c; + dm_i2c_write(dev, 0xff, ®, 1); + + /* Reset Channel Registers */ + dm_i2c_read(dev, 0, ®, 1); + reg |= 0x4; + dm_i2c_write(dev, 0, ®, 1); + + /* Enable override divider select and Enable Override Output Mux */ + dm_i2c_read(dev, 9, ®, 1); + reg |= 0x24; + dm_i2c_write(dev, 9, ®, 1); + + /* Select VCO Divider to full rate (000) */ + dm_i2c_read(dev, 0x18, ®, 1); + reg &= 0x8f; + dm_i2c_write(dev, 0x18, ®, 1); + + /* Select active PFD MUX input as re-timed data (001) */ + dm_i2c_read(dev, 0x1e, ®, 1); + reg &= 0x3f; + reg |= 0x20; + dm_i2c_write(dev, 0x1e, ®, 1); + + /* Set data rate as 10.3125 Gbps */ + reg = 0x0; + dm_i2c_write(dev, 0x60, ®, 1); + reg = 0xb2; + dm_i2c_write(dev, 0x61, ®, 1); + reg = 0x90; + dm_i2c_write(dev, 0x62, ®, 1); + reg = 0xb3; + dm_i2c_write(dev, 0x63, ®, 1); + reg = 0xcd; + dm_i2c_write(dev, 0x64, ®, 1); + return; + +failed: + printf("%s: Cannot find udev for a bus %d\n", __func__, + bus_num); + return; +#else /* Retimer DS125DF111 is connected to I2C1_CH7_CH5 */ reg = I2C_MUX_CH7; i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, ®, 1); @@ -241,6 +331,7 @@ void board_retimer_ds125df111_init(void) i2c_write(I2C_RETIMER_ADDR, 0x63, 1, ®, 1); reg = 0xcd; i2c_write(I2C_RETIMER_ADDR, 0x64, 1, ®, 1); +#endif } int board_early_init_f(void) @@ -281,7 +372,7 @@ int board_early_init_r(void) MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, flash_esel, BOOKE_PAGESZ_256M, 1); #endif - select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0); board_mux_lane_to_slot(); board_retimer_ds125df111_init(); diff --git a/board/freescale/t102xqds/t102xqds.h b/board/freescale/t102xqds/t102xqds.h index 15de132598..d327b5edb9 100644 --- a/board/freescale/t102xqds/t102xqds.h +++ b/board/freescale/t102xqds/t102xqds.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2020 NXP */ #ifndef __T102x_QDS_H__ @@ -8,6 +9,6 @@ void fdt_fixup_board_enet(void *blob); void pci_of_setup(void *blob, bd_t *bd); -int select_i2c_ch_pca9547(u8 ch); +int select_i2c_ch_pca9547(u8 ch, int bus_num); #endif diff --git a/board/freescale/t102xrdb/t102xrdb.c b/board/freescale/t102xrdb/t102xrdb.c index eee09a5701..a34490c8bd 100644 --- a/board/freescale/t102xrdb/t102xrdb.c +++ b/board/freescale/t102xrdb/t102xrdb.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2020 NXP */ #include @@ -250,8 +251,69 @@ static u32 t1023rdb_ctrl(u32 ctrl_type) { ccsr_gpio_t __iomem *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - u32 val, orig_bus = i2c_get_bus_num(); + u32 val; u8 tmp; + int bus_num = I2C_PCA6408_BUS_NUM; + +#ifdef CONFIG_DM_I2C + struct udevice *dev; + int ret; + + ret = i2c_get_chip_for_busnum(bus_num, I2C_PCA6408_ADDR, + 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", __func__, + bus_num); + return ret; + } + switch (ctrl_type) { + case GPIO1_SD_SEL: + val = in_be32(&pgpio->gpdat); + val |= GPIO1_SD_SEL; + out_be32(&pgpio->gpdat, val); + setbits_be32(&pgpio->gpdir, GPIO1_SD_SEL); + break; + case GPIO1_EMMC_SEL: + val = in_be32(&pgpio->gpdat); + val &= ~GPIO1_SD_SEL; + out_be32(&pgpio->gpdat, val); + setbits_be32(&pgpio->gpdir, GPIO1_SD_SEL); + break; + case GPIO3_GET_VERSION: + pgpio = (ccsr_gpio_t *)(CONFIG_SYS_MPC85xx_GPIO_ADDR + + GPIO3_OFFSET); + val = in_be32(&pgpio->gpdat); + val = ((val & GPIO3_BRD_VER_MASK) >> 26) & 0x3; + if (val == 0x3) /* GPIO3_4/5 not used on RevB */ + val = 0; + return val; + case I2C_GET_BANK: + dm_i2c_read(dev, 0, &tmp, 1); + tmp &= 0x7; + tmp = ((tmp & 1) << 2) | (tmp & 2) | ((tmp & 4) >> 2); + return tmp; + case I2C_SET_BANK0: + tmp = 0x0; + dm_i2c_write(dev, 1, &tmp, 1); + tmp = 0xf8; + dm_i2c_write(dev, 3, &tmp, 1); + /* asserting HRESET_REQ */ + out_be32(&gur->rstcr, 0x2); + break; + case I2C_SET_BANK4: + tmp = 0x1; + dm_i2c_write(dev, 1, &tmp, 1); + tmp = 0xf8; + dm_i2c_write(dev, 3, &tmp, 1); + out_be32(&gur->rstcr, 0x2); + break; + default: + break; + } +#else + u32 orig_bus; + + orig_bus = i2c_get_bus_num(); switch (ctrl_type) { case GPIO1_SD_SEL: @@ -275,14 +337,14 @@ static u32 t1023rdb_ctrl(u32 ctrl_type) val = 0; return val; case I2C_GET_BANK: - i2c_set_bus_num(I2C_PCA6408_BUS_NUM); + i2c_set_bus_num(bus_num); i2c_read(I2C_PCA6408_ADDR, 0, 1, &tmp, 1); tmp &= 0x7; tmp = ((tmp & 1) << 2) | (tmp & 2) | ((tmp & 4) >> 2); i2c_set_bus_num(orig_bus); return tmp; case I2C_SET_BANK0: - i2c_set_bus_num(I2C_PCA6408_BUS_NUM); + i2c_set_bus_num(bus_num); tmp = 0x0; i2c_write(I2C_PCA6408_ADDR, 1, 1, &tmp, 1); tmp = 0xf8; @@ -291,7 +353,7 @@ static u32 t1023rdb_ctrl(u32 ctrl_type) out_be32(&gur->rstcr, 0x2); break; case I2C_SET_BANK4: - i2c_set_bus_num(I2C_PCA6408_BUS_NUM); + i2c_set_bus_num(bus_num); tmp = 0x1; i2c_write(I2C_PCA6408_ADDR, 1, 1, &tmp, 1); tmp = 0xf8; @@ -301,6 +363,7 @@ static u32 t1023rdb_ctrl(u32 ctrl_type) default: break; } +#endif return 0; } -- cgit From 2703e640d218d9bf297bd9ad9ccdd10e8bd2ce56 Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Fri, 1 May 2020 20:04:13 +0800 Subject: dm: ppc: p1010: add i2c DM support This supports i2c DM for SoC P1010 Signed-off-by: Biwen Li Reviewed-by: Priyanka Jain --- board/freescale/p1010rdb/p1010rdb.c | 156 +++++++++++++++++++++++++++++++++++- 1 file changed, 155 insertions(+), 1 deletion(-) (limited to 'board') diff --git a/board/freescale/p1010rdb/p1010rdb.c b/board/freescale/p1010rdb/p1010rdb.c index a086692683..65ac47263e 100644 --- a/board/freescale/p1010rdb/p1010rdb.c +++ b/board/freescale/p1010rdb/p1010rdb.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2010-2011 Freescale Semiconductor, Inc. + * Copyright 2020 NXP */ #include @@ -136,6 +137,125 @@ int config_board_mux(int ctrl_type) ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); u8 tmp; +#ifdef CONFIG_DM_I2C + struct udevice *dev; + int ret; +#if defined(CONFIG_TARGET_P1010RDB_PA) + struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); + + ret = i2c_get_chip_for_busnum(I2C_PCA9557_BUS_NUM, + I2C_PCA9557_ADDR1, 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", + __func__, I2C_PCA9557_BUS_NUM); + return ret; + } + switch (ctrl_type) { + case MUX_TYPE_IFC: + tmp = 0xf0; + dm_i2c_write(dev, 3, &tmp, 1); + tmp = 0x01; + dm_i2c_write(dev, 1, &tmp, 1); + sd_ifc_mux = MUX_TYPE_IFC; + clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK); + break; + case MUX_TYPE_SDHC: + tmp = 0xf0; + dm_i2c_write(dev, 3, &tmp, 1); + tmp = 0x05; + dm_i2c_write(dev, 1, &tmp, 1); + sd_ifc_mux = MUX_TYPE_SDHC; + clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK, + PMUXCR1_SDHC_ENABLE); + break; + case MUX_TYPE_SPIFLASH: + out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_FLASH); + break; + case MUX_TYPE_TDM: + out_8(&cpld_data->tdm_can_sel, MUX_CPLD_TDM); + out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_SLIC); + break; + case MUX_TYPE_CAN: + out_8(&cpld_data->tdm_can_sel, MUX_CPLD_CAN_UART); + break; + default: + break; + } +#elif defined(CONFIG_TARGET_P1010RDB_PB) + ret = i2c_get_chip_for_busnum(I2C_PCA9557_BUS_NUM, + I2C_PCA9557_ADDR2, 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", + __func__, I2C_PCA9557_BUS_NUM); + return ret; + } + switch (ctrl_type) { + case MUX_TYPE_IFC: + dm_i2c_read(dev, 0, &tmp, 1); + clrbits_8(&tmp, 0x04); + dm_i2c_write(dev, 1, &tmp, 1); + dm_i2c_read(dev, 3, &tmp, 1); + clrbits_8(&tmp, 0x04); + dm_i2c_write(dev, 3, &tmp, 1); + sd_ifc_mux = MUX_TYPE_IFC; + clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK); + break; + case MUX_TYPE_SDHC: + dm_i2c_read(dev, 0, &tmp, 1); + setbits_8(&tmp, 0x04); + dm_i2c_write(dev, 1, &tmp, 1); + dm_i2c_read(dev, 3, &tmp, 1); + clrbits_8(&tmp, 0x04); + dm_i2c_write(dev, 3, &tmp, 1); + sd_ifc_mux = MUX_TYPE_SDHC; + clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK, + PMUXCR1_SDHC_ENABLE); + break; + case MUX_TYPE_SPIFLASH: + dm_i2c_read(dev, 0, &tmp, 1); + clrbits_8(&tmp, 0x80); + dm_i2c_write(dev, 1, &tmp, 1); + dm_i2c_read(dev, 3, &tmp, 1); + clrbits_8(&tmp, 0x80); + dm_i2c_write(dev, 3, &tmp, 1); + break; + case MUX_TYPE_TDM: + dm_i2c_read(dev, 0, &tmp, 1); + setbits_8(&tmp, 0x82); + dm_i2c_write(dev, 1, &tmp, 1); + dm_i2c_read(dev, 3, &tmp, 1); + clrbits_8(&tmp, 0x82); + dm_i2c_write(dev, 3, &tmp, 1); + break; + case MUX_TYPE_CAN: + dm_i2c_read(dev, 0, &tmp, 1); + clrbits_8(&tmp, 0x02); + dm_i2c_write(dev, 1, &tmp, 1); + dm_i2c_read(dev, 3, &tmp, 1); + clrbits_8(&tmp, 0x02); + dm_i2c_write(dev, 3, &tmp, 1); + break; + case MUX_TYPE_CS0_NOR: + dm_i2c_read(dev, 0, &tmp, 1); + clrbits_8(&tmp, 0x08); + dm_i2c_write(dev, 1, &tmp, 1); + dm_i2c_read(dev, 3, &tmp, 1); + clrbits_8(&tmp, 0x08); + dm_i2c_write(dev, 3, &tmp, 1); + break; + case MUX_TYPE_CS0_NAND: + dm_i2c_read(dev, 0, &tmp, 1); + setbits_8(&tmp, 0x08); + dm_i2c_write(dev, 1, &tmp, 1); + dm_i2c_read(dev, 3, &tmp, 1); + clrbits_8(&tmp, 0x08); + dm_i2c_write(dev, 3, &tmp, 1); + break; + default: + break; + } +#endif +#else #if defined(CONFIG_TARGET_P1010RDB_PA) struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); @@ -242,6 +362,7 @@ int config_board_mux(int ctrl_type) break; } i2c_set_bus_num(orig_bus); +#endif #endif return 0; } @@ -250,9 +371,23 @@ int config_board_mux(int ctrl_type) int i2c_pca9557_read(int type) { u8 val; + int bus_num = I2C_PCA9557_BUS_NUM; - i2c_set_bus_num(I2C_PCA9557_BUS_NUM); +#ifdef CONFIG_DM_I2C + struct udevice *dev; + int ret; + + ret = i2c_get_chip_for_busnum(bus_num, I2C_PCA9557_ADDR2, 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", + __func__, bus_num); + return ret; + } + dm_i2c_read(dev, 0, &val, 1); +#else + i2c_set_bus_num(bus_num); i2c_read(I2C_PCA9557_ADDR2, 0, 1, &val, 1); +#endif switch (type) { case I2C_READ_BANK: @@ -280,11 +415,26 @@ int checkboard(void) printf("Board: %sRDB-PA, ", cpu->name); #elif defined(CONFIG_TARGET_P1010RDB_PB) printf("Board: %sRDB-PB, ", cpu->name); +#ifdef CONFIG_DM_I2C + struct udevice *dev; + int ret; + + ret = i2c_get_chip_for_busnum(I2C_PCA9557_BUS_NUM, I2C_PCA9557_ADDR2, + 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", __func__, + I2C_PCA9557_BUS_NUM); + return ret; + } + val = 0x0; /* no polarity inversion */ + dm_i2c_write(dev, 2, &val, 1); +#else i2c_set_bus_num(I2C_PCA9557_BUS_NUM); i2c_init(CONFIG_SYS_FSL_I2C_SPEED, CONFIG_SYS_FSL_I2C_SLAVE); val = 0x0; /* no polarity inversion */ i2c_write(I2C_PCA9557_ADDR2, 2, 1, &val, 1); #endif +#endif #ifdef CONFIG_SDCARD /* switch to IFC to read info from CPLD */ @@ -308,7 +458,11 @@ int checkboard(void) case 0xe: puts("SDHC\n"); val = 0x60; /* set pca9557 pin input/output */ +#ifdef CONFIG_DM_I2C + dm_i2c_write(dev, 3, &val, 1); +#else i2c_write(I2C_PCA9557_ADDR2, 3, 1, &val, 1); +#endif break; case 0x5: config_board_mux(MUX_TYPE_IFC); -- cgit From 01d97d5f18a28dfbb8d5e033f2408040fb4f8134 Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Fri, 1 May 2020 20:56:37 +0800 Subject: dm: ppc: MPC8548CDS: add i2c DM support This supports i2c DM for board MPC8548CDS Signed-off-by: Biwen Li Reviewed-by: Priyanka Jain --- board/freescale/common/sys_eeprom.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'board') diff --git a/board/freescale/common/sys_eeprom.c b/board/freescale/common/sys_eeprom.c index 6f151b0f71..c487e3a515 100644 --- a/board/freescale/common/sys_eeprom.c +++ b/board/freescale/common/sys_eeprom.c @@ -595,6 +595,7 @@ unsigned int get_cpu_board_revision(void) (void *)&be, sizeof(be)); #else struct udevice *dev; + int ret; #ifdef CONFIG_SYS_EEPROM_BUS_NUM ret = i2c_get_chip_for_busnum(CONFIG_SYS_EEPROM_BUS_NUM, CONFIG_SYS_I2C_EEPROM_ADDR, @@ -603,7 +604,7 @@ unsigned int get_cpu_board_revision(void) #else ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_EEPROM_ADDR, CONFIG_SYS_I2C_EEPROM_ADDR_LEN, - &dev) + &dev); #endif if (!ret) dm_i2c_read(dev, 0, (void *)&be, sizeof(be)); -- cgit From e6bd72f880a76652ce1d6742880e7efcd85b8fb1 Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Fri, 1 May 2020 20:04:17 +0800 Subject: dm: ppc: T4240: add i2c DM support This supports i2c DM for SoC T4240 Signed-off-by: Biwen Li Reviewed-by: Priyanka Jain --- board/freescale/common/vsc3316_3308.c | 258 +++++++++++++++++++++++++++++++++- board/freescale/t4qds/t4240qds.c | 45 +++++- 2 files changed, 295 insertions(+), 8 deletions(-) (limited to 'board') diff --git a/board/freescale/common/vsc3316_3308.c b/board/freescale/common/vsc3316_3308.c index 033fae020f..f0d273ca20 100644 --- a/board/freescale/common/vsc3316_3308.c +++ b/board/freescale/common/vsc3316_3308.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2020 NXP */ #include "vsc3316_3308.h" @@ -32,7 +33,22 @@ int vsc_if_enable(unsigned int vsc_addr) /* enable 2-wire Serial InterFace (I2C) */ data = 0x02; +#ifdef CONFIG_DM_I2C + int ret, bus_num = 0; + struct udevice *dev; + + ret = i2c_get_chip_for_busnum(bus_num, vsc_addr, + 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", __func__, + bus_num); + return ret; + } + + return dm_i2c_write(dev, INTERFACE_MODE_REG, &data, 1); +#else return i2c_write(vsc_addr, INTERFACE_MODE_REG, 1, &data, 1); +#endif } int vsc3316_config(unsigned int vsc_addr, int8_t con_arr[][2], @@ -45,6 +61,66 @@ int vsc3316_config(unsigned int vsc_addr, int8_t con_arr[][2], debug("VSC:Initializing VSC3316 at I2C address 0x%2x" " for Tx\n", vsc_addr); +#ifdef CONFIG_DM_I2C + int bus_num = 0; + struct udevice *dev; + + ret = i2c_get_chip_for_busnum(bus_num, vsc_addr, + 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", __func__, + bus_num); + return ret; + } + + ret = dm_i2c_read(dev, REVISION_ID_REG, &rev_id, 1); + if (ret < 0) { + printf("VSC:0x%x could not read REV_ID from device.\n", + vsc_addr); + return ret; + } + + if (rev_id != 0xab) { + printf("VSC: device at address 0x%x is not VSC3316/3308.\n", + vsc_addr); + return -ENODEV; + } + + ret = vsc_if_enable(vsc_addr); + if (ret) { + printf("VSC:0x%x could not configured for 2-wire I/F.\n", + vsc_addr); + return ret; + } + + /* config connections - page 0x00 */ + dm_i2c_reg_write(dev, CURRENT_PAGE_REGISTER, CONNECTION_CONFIG_PAGE); + + /* Making crosspoint connections, by connecting required + * input to output + */ + for (i = 0; i < num_con ; i++) + dm_i2c_reg_write(dev, con_arr[i][1], con_arr[i][0]); + + /* input state - page 0x13 */ + dm_i2c_reg_write(dev, CURRENT_PAGE_REGISTER, INPUT_STATE_REG); + /* Configuring the required input of the switch */ + for (i = 0; i < num_con ; i++) + dm_i2c_reg_write(dev, con_arr[i][0], 0x80); + + /* Setting Global Input LOS threshold value */ + dm_i2c_reg_write(dev, GLOBAL_INPUT_LOS, 0x60); + + /* config output mode - page 0x23 */ + dm_i2c_reg_write(dev, CURRENT_PAGE_REGISTER, OUTPUT_MODE_PAGE); + /* Turn ON the Output driver correspond to required output*/ + for (i = 0; i < num_con ; i++) + dm_i2c_reg_write(dev, con_arr[i][1], 0); + + /* configure global core control register, Turn on Global core power */ + dm_i2c_reg_write(dev, GLOBAL_CORE_CNTRL, 0); + +#else ret = i2c_read(vsc_addr, REVISION_ID_REG, 1, &rev_id, 1); if (ret < 0) { printf("VSC:0x%x could not read REV_ID from device.\n", @@ -90,6 +166,7 @@ int vsc3316_config(unsigned int vsc_addr, int8_t con_arr[][2], /* configure global core control register, Turn on Global core power */ i2c_reg_write(vsc_addr, GLOBAL_CORE_CNTRL, 0); +#endif vsc_wp_config(vsc_addr); @@ -107,6 +184,105 @@ int vsc3308_config_adjust(unsigned int vsc_addr, const int8_t con_arr[][2], debug("VSC:Initializing VSC3308 at I2C address 0x%x for Tx\n", vsc_addr); +#ifdef CONFIG_DM_I2C + int bus_num = 0; + struct udevice *dev; + + ret = i2c_get_chip_for_busnum(bus_num, vsc_addr, + 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", __func__, + bus_num); + return ret; + } + + ret = dm_i2c_read(dev, REVISION_ID_REG, &rev_id, 1); + if (ret < 0) { + printf("VSC:0x%x could not read REV_ID from device.\n", + vsc_addr); + return ret; + } + + if (rev_id != 0xab) { + printf("VSC: device at address 0x%x is not VSC3316/3308.\n", + vsc_addr); + return -ENODEV; + } + + ret = vsc_if_enable(vsc_addr); + if (ret) { + printf("VSC:0x%x could not configured for 2-wire I/F.\n", + vsc_addr); + return ret; + } + + /* config connections - page 0x00 */ + dm_i2c_reg_write(dev, CURRENT_PAGE_REGISTER, CONNECTION_CONFIG_PAGE); + + /* Configure Global Input ISE */ + dm_i2c_reg_write(dev, GLOBAL_INPUT_ISE1, 0); + dm_i2c_reg_write(dev, GLOBAL_INPUT_ISE2, 0); + + /* Configure Tx/Rx Global Output PE1 */ + dm_i2c_reg_write(dev, GLOBAL_OUTPUT_PE1, 0); + + /* Configure Tx/Rx Global Output PE2 */ + dm_i2c_reg_write(dev, GLOBAL_OUTPUT_PE2, 0); + + /* Configure Tx/Rx Global Input GAIN */ + dm_i2c_reg_write(dev, GLOBAL_INPUT_GAIN, 0x3F); + + /* Setting Global Input LOS threshold value */ + dm_i2c_reg_write(dev, GLOBAL_INPUT_LOS, 0xE0); + + /* Setting Global output termination */ + dm_i2c_reg_write(dev, GLOBAL_OUTPUT_TERMINATION, 0); + + /* Configure Tx/Rx Global Output level */ + if (vsc_addr == VSC3308_TX_ADDRESS) + dm_i2c_reg_write(dev, GLOBAL_OUTPUT_LEVEL, 4); + else + dm_i2c_reg_write(dev, GLOBAL_OUTPUT_LEVEL, 2); + + /* Making crosspoint connections, by connecting required + * input to output + */ + for (i = 0; i < num_con ; i++) + dm_i2c_reg_write(dev, con_arr[i][1], con_arr[i][0]); + + /* input state - page 0x13 */ + dm_i2c_reg_write(dev, CURRENT_PAGE_REGISTER, INPUT_STATE_REG); + /* Turning off all the required input of the switch */ + for (i = 0; i < num_con; i++) + dm_i2c_reg_write(dev, con_arr[i][0], 1); + + /* only turn on specific Tx/Rx requested by the XFI erratum */ + if (vsc_addr == VSC3308_TX_ADDRESS) { + dm_i2c_reg_write(dev, 2, 0); + dm_i2c_reg_write(dev, 3, 0); + } else { + dm_i2c_reg_write(dev, 0, 0); + dm_i2c_reg_write(dev, 1, 0); + } + + /* config output mode - page 0x23 */ + dm_i2c_reg_write(dev, CURRENT_PAGE_REGISTER, OUTPUT_MODE_PAGE); + /* Turn off the Output driver correspond to required output*/ + for (i = 0; i < num_con ; i++) + dm_i2c_reg_write(dev, con_arr[i][1], 1); + + /* only turn on specific Tx/Rx requested by the XFI erratum */ + if (vsc_addr == VSC3308_TX_ADDRESS) { + dm_i2c_reg_write(dev, 0, 0); + dm_i2c_reg_write(dev, 1, 0); + } else { + dm_i2c_reg_write(dev, 3, 0); + dm_i2c_reg_write(dev, 4, 0); + } + + /* configure global core control register, Turn on Global core power */ + dm_i2c_reg_write(dev, GLOBAL_CORE_CNTRL, 0); +#else ret = i2c_read(vsc_addr, REVISION_ID_REG, 1, &rev_id, 1); if (ret < 0) { printf("VSC:0x%x could not read REV_ID from device.\n", @@ -192,7 +368,7 @@ int vsc3308_config_adjust(unsigned int vsc_addr, const int8_t con_arr[][2], /* configure global core control register, Turn on Global core power */ i2c_reg_write(vsc_addr, GLOBAL_CORE_CNTRL, 0); - +#endif vsc_wp_config(vsc_addr); return 0; @@ -208,7 +384,69 @@ int vsc3308_config(unsigned int vsc_addr, const int8_t con_arr[][2], debug("VSC:Initializing VSC3308 at I2C address 0x%x" " for Tx\n", vsc_addr); +#ifdef CONFIG_DM_I2C + int bus_num = 0; + struct udevice *dev; + + ret = i2c_get_chip_for_busnum(bus_num, vsc_addr, + 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", __func__, + bus_num); + return ret; + } + ret = dm_i2c_read(dev, REVISION_ID_REG, &rev_id, 1); + if (ret < 0) { + printf("VSC:0x%x could not read REV_ID from device.\n", + vsc_addr); + return ret; + } + + if (rev_id != 0xab) { + printf("VSC: device at address 0x%x is not VSC3316/3308.\n", + vsc_addr); + return -ENODEV; + } + + ret = vsc_if_enable(vsc_addr); + if (ret) { + printf("VSC:0x%x could not configured for 2-wire I/F.\n", + vsc_addr); + return ret; + } + + /* config connections - page 0x00 */ + dm_i2c_reg_write(dev, CURRENT_PAGE_REGISTER, CONNECTION_CONFIG_PAGE); + + /* Making crosspoint connections, by connecting required + * input to output + */ + for (i = 0; i < num_con ; i++) + dm_i2c_reg_write(dev, con_arr[i][1], con_arr[i][0]); + + /*Configure Global Input ISE and gain */ + dm_i2c_reg_write(dev, GLOBAL_INPUT_ISE1, 0x12); + dm_i2c_reg_write(dev, GLOBAL_INPUT_ISE2, 0x12); + + /* input state - page 0x13 */ + dm_i2c_reg_write(dev, CURRENT_PAGE_REGISTER, INPUT_STATE_REG); + /* Turning ON the required input of the switch */ + for (i = 0; i < num_con ; i++) + dm_i2c_reg_write(dev, con_arr[i][0], 0); + + /* Setting Global Input LOS threshold value */ + dm_i2c_reg_write(dev, GLOBAL_INPUT_LOS, 0x60); + + /* config output mode - page 0x23 */ + dm_i2c_reg_write(dev, CURRENT_PAGE_REGISTER, OUTPUT_MODE_PAGE); + /* Turn ON the Output driver correspond to required output*/ + for (i = 0; i < num_con ; i++) + dm_i2c_reg_write(dev, con_arr[i][1], 0); + + /* configure global core control register, Turn on Global core power */ + dm_i2c_reg_write(dev, GLOBAL_CORE_CNTRL, 0); +#else ret = i2c_read(vsc_addr, REVISION_ID_REG, 1, &rev_id, 1); if (ret < 0) { printf("VSC:0x%x could not read REV_ID from device.\n", @@ -258,7 +496,7 @@ int vsc3308_config(unsigned int vsc_addr, const int8_t con_arr[][2], /* configure global core control register, Turn on Global core power */ i2c_reg_write(vsc_addr, GLOBAL_CORE_CNTRL, 0); - +#endif vsc_wp_config(vsc_addr); return 0; @@ -270,6 +508,22 @@ void vsc_wp_config(unsigned int vsc_addr) /* For new crosspoint configuration to occur, WP bit of * CORE_CONFIG_REG should be set 1 and then reset to 0 */ +#ifdef CONFIG_DM_I2C + int ret, bus_num = 0; + struct udevice *dev; + + ret = i2c_get_chip_for_busnum(bus_num, vsc_addr, + 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", __func__, + bus_num); + return; + } + + dm_i2c_reg_write(dev, CORE_CONFIG_REG, 0x01); + dm_i2c_reg_write(dev, CORE_CONFIG_REG, 0x0); +#else i2c_reg_write(vsc_addr, CORE_CONFIG_REG, 0x01); i2c_reg_write(vsc_addr, CORE_CONFIG_REG, 0x0); +#endif } diff --git a/board/freescale/t4qds/t4240qds.c b/board/freescale/t4qds/t4240qds.c index 5608774afd..869c01de92 100644 --- a/board/freescale/t4qds/t4240qds.c +++ b/board/freescale/t4qds/t4240qds.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2009-2012 Freescale Semiconductor, Inc. + * Copyright 2020 NXP */ #include @@ -91,11 +92,25 @@ int checkboard(void) return 0; } -int select_i2c_ch_pca9547(u8 ch) +int select_i2c_ch_pca9547(u8 ch, int bus_num) { int ret; +#ifdef CONFIG_DM_I2C + struct udevice *dev; + + ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI, + 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", __func__, + bus_num); + return ret; + } + + ret = dm_i2c_write(dev, 0, &ch, 1); +#else ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); +#endif if (ret) { puts("PCA: failed to select proper channel\n"); return ret; @@ -115,10 +130,28 @@ static inline int read_voltage(void) { int i, ret, voltage_read = 0; u16 vol_mon; +#ifdef CONFIG_DM_I2C + struct udevice *dev; + int bus_num = 0; +#endif for (i = 0; i < NUM_READINGS; i++) { +#ifdef CONFIG_DM_I2C + ret = i2c_get_chip_for_busnum(bus_num, I2C_VOL_MONITOR_ADDR, + 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", __func__, + bus_num); + return ret; + } + + ret = dm_i2c_read(dev, + I2C_VOL_MONITOR_BUS_V_OFFSET, + (void *)&vol_mon, 2); +#else ret = i2c_read(I2C_VOL_MONITOR_ADDR, I2C_VOL_MONITOR_BUS_V_OFFSET, 1, (void *)&vol_mon, 2); +#endif if (ret) { printf("VID: failed to read core voltage\n"); return ret; @@ -250,7 +283,7 @@ static int adjust_vdd(ulong vdd_override) unsigned voltage; }; - ret = select_i2c_ch_pca9547(I2C_MUX_CH_VOL_MONITOR); + ret = select_i2c_ch_pca9547(I2C_MUX_CH_VOL_MONITOR, 0); if (ret) { debug("VID: I2c failed to switch channel\n"); ret = -1; @@ -348,7 +381,7 @@ int config_frontside_crossbar_vsc3316(void) u32 srds_prtcl_s1, srds_prtcl_s2; int ret; - ret = select_i2c_ch_pca9547(I2C_MUX_CH_VSC3316_FS); + ret = select_i2c_ch_pca9547(I2C_MUX_CH_VSC3316_FS, 0); if (ret) return ret; @@ -567,7 +600,7 @@ int board_early_init_r(void) /* Configure board SERDES ports crossbar */ config_frontside_crossbar_vsc3316(); config_backside_crossbar_mux(); - select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0); return 0; } @@ -732,11 +765,11 @@ void board_detail(void) } /* Voltage secion */ - if (!select_i2c_ch_pca9547(I2C_MUX_CH_VOL_MONITOR)) { + if (!select_i2c_ch_pca9547(I2C_MUX_CH_VOL_MONITOR, 0)) { vdd = read_voltage(); if (vdd > 0) printf("Core voltage= %d mV\n", vdd); - select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0); } printf("XVDD = 1.%d V\n", ((brdcfg[8] & 0xf) - 4) * 5 + 25); -- cgit From 8e4be6dfb755bda97bea4d4b211c4aaabe08b730 Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Fri, 1 May 2020 20:04:19 +0800 Subject: dm: powerpc: T2080/T2081: add i2c DM support This supports i2c DM for SoC T2080/T2081 Signed-off-by: Biwen Li Reviewed-by: Priyanka Jain --- board/freescale/t208xqds/t208xqds.c | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-) (limited to 'board') diff --git a/board/freescale/t208xqds/t208xqds.c b/board/freescale/t208xqds/t208xqds.c index 79cc1543f9..9100401022 100644 --- a/board/freescale/t208xqds/t208xqds.c +++ b/board/freescale/t208xqds/t208xqds.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2009-2013 Freescale Semiconductor, Inc. + * Copyright 2020 NXP */ #include @@ -75,11 +76,23 @@ int checkboard(void) return 0; } -int select_i2c_ch_pca9547(u8 ch) +int select_i2c_ch_pca9547(u8 ch, int bus_num) { int ret; +#ifdef CONFIG_DM_I2C + struct udevice *dev; + + ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI, 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", __func__, + bus_num); + return ret; + } + ret = dm_i2c_write(dev, 0, &ch, 1); +#else ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); +#endif if (ret) { puts("PCA: failed to select proper channel\n"); return ret; @@ -90,7 +103,7 @@ int select_i2c_ch_pca9547(u8 ch) int i2c_multiplexer_select_vid_channel(u8 channel) { - return select_i2c_ch_pca9547(channel); + return select_i2c_ch_pca9547(channel, 0); } int brd_mux_lane_to_slot(void) @@ -368,7 +381,7 @@ int board_early_init_r(void) printf("Warning: Adjusting core voltage failed.\n"); brd_mux_lane_to_slot(); - select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0); return 0; } -- cgit From d2e3f7c608b86fbbc027e46acb431abfba304333 Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Fri, 1 May 2020 20:04:21 +0800 Subject: dm: powerpc: T1040/T1042: add i2c DM support This supports i2c DM for SoC T1040/T1042 Signed-off-by: Biwen Li Reviewed-by: Priyanka Jain --- board/freescale/t1040qds/diu.c | 5 +++-- board/freescale/t1040qds/t1040qds.c | 18 ++++++++++++++++-- board/freescale/t1040qds/t1040qds.h | 3 ++- 3 files changed, 21 insertions(+), 5 deletions(-) (limited to 'board') diff --git a/board/freescale/t1040qds/diu.c b/board/freescale/t1040qds/diu.c index ab9e922a92..0b1aeed69e 100644 --- a/board/freescale/t1040qds/diu.c +++ b/board/freescale/t1040qds/diu.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2020 NXP * Author: Priyanka Jain */ @@ -48,7 +49,7 @@ void diu_set_pixel_clock(unsigned int pixclock) /* Program HDMI encoder */ /* Switch channel to DIU */ - select_i2c_ch_pca9547(I2C_MUX_CH_DIU); + select_i2c_ch_pca9547(I2C_MUX_CH_DIU, 0); /* Set dispaly encoder */ ret = diu_set_dvi_encoder(temp); @@ -58,7 +59,7 @@ void diu_set_pixel_clock(unsigned int pixclock) } /* Switch channel to default */ - select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0); /* Program pixel clock */ out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR, diff --git a/board/freescale/t1040qds/t1040qds.c b/board/freescale/t1040qds/t1040qds.c index 92dd9237ec..9e253fdec2 100644 --- a/board/freescale/t1040qds/t1040qds.c +++ b/board/freescale/t1040qds/t1040qds.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2013 Freescale Semiconductor, Inc. + * Copyright 2020 NXP */ #include @@ -79,11 +80,24 @@ int checkboard(void) return 0; } -int select_i2c_ch_pca9547(u8 ch) +int select_i2c_ch_pca9547(u8 ch, int bus_num) { int ret; +#ifdef CONFIG_DM_I2C + struct udevice *dev; + + ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI, 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", __func__, + bus_num); + return ret; + } + + ret = dm_i2c_write(dev, 0, &ch, 1); +#else ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); +#endif if (ret) { puts("PCA: failed to select proper channel\n"); return ret; @@ -154,7 +168,7 @@ int board_early_init_r(void) MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, flash_esel, BOOKE_PAGESZ_256M, 1); #endif - select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0); return 0; } diff --git a/board/freescale/t1040qds/t1040qds.h b/board/freescale/t1040qds/t1040qds.h index d2f0203f17..781bcdefc9 100644 --- a/board/freescale/t1040qds/t1040qds.h +++ b/board/freescale/t1040qds/t1040qds.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2013 Freescale Semiconductor, Inc. + * Copyright 2020 NXP */ #ifndef __T1040_QDS_H__ @@ -8,6 +9,6 @@ void fdt_fixup_board_enet(void *blob); void pci_of_setup(void *blob, bd_t *bd); -int select_i2c_ch_pca9547(u8 ch); +int select_i2c_ch_pca9547(u8 ch, int bus_bum); #endif -- cgit From 177edd82b2dad578b2df212189ff94d6b9f47b61 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Fri, 1 May 2020 19:06:27 +0800 Subject: powerpc: P1010RDB: Compile legacy PCIe routines conditionally Compile the legacy PCIe initialization reoutines for P1010RDB boards only when DM_PCI is not enabled. Signed-off-by: Hou Zhiqiang Reviewed-by: Priyanka Jain --- board/freescale/p1010rdb/p1010rdb.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'board') diff --git a/board/freescale/p1010rdb/p1010rdb.c b/board/freescale/p1010rdb/p1010rdb.c index 65ac47263e..314646d4ff 100644 --- a/board/freescale/p1010rdb/p1010rdb.c +++ b/board/freescale/p1010rdb/p1010rdb.c @@ -125,7 +125,7 @@ int board_early_init_r(void) return 0; } -#ifdef CONFIG_PCI +#if defined(CONFIG_PCI) && !defined(CONFIG_DM_PCI) void pci_init_board(void) { fsl_pcie_init_board(0); @@ -611,7 +611,7 @@ int ft_board_setup(void *blob, bd_t *bd) base = env_get_bootm_low(); size = env_get_bootm_size(); -#if defined(CONFIG_PCI) +#if defined(CONFIG_PCI) && !defined(CONFIG_DM_PCI) FT_FSL_PCI_SETUP; #endif -- cgit From 538437ed39e01b7ecfa79669982fe7db51fb2e1b Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 1 May 2020 07:36:10 -0600 Subject: x86: Add a 64-bit 'coreboot64' build Coreboot is a first-stage bootloader mostly used on x86 devices as an alternative to UEFI. Coreboot runs in 32-bit mode. U-Boot currently supports booting from coreboot as a second-stage bootloader, also in 32-bit mode. However it is useful to be able to run U-Boot in 64-bit mode. To do this we can have a 32-bit SPL which switches over the CPU and jumps to a 64-bit U-Boot proper. Add a new 'coreboot64' board for running 64-bit U-Boot from coreboot. This uses binman to create an image with a 32-bit SPL and a 64-bit U-Boot. This allows running 64-bit EFI images on x86, for example, without needing a native U-Boot port for a board. Signed-off-by: Simon Glass Reviewed-by: Bin Meng Tested-by: Bin Meng --- board/coreboot/coreboot/MAINTAINERS | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'board') diff --git a/board/coreboot/coreboot/MAINTAINERS b/board/coreboot/coreboot/MAINTAINERS index 188906b080..a05673bb0b 100644 --- a/board/coreboot/coreboot/MAINTAINERS +++ b/board/coreboot/coreboot/MAINTAINERS @@ -4,3 +4,10 @@ S: Maintained F: board/coreboot/coreboot/ F: include/configs/chromebook_link.h F: configs/coreboot_defconfig + +COREBOOT64 BOARD +M: Simon Glass +S: Maintained +F: board/coreboot/coreboot/ +F: include/configs/chromebook_link.h +F: configs/coreboot64_defconfig -- cgit From b3270e91385111facdb7c79c30f2943d93e63280 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Mon, 27 Apr 2020 19:18:01 +0100 Subject: arm: juno: Enable OF_CONTROL The Arm Juno board was still somewhat stuck in "hardcoded land", even though there are stable DTs around, and one happens to actually be on the memory mapped NOR flash. Enable the configuration options to let the board use OF_CONTROL, and add a routine to find the address of the DTB partition in NOR flash, to use that for U-Boot's own purposes. This can also passed on via $fdtcontroladdr to any kernel or EFI application, removing the need to actually load a device tree. Since the existing "afs" command and its flash routines require flash_init() to be called before being usable, and this is done much later in the boot process, we introduce a stripped-down partition finder routine in vexpress64.c, to scan the NOR flash partitions for the DT partition. This location is then used for U-Boot to find and probe devices. The name of the partition can be configured, if needed, but defaults to "board.dtb", which is used by Linaro's firmware image provided. Signed-off-by: Andre Przywara Reviewed-by: Linus Walleij Reviewed-by: Simon Glass --- board/armltd/vexpress64/Kconfig | 7 +++++ board/armltd/vexpress64/vexpress64.c | 57 ++++++++++++++++++++++++++++++++++++ 2 files changed, 64 insertions(+) (limited to 'board') diff --git a/board/armltd/vexpress64/Kconfig b/board/armltd/vexpress64/Kconfig index 9014418433..1d13f542e6 100644 --- a/board/armltd/vexpress64/Kconfig +++ b/board/armltd/vexpress64/Kconfig @@ -9,4 +9,11 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "vexpress_aemv8a" +config JUNO_DTB_PART + string "NOR flash partition holding DTB" + default "board.dtb" + help + The ARM partition name in the NOR flash memory holding the + device tree blob to configure U-Boot. + endif diff --git a/board/armltd/vexpress64/vexpress64.c b/board/armltd/vexpress64/vexpress64.c index dd0ebdd303..ba49b32e58 100644 --- a/board/armltd/vexpress64/vexpress64.c +++ b/board/armltd/vexpress64/vexpress64.c @@ -82,6 +82,63 @@ int dram_init_banksize(void) return 0; } +#ifdef CONFIG_OF_BOARD +#define JUNO_FLASH_SEC_SIZE (256 * 1024) +static phys_addr_t find_dtb_in_nor_flash(const char *partname) +{ + phys_addr_t sector = CONFIG_SYS_FLASH_BASE; + int i; + + for (i = 0; + i < CONFIG_SYS_MAX_FLASH_SECT; + i++, sector += JUNO_FLASH_SEC_SIZE) { + int len = strlen(partname) + 1; + int offs; + phys_addr_t imginfo; + u32 reg; + + reg = readl(sector + JUNO_FLASH_SEC_SIZE - 0x04); + /* This makes up the string "HSLFTOOF" flash footer */ + if (reg != 0x464F4F54U) + continue; + reg = readl(sector + JUNO_FLASH_SEC_SIZE - 0x08); + if (reg != 0x464C5348U) + continue; + + for (offs = 0; offs < 32; offs += 4, len -= 4) { + reg = readl(sector + JUNO_FLASH_SEC_SIZE - 0x30 + offs); + if (strncmp(partname + offs, (char *)®, + len > 4 ? 4 : len)) + break; + + if (len > 4) + continue; + + reg = readl(sector + JUNO_FLASH_SEC_SIZE - 0x10); + imginfo = sector + JUNO_FLASH_SEC_SIZE - 0x30 - reg; + reg = readl(imginfo + 0x54); + + return CONFIG_SYS_FLASH_BASE + + reg * JUNO_FLASH_SEC_SIZE; + } + } + + printf("No DTB found\n"); + + return ~0; +} + +void *board_fdt_blob_setup(void) +{ + phys_addr_t fdt_rom_addr = find_dtb_in_nor_flash(CONFIG_JUNO_DTB_PART); + + if (fdt_rom_addr == ~0UL) + return NULL; + + return (void *)fdt_rom_addr; +} +#endif + /* * Board specific reset that is system reset. */ -- cgit From be0d09695d2bd689a3804eab82658d77eb495681 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Mon, 27 Apr 2020 19:18:02 +0100 Subject: arm: juno: Use PSCI based reset So far the Juno board wasn't implementing reset. Let's just use the already existing PSCI_RESET based method to avoid any extra code. Signed-off-by: Andre Przywara Acked-by: Liviu Dudau Reviewed-by: Simon Glass --- board/armltd/vexpress64/vexpress64.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'board') diff --git a/board/armltd/vexpress64/vexpress64.c b/board/armltd/vexpress64/vexpress64.c index ba49b32e58..5c7a8f55f0 100644 --- a/board/armltd/vexpress64/vexpress64.c +++ b/board/armltd/vexpress64/vexpress64.c @@ -139,9 +139,7 @@ void *board_fdt_blob_setup(void) } #endif -/* - * Board specific reset that is system reset. - */ +/* Actual reset is done via PSCI. */ void reset_cpu(ulong addr) { } -- cgit From 702de89cc6a34c1c23dd3d987b0472b2cecdb63c Mon Sep 17 00:00:00 2001 From: Ashok Reddy Soma Date: Mon, 4 May 2020 15:26:21 +0200 Subject: treewide: mem: Move mtest related defines to Kconfig Move below defines which are used by mtest utility to Kconfig. CONFIG_SYS_MEMTEST_START CONFIG_SYS_MEMTEST_END Signed-off-by: Ashok Reddy Soma Signed-off-by: Michal Simek [trini: Fix kmcoge5ne board, re-run migration as well] Signed-off-by: Tom Rini --- board/keymile/km83xx/km83xx.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'board') diff --git a/board/keymile/km83xx/km83xx.c b/board/keymile/km83xx/km83xx.c index 23bbdcccac..8f7e7f05d8 100644 --- a/board/keymile/km83xx/km83xx.c +++ b/board/keymile/km83xx/km83xx.c @@ -330,8 +330,12 @@ void post_word_store(ulong value) int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset) { - *vstart = CONFIG_SYS_MEMTEST_START; - *size = CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START; + /* + * These match CONFIG_SYS_MEMTEST_START and + * (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) + */ + *vstart = 0x00100000; + *size = 0xe00000; debug("arch_memory_test_prepare 0x%08X 0x%08X\n", *vstart, *size); return 0; -- cgit