From 1667013ddfa95007c242d7772fb38e3e3bf72b48 Mon Sep 17 00:00:00 2001 From: Paul Gortmaker Date: Fri, 16 Dec 2011 17:31:53 -0500 Subject: MPC85xxCDS: Fix missing LCRR_DBYP bits for 66-133MHz LBC These boards were meaning to deploy this value: #define LCRR_DBYP 0x80000000 but were missing a zero, and hence toggling a bit that lands in an area marked as reserved in the 8548 reference manual. According to the documentation, LCRR_DBYP should be used as: PLL bypass. This bit should be set when using low bus clock frequencies if the PLL is unable to lock. When in PLL bypass mode, incoming data is captured in the middle of the bus clock cycle. It is recommended that PLL bypass mode be used at frequencies of 83 MHz or less. So the impact would most likely be undefined behaviour for LBC peripherals on boards that were running below 83MHz LBC. Looking at the actual u-boot code, the missing DBYP bit was meant to be deployed as follows: Between 66 and 133, the DLL is enabled with an override workaround. In the future, we'll convert all boards to use the symbolic DBYP constant to avoid these "count the zeros" problems, but for now, just fix the impacted boards. Signed-off-by: Paul Gortmaker Signed-off-by: Kumar Gala --- board/freescale/mpc8541cds/mpc8541cds.c | 2 +- board/freescale/mpc8555cds/mpc8555cds.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'board') diff --git a/board/freescale/mpc8541cds/mpc8541cds.c b/board/freescale/mpc8541cds/mpc8541cds.c index d127137ddb..532d32ac7c 100644 --- a/board/freescale/mpc8541cds/mpc8541cds.c +++ b/board/freescale/mpc8541cds/mpc8541cds.c @@ -275,7 +275,7 @@ local_bus_init(void) lbc->lcrr &= (~0x80000000); /* DLL Enabled */ } else { - lbc->lcrr &= (~0x8000000); /* DLL Enabled */ + lbc->lcrr &= (~0x80000000); /* DLL Enabled */ udelay(200); /* diff --git a/board/freescale/mpc8555cds/mpc8555cds.c b/board/freescale/mpc8555cds/mpc8555cds.c index 48ede9840f..3361614de5 100644 --- a/board/freescale/mpc8555cds/mpc8555cds.c +++ b/board/freescale/mpc8555cds/mpc8555cds.c @@ -273,7 +273,7 @@ local_bus_init(void) lbc->lcrr &= (~0x80000000); /* DLL Enabled */ } else { - lbc->lcrr &= (~0x8000000); /* DLL Enabled */ + lbc->lcrr &= (~0x80000000); /* DLL Enabled */ udelay(200); /* -- cgit From 3fd673cf363bc86ed42eff713d4e3506720e91a2 Mon Sep 17 00:00:00 2001 From: Paul Gortmaker Date: Fri, 30 Dec 2011 23:53:07 -0500 Subject: sbc8548: relocate 64MB user flash to sane boundary The current situation has the 64MB user flash at an awkward alignment; shifted back from 0xfc00_0000 by 8M, to leave an 8MB hole for the soldered on boot flash @ EOM. But to switch to optionally supporting booting off the 64MB flash, the 64MB will then be mapped at the sane address of 0xfc00_0000. This leads to awkward things when programming the 64MB flash prior to transitioning to it -- i.e. even though the chip spans from 0xfb80_0000 to 0xff7f_ffff, you would have to program a u-boot image into the two sectors from 0xfbf0_0000 --> 0xfbff_ffff so that it was in the right place when JP12/SW2.8 were switched to make the 64MB on /CS0. (i.e. the chip is only looking at the bits in mask 0x3ff_ffff) We also have to have three TLB entries responsible for dealing with mapping the 64MB flash due to this 8MB of misalignment. In the end, there is address space from 0xec00_0000 to 0xefff_ffff where we can map it, and then the transition from booting from one config to the other will be a simple 0xec --> 0xfc mapping. Plus we can toss out a TLB entry. Note that TLB0 is kept at 64MB and not shrunk down to the 8MB boot flash; this means we won't have to change it when the alternate config uses the full 64MB for booting, in TLB0. Signed-off-by: Paul Gortmaker Signed-off-by: Kumar Gala --- board/sbc8548/law.c | 3 ++- board/sbc8548/tlb.c | 23 ++++++++--------------- 2 files changed, 10 insertions(+), 16 deletions(-) (limited to 'board') diff --git a/board/sbc8548/law.c b/board/sbc8548/law.c index 5fa9db02f5..febb6829c3 100644 --- a/board/sbc8548/law.c +++ b/board/sbc8548/law.c @@ -36,9 +36,9 @@ * 0xe000_0000 0xe000_ffff CCSR 1M * 0xe200_0000 0xe27f_ffff PCI1 IO 8M * 0xe280_0000 0xe2ff_ffff PCIe IO 8M + * 0xec00_0000 0xefff_ffff FLASH (2nd bank) 64M * 0xf000_0000 0xf7ff_ffff SDRAM 128M * 0xf8b0_0000 0xf80f_ffff EEPROM 1M - * 0xfb80_0000 0xff7f_ffff FLASH (2nd bank) 64M * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M * * Notes: @@ -47,6 +47,7 @@ */ struct law_entry law_table[] = { + SET_LAW(CONFIG_SYS_ALT_FLASH, LAW_SIZE_64M, LAW_TRGT_IF_LBC), #ifndef CONFIG_SPD_EEPROM SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR), #endif diff --git a/board/sbc8548/tlb.c b/board/sbc8548/tlb.c index bb4c05210c..e9cedc7c0d 100644 --- a/board/sbc8548/tlb.c +++ b/board/sbc8548/tlb.c @@ -46,12 +46,14 @@ struct fsl_e_tlb_entry tlb_table[] = { /* * TLB 0: 64M Non-cacheable, guarded - * 0xfc000000 56M 8MB -> 64MB of user flash + * 0xfc000000 56M unused * 0xff800000 8M boot FLASH + * .... or .... + * 0xfc000000 64M user flash + * * Out of reset this entry is only 4K. */ - SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH + 0x800000, - CONFIG_SYS_ALT_FLASH + 0x800000, + SET_TLB_ENTRY(1, 0xfc000000, 0xfc000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 0, BOOKE_PAGESZ_64M, 1), @@ -103,21 +105,12 @@ struct fsl_e_tlb_entry tlb_table[] = { 0, 5, BOOKE_PAGESZ_16M, 1), /* - * TLB 6: 4M Non-cacheable, guarded - * 0xfb800000 4M 1st 4MB block of 64MB user FLASH + * TLB 6: 64M Non-cacheable, guarded + * 0xec000000 64M 64MB user FLASH */ SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH, CONFIG_SYS_ALT_FLASH, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 6, BOOKE_PAGESZ_4M, 1), - - /* - * TLB 7: 4M Non-cacheable, guarded - * 0xfbc00000 4M 2nd 4MB block of 64MB user FLASH - */ - SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH + 0x400000, - CONFIG_SYS_ALT_FLASH + 0x400000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 7, BOOKE_PAGESZ_4M, 1), + 0, 6, BOOKE_PAGESZ_64M, 1), }; -- cgit From f0aec4ea3301f7db3a691ec0cbb5230e99cceb34 Mon Sep 17 00:00:00 2001 From: Paul Gortmaker Date: Fri, 30 Dec 2011 23:53:08 -0500 Subject: sbc8548: enable ability to boot from alternate flash This board has an 8MB soldered on flash, and a 64MB SODIMM flash module. Normally the board boots from the 8MB flash, but the hardware can be configured for booting from the 64MB flash as well by swapping CS0 and CS6. This can be handy for recovery purposes, or for supporting u-boot and VxBoot at the same time. To support this in u-boot, we need to have different BR0/OR0 and BR6/OR6 settings in place for when the board is configured in this way, and a different TEXT_BASE needs to be used due to the larger sector size of the 64MB flash module. We introduce the suffix _8M and _64M for the BR0/BR6 and the OR0/OR6 values so it is clear which is being used to map what specific device. The larger sector size (512k) of the alternate flash needs a larger malloc pool, otherwise you'll get failures when running saveenv, so bump it up accordingly. Signed-off-by: Paul Gortmaker Signed-off-by: Kumar Gala --- board/sbc8548/law.c | 8 ++++++++ board/sbc8548/sbc8548.c | 2 +- board/sbc8548/tlb.c | 19 +++++++++++++++++++ 3 files changed, 28 insertions(+), 1 deletion(-) (limited to 'board') diff --git a/board/sbc8548/law.c b/board/sbc8548/law.c index febb6829c3..c263191c3d 100644 --- a/board/sbc8548/law.c +++ b/board/sbc8548/law.c @@ -41,13 +41,21 @@ * 0xf8b0_0000 0xf80f_ffff EEPROM 1M * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M * + * If swapped CS0/CS6 via JP12+SW2.8: + * 0xef80_0000 0xefff_ffff FLASH (2nd bank) 8M + * 0xfc00_0000 0xffff_ffff FLASH (boot bank) 64M + * * Notes: * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. * If flash is 8M at default position (last 8M), no LAW needed. */ struct law_entry law_table[] = { +#ifdef CONFIG_SYS_ALT_BOOT + SET_LAW(CONFIG_SYS_ALT_FLASH, LAW_SIZE_8M, LAW_TRGT_IF_LBC), +#else SET_LAW(CONFIG_SYS_ALT_FLASH, LAW_SIZE_64M, LAW_TRGT_IF_LBC), +#endif #ifndef CONFIG_SPD_EEPROM SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR), #endif diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c index 26095a5455..63d504d61d 100644 --- a/board/sbc8548/sbc8548.c +++ b/board/sbc8548/sbc8548.c @@ -113,7 +113,7 @@ void lbc_sdram_init(void) puts(" SDRAM: "); - print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); + print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); /* * Setup SDRAM Base and Option Registers diff --git a/board/sbc8548/tlb.c b/board/sbc8548/tlb.c index e9cedc7c0d..4bf72147ba 100644 --- a/board/sbc8548/tlb.c +++ b/board/sbc8548/tlb.c @@ -104,6 +104,7 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 5, BOOKE_PAGESZ_16M, 1), +#ifndef CONFIG_SYS_ALT_BOOT /* * TLB 6: 64M Non-cacheable, guarded * 0xec000000 64M 64MB user FLASH @@ -111,6 +112,24 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH, CONFIG_SYS_ALT_FLASH, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 6, BOOKE_PAGESZ_64M, 1), +#else + /* + * TLB 6: 4M Non-cacheable, guarded + * 0xef800000 4M 1st 1/2 8MB soldered FLASH + */ + SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH, CONFIG_SYS_ALT_FLASH, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 6, BOOKE_PAGESZ_4M, 1), + + /* + * TLB 7: 4M Non-cacheable, guarded + * 0xefc00000 4M 2nd half 8MB soldered FLASH + */ + SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH + 0x400000, + CONFIG_SYS_ALT_FLASH + 0x400000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 7, BOOKE_PAGESZ_4M, 1), +#endif }; -- cgit From 5f4c6f0db930646e9ca3b479b5fe9b8d2691fa77 Mon Sep 17 00:00:00 2001 From: Paul Gortmaker Date: Fri, 30 Dec 2011 23:53:09 -0500 Subject: sbc8548: Fix LBC SDRAM initialization settings These were cloned from the mpc8548cds platform which has a different memory layout (1/2 the size). Set the values by comparing to the register file for the board used during JTAG init sequence: LSDMR1 0x2863B727 /* PCHALL */ LSDMR2 0x0863B727 /* NORMAL */ LSDMR3 0x1863B727 /* MRW */ LSDMR4 0x4063B727 /* RFEN */ This differs from what was there already in that the RFEN is not bundled in all four steps implicitly, but issued once as the final step. The other difference seen when comparing vs. the register file init, is that since the memory is split across /CS3 and /CS4, the dummy writes need to go to 0xf000_0000 _and_ to 0xf400_0000. We also rewrite the final LBC SDRAM inits as macros, as there is no real need for them to be a local variable that is modified on the fly at runtime. Signed-off-by: Paul Gortmaker Signed-off-by: Kumar Gala --- board/sbc8548/sbc8548.c | 29 ++++++++++++++++------------- 1 file changed, 16 insertions(+), 13 deletions(-) (limited to 'board') diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c index 63d504d61d..96554b2cdc 100644 --- a/board/sbc8548/sbc8548.c +++ b/board/sbc8548/sbc8548.c @@ -107,13 +107,14 @@ void lbc_sdram_init(void) #if defined(CONFIG_SYS_LBC_SDRAM_SIZE) uint idx; + const unsigned long size = CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024; volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; - uint lsdmr_common; + uint *sdram_addr2 = (uint *)(CONFIG_SYS_LBC_SDRAM_BASE + size/2); puts(" SDRAM: "); - print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); + print_size(size, "\n"); /* * Setup SDRAM Base and Option Registers @@ -130,48 +131,50 @@ void lbc_sdram_init(void) out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR); asm("msync"); - /* - * MPC8548 uses "new" 15-16 style addressing. - */ - lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON; - lsdmr_common |= LSDMR_BSMA1516; - /* * Issue PRECHARGE ALL command. */ - out_be32(&lbc->lsdmr, lsdmr_common | LSDMR_OP_PCHALL); + out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_PCHALL); asm("sync;msync"); *sdram_addr = 0xff; ppcDcbf((unsigned long) sdram_addr); + *sdram_addr2 = 0xff; + ppcDcbf((unsigned long) sdram_addr2); udelay(100); /* * Issue 8 AUTO REFRESH commands. */ for (idx = 0; idx < 8; idx++) { - out_be32(&lbc->lsdmr, lsdmr_common | LSDMR_OP_ARFRSH); + out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_ARFRSH); asm("sync;msync"); *sdram_addr = 0xff; ppcDcbf((unsigned long) sdram_addr); + *sdram_addr2 = 0xff; + ppcDcbf((unsigned long) sdram_addr2); udelay(100); } /* * Issue 8 MODE-set command. */ - out_be32(&lbc->lsdmr, lsdmr_common | LSDMR_OP_MRW); + out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_MRW); asm("sync;msync"); *sdram_addr = 0xff; ppcDcbf((unsigned long) sdram_addr); + *sdram_addr2 = 0xff; + ppcDcbf((unsigned long) sdram_addr2); udelay(100); /* - * Issue NORMAL OP command. + * Issue RFEN command. */ - out_be32(&lbc->lsdmr, lsdmr_common | LSDMR_OP_NORMAL); + out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_RFEN); asm("sync;msync"); *sdram_addr = 0xff; ppcDcbf((unsigned long) sdram_addr); + *sdram_addr2 = 0xff; + ppcDcbf((unsigned long) sdram_addr2); udelay(200); /* Overkill. Must wait > 200 bus cycles */ #endif /* enable SDRAM init */ -- cgit From 7e44f2b710db09a1b02e55246e0915732cc4775e Mon Sep 17 00:00:00 2001 From: Paul Gortmaker Date: Fri, 30 Dec 2011 23:53:10 -0500 Subject: sbc8548: Make enabling SPD RAM configuration work Previously, SPD configuration of RAM was non functional on this board. Now that the root cause is known (an i2c address conflict), there is a simple end-user workaround - remove the old slower local bus 128MB module and then SPD detection on the main DDR2 memory module works fine. We make the enablement of the LBC SDRAM support conditional on being not SPD enabled. We can revisit this dependency as the hardware workaround becomes available. Turning off LBC SDRAM support revealed a couple implict dependencies in the tlb/law code that always expected an LBC SDRAM address. This has been tested with the default 256MB module, a 512MB a 1GB and a 2GB, of varying speeds, and the SPD autoconfiguration worked fine in all cases. The default configuration remains to go with the hard coded DDR config, so the default build will continue to work on boards where people don't bother to read the docs. But the advantage of going to the SPD config is that even the small default module gets configured for CL3 instead of CL4. Signed-off-by: Paul Gortmaker Signed-off-by: Kumar Gala --- board/sbc8548/law.c | 5 +++++ board/sbc8548/tlb.c | 2 ++ 2 files changed, 7 insertions(+) (limited to 'board') diff --git a/board/sbc8548/law.c b/board/sbc8548/law.c index c263191c3d..322af76d65 100644 --- a/board/sbc8548/law.c +++ b/board/sbc8548/law.c @@ -59,8 +59,13 @@ struct law_entry law_table[] = { #ifndef CONFIG_SPD_EEPROM SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR), #endif +#ifdef CONFIG_SYS_LBC_SDRAM_BASE /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), +#else + /* LBC window - maps 128M 0xf8000000 -> 0xffffffff */ + SET_LAW(CONFIG_SYS_EPLD_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC), +#endif }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/sbc8548/tlb.c b/board/sbc8548/tlb.c index 4bf72147ba..af927f165b 100644 --- a/board/sbc8548/tlb.c +++ b/board/sbc8548/tlb.c @@ -76,6 +76,7 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 2, BOOKE_PAGESZ_64M, 1), +#ifdef CONFIG_SYS_LBC_SDRAM_BASE /* * TLB 3: 64M Cacheable, non-guarded * 0xf0000000 64M LBC SDRAM First half @@ -92,6 +93,7 @@ struct fsl_e_tlb_entry tlb_table[] = { CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 4, BOOKE_PAGESZ_64M, 1), +#endif /* * TLB 5: 16M Cacheable, non-guarded -- cgit From 2a6b3b74d85cff3f9a76edd09a7b2e8e25bb4eb4 Mon Sep 17 00:00:00 2001 From: Paul Gortmaker Date: Fri, 30 Dec 2011 23:53:11 -0500 Subject: sbc8548: relocate fixed ddr init code to ddr.c file Nothing to see here, just a relocation of the fixed ddr init sequence to live in the actual ddr.c file itself. Signed-off-by: Paul Gortmaker Signed-off-by: Kumar Gala --- board/sbc8548/ddr.c | 48 ++++++++++++++++++++++++++++++++++++++++++++++++ board/sbc8548/sbc8548.c | 44 -------------------------------------------- 2 files changed, 48 insertions(+), 44 deletions(-) (limited to 'board') diff --git a/board/sbc8548/ddr.c b/board/sbc8548/ddr.c index 996ffe206d..0d9a1ba62b 100644 --- a/board/sbc8548/ddr.c +++ b/board/sbc8548/ddr.c @@ -54,3 +54,51 @@ void fsl_ddr_board_options(memctl_options_t *popts, */ popts->half_strength_driver_enable = 0; } + +#if !defined(CONFIG_SPD_EEPROM) +/* + * fixed_sdram init -- doesn't use serial presence detect. + * Assumes 256MB DDR2 SDRAM SODIMM, without ECC, running at DDR400 speed. + */ +phys_size_t fixed_sdram(void) +{ + volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); + + out_be32(&ddr->cs0_bnds, 0x0000007f); + out_be32(&ddr->cs1_bnds, 0x008000ff); + out_be32(&ddr->cs2_bnds, 0x00000000); + out_be32(&ddr->cs3_bnds, 0x00000000); + + out_be32(&ddr->cs0_config, 0x80010101); + out_be32(&ddr->cs1_config, 0x80010101); + out_be32(&ddr->cs2_config, 0x00000000); + out_be32(&ddr->cs3_config, 0x00000000); + + out_be32(&ddr->timing_cfg_3, 0x00000000); + out_be32(&ddr->timing_cfg_0, 0x00220802); + out_be32(&ddr->timing_cfg_1, 0x38377322); + out_be32(&ddr->timing_cfg_2, 0x0fa044C7); + + out_be32(&ddr->sdram_cfg, 0x4300C000); + out_be32(&ddr->sdram_cfg_2, 0x24401000); + + out_be32(&ddr->sdram_mode, 0x23C00542); + out_be32(&ddr->sdram_mode_2, 0x00000000); + + out_be32(&ddr->sdram_interval, 0x05080100); + out_be32(&ddr->sdram_md_cntl, 0x00000000); + out_be32(&ddr->sdram_data_init, 0x00000000); + out_be32(&ddr->sdram_clk_cntl, 0x03800000); + asm("sync;isync;msync"); + udelay(500); + + #ifdef CONFIG_DDR_ECC + /* Enable ECC checking */ + out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL | 0x20000000); + #else + out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL); + #endif + + return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; +} +#endif diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c index 96554b2cdc..d1ef3bee50 100644 --- a/board/sbc8548/sbc8548.c +++ b/board/sbc8548/sbc8548.c @@ -219,50 +219,6 @@ testdram(void) } #endif -#if !defined(CONFIG_SPD_EEPROM) -#define CONFIG_SYS_DDR_CONTROL 0xc300c000 -/************************************************************************* - * fixed_sdram init -- doesn't use serial presence detect. - * assumes 256MB DDR2 SDRAM SODIMM, without ECC, running at DDR400 speed. - ************************************************************************/ -phys_size_t fixed_sdram(void) -{ - volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); - - out_be32(&ddr->cs0_bnds, 0x0000007f); - out_be32(&ddr->cs1_bnds, 0x008000ff); - out_be32(&ddr->cs2_bnds, 0x00000000); - out_be32(&ddr->cs3_bnds, 0x00000000); - out_be32(&ddr->cs0_config, 0x80010101); - out_be32(&ddr->cs1_config, 0x80010101); - out_be32(&ddr->cs2_config, 0x00000000); - out_be32(&ddr->cs3_config, 0x00000000); - out_be32(&ddr->timing_cfg_3, 0x00000000); - out_be32(&ddr->timing_cfg_0, 0x00220802); - out_be32(&ddr->timing_cfg_1, 0x38377322); - out_be32(&ddr->timing_cfg_2, 0x0fa044C7); - out_be32(&ddr->sdram_cfg, 0x4300C000); - out_be32(&ddr->sdram_cfg_2, 0x24401000); - out_be32(&ddr->sdram_mode, 0x23C00542); - out_be32(&ddr->sdram_mode_2, 0x00000000); - out_be32(&ddr->sdram_interval, 0x05080100); - out_be32(&ddr->sdram_md_cntl, 0x00000000); - out_be32(&ddr->sdram_data_init, 0x00000000); - out_be32(&ddr->sdram_clk_cntl, 0x03800000); - asm("sync;isync;msync"); - udelay(500); - - #if defined (CONFIG_DDR_ECC) - /* Enable ECC checking */ - out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL | 0x20000000); - #else - out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL); - #endif - - return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; -} -#endif - #ifdef CONFIG_PCI1 static struct pci_controller pci1_hose; #endif /* CONFIG_PCI1 */ -- cgit From 3e3262bd149e21d0f5a82648218c26f2aa0e15e7 Mon Sep 17 00:00:00 2001 From: Paul Gortmaker Date: Fri, 30 Dec 2011 23:53:12 -0500 Subject: sbc8548: enable support for hardware SPD errata workaround Existing boards by default have an issue where the LBC SDRAM SPD EEPROM and the DDR2 SDRAM SPD EEPROM both land at 0x51. After the hardware modification listed in the README is made, then the DDR2 SPD EEPROM appears at 0x53. So this implements a board specific get_spd() by taking advantage of the existing weak linkage, that 1st tries reading at 0x53 and then if that fails, it falls back to the old 0x51. Since the old dependency issue of "SPD implies no LBC SDRAM" gets removed with the hardware errata fix, remove that restriction in the code, so both LBC SDRAM and SPD can be selected. Signed-off-by: Paul Gortmaker Signed-off-by: Kumar Gala --- board/sbc8548/ddr.c | 31 ++++++++++++++++++++++++++++++- 1 file changed, 30 insertions(+), 1 deletion(-) (limited to 'board') diff --git a/board/sbc8548/ddr.c b/board/sbc8548/ddr.c index 0d9a1ba62b..45ec485c50 100644 --- a/board/sbc8548/ddr.c +++ b/board/sbc8548/ddr.c @@ -7,6 +7,7 @@ */ #include +#include #include #include @@ -55,7 +56,35 @@ void fsl_ddr_board_options(memctl_options_t *popts, popts->half_strength_driver_enable = 0; } -#if !defined(CONFIG_SPD_EEPROM) +#ifdef CONFIG_SPD_EEPROM +/* + * Workaround for hardware errata. An i2c address conflict + * existed on earlier boards; the workaround moved the DDR + * SPD from 0x51 to 0x53. So we try and read 0x53 1st, and + * if that fails, then fall back to reading at 0x51. + */ +void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address) +{ + int ret; + +#ifdef ALT_SPD_EEPROM_ADDRESS + if (i2c_address == SPD_EEPROM_ADDRESS) { + ret = i2c_read(ALT_SPD_EEPROM_ADDRESS, 0, 1, (uchar *)spd, + sizeof(generic_spd_eeprom_t)); + if (ret == 0) + return; /* Good data at 0x53 */ + memset(spd, 0, sizeof(generic_spd_eeprom_t)); + } +#endif + ret = i2c_read(i2c_address, 0, 1, (uchar *)spd, + sizeof(generic_spd_eeprom_t)); + if (ret) { + printf("DDR: failed to read SPD from addr %u\n", i2c_address); + memset(spd, 0, sizeof(generic_spd_eeprom_t)); + } +} + +#else /* * fixed_sdram init -- doesn't use serial presence detect. * Assumes 256MB DDR2 SDRAM SODIMM, without ECC, running at DDR400 speed. -- cgit From e2b363ff534ad943794682c60adf9cab6e3d3192 Mon Sep 17 00:00:00 2001 From: Paul Gortmaker Date: Fri, 30 Dec 2011 23:53:13 -0500 Subject: sbc8548: Fix up local bus init to be frequency aware The code here was copied from the mpc8548cds support, and it wasn't using the CONFIG_SYS_LBC_LCRR define, and was just unconditionally setting the LCRR_EADC bit. Snooping with a hardware debugger also showed we had LCRR_DBYP set, since we were setting it based on a read of an uninitialized lcrr read via clkdiv. Borrow from the code in the tqm85xx.c support to add LBC frequency aware masking of these bits. This change will correct reliability issues associated with trying to use the 128MB of LBC 100MHz SDRAM on this board. Thanks to Keith Savage for assistance in diagnosing the root cause of this. Signed-off-by: Paul Gortmaker Signed-off-by: Kumar Gala --- board/sbc8548/sbc8548.c | 38 +++++++++++++++++++++++++++++++++++--- 1 file changed, 35 insertions(+), 3 deletions(-) (limited to 'board') diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c index d1ef3bee50..371d07695e 100644 --- a/board/sbc8548/sbc8548.c +++ b/board/sbc8548/sbc8548.c @@ -76,11 +76,15 @@ local_bus_init(void) volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; - uint clkdiv; + uint clkdiv, lbc_mhz, lcrr = CONFIG_SYS_LBC_LCRR; sys_info_t sysinfo; get_sys_info(&sysinfo); - clkdiv = (in_be32(&lbc->lcrr) & LCRR_CLKDIV) * 2; + + lbc_mhz = sysinfo.freqLocalBus / 1000000; + clkdiv = sysinfo.freqSystemBus / sysinfo.freqLocalBus; + + debug("LCRR=0x%x, CD=%d, MHz=%d\n", lcrr, clkdiv, lbc_mhz); out_be32(&gur->lbiuiplldcr1, 0x00078080); if (clkdiv == 16) { @@ -91,10 +95,38 @@ local_bus_init(void) out_be32(&gur->lbiuiplldcr0, 0x5c0f1bf0); } - setbits_be32(&lbc->lcrr, 0x00030000); + /* + * Local Bus Clock > 83.3 MHz. According to timing + * specifications set LCRR[EADC] to 2 delay cycles. + */ + if (lbc_mhz > 83) { + lcrr &= ~LCRR_EADC; + lcrr |= LCRR_EADC_2; + } + + /* + * According to MPC8548ERMAD Rev. 1.3, 13.3.1.16, 13-30 + * disable PLL bypass for Local Bus Clock > 83 MHz. + */ + if (lbc_mhz >= 66) + lcrr &= (~LCRR_DBYP); /* DLL Enabled */ + + else + lcrr |= LCRR_DBYP; /* DLL Bypass */ + out_be32(&lbc->lcrr, lcrr); asm("sync;isync;msync"); + /* + * According to MPC8548ERMAD Rev.1.3 read back LCRR + * and terminate with isync + */ + lcrr = in_be32(&lbc->lcrr); + asm ("isync;"); + + /* let DLL stabilize */ + udelay(500); + out_be32(&lbc->ltesr, 0xffffffff); /* Clear LBC error IRQs */ out_be32(&lbc->lteir, 0xffffffff); /* Enable LBC error IRQs */ } -- cgit