From 181c65b814b29a9e12f5fd034e259c891f3bbb64 Mon Sep 17 00:00:00 2001 From: Yangbo Lu Date: Thu, 16 Jan 2020 13:19:44 +0800 Subject: configs: ls1028a: use default SDHC clock divider value The SDHC clock divider value for LS1028A should be default 2, not 1. Signed-off-by: Yangbo Lu --- configs/ls1028ardb_tfa_defconfig | 1 - 1 file changed, 1 deletion(-) (limited to 'configs/ls1028ardb_tfa_defconfig') diff --git a/configs/ls1028ardb_tfa_defconfig b/configs/ls1028ardb_tfa_defconfig index 41fe40a853..6715d310fa 100644 --- a/configs/ls1028ardb_tfa_defconfig +++ b/configs/ls1028ardb_tfa_defconfig @@ -3,7 +3,6 @@ CONFIG_TARGET_LS1028ARDB=y CONFIG_TFABOOT=y CONFIG_SYS_MALLOC_F_LEN=0x6000 CONFIG_FSPI_AHB_EN_4BYTE=y -CONFIG_SYS_FSL_SDHC_CLK_DIV=1 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x500000 CONFIG_NR_DRAM_BANKS=2 -- cgit