From 4b294886d03e9989d6ff163eef04da4927f75952 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Wed, 23 Oct 2019 11:10:36 +0800 Subject: rockchip: evb-px5: defconfig: no need to reserve IRAM for SPL We use to reserve IRAM to avoid the SPL text overlap with ATF M0 code, and when we introduce the TPL, the SPL space is in DRAM, we reserve space to avoid SPL text overlap with ATF bl31. Now we decide to move ATF entry point to 0x40000 instead of 0x1000, so that the SPL can have 0x4000 as code size and no need to reserve space or relocate before loading ATF. The mainline ATF has update since: 0aad563c rockchip: Update BL31_BASE to 0x40000 Signed-off-by: Kever Yang --- configs/evb-px5_defconfig | 1 - 1 file changed, 1 deletion(-) (limited to 'configs') diff --git a/configs/evb-px5_defconfig b/configs/evb-px5_defconfig index 5a06b2a99f..1d2d8e1078 100644 --- a/configs/evb-px5_defconfig +++ b/configs/evb-px5_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_ROCKCHIP_RK3368=y -CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x40000 CONFIG_TPL_LIBCOMMON_SUPPORT=y CONFIG_TPL_LIBGENERIC_SUPPORT=y CONFIG_SPL_DRIVERS_MISC_SUPPORT=y -- cgit