From 0d4f24b70f7a979f58174f3eb271874950b551b6 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Sun, 1 Jun 2008 01:28:24 -0400 Subject: Blackfin: setup a sane default EBIU_SDBCTL for SDRAM controllers If the board config does not specify an explicit EBIU_SDBCTL value, set it up with sane values based on other configuration options. Signed-off-by: Mike Frysinger --- cpu/blackfin/initcode.c | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) (limited to 'cpu/blackfin/initcode.c') diff --git a/cpu/blackfin/initcode.c b/cpu/blackfin/initcode.c index 1b58f997dd..1352fd65db 100644 --- a/cpu/blackfin/initcode.c +++ b/cpu/blackfin/initcode.c @@ -203,6 +203,39 @@ static inline void serial_putc(char c) # define CONFIG_VR_CTL_VAL (CONFIG_VR_CTL_CLKBUF | CONFIG_VR_CTL_VLEV | CONFIG_VR_CTL_FREQ) #endif +#ifndef EBIU_RSTCTL +/* Blackfin with SDRAM */ +#ifndef CONFIG_EBIU_SDBCTL_VAL +# if CONFIG_MEM_SIZE == 16 +# define CONFIG_EBSZ_VAL EBSZ_16 +# elif CONFIG_MEM_SIZE == 32 +# define CONFIG_EBSZ_VAL EBSZ_32 +# elif CONFIG_MEM_SIZE == 64 +# define CONFIG_EBSZ_VAL EBSZ_64 +# elif CONFIG_MEM_SIZE == 128 +# define CONFIG_EBSZ_VAL EBSZ_128 +# elif CONFIG_MEM_SIZE == 256 +# define CONFIG_EBSZ_VAL EBSZ_256 +# elif CONFIG_MEM_SIZE == 512 +# define CONFIG_EBSZ_VAL EBSZ_512 +# else +# error You need to define CONFIG_EBIU_SDBCTL_VAL or CONFIG_MEM_SIZE +# endif +# if CONFIG_MEM_ADD_WDTH == 8 +# define CONFIG_EBCAW_VAL EBCAW_8 +# elif CONFIG_MEM_ADD_WDTH == 9 +# define CONFIG_EBCAW_VAL EBCAW_9 +# elif CONFIG_MEM_ADD_WDTH == 10 +# define CONFIG_EBCAW_VAL EBCAW_10 +# elif CONFIG_MEM_ADD_WDTH == 11 +# define CONFIG_EBCAW_VAL EBCAW_11 +# else +# error You need to define CONFIG_EBIU_SDBCTL_VAL or CONFIG_MEM_ADD_WDTH +# endif +# define CONFIG_EBIU_SDBCTL_VAL (CONFIG_EBCAW_VAL | CONFIG_EBSZ_VAL | EBE) +#endif +#endif + BOOTROM_CALLED_FUNC_ATTR void initcode(ADI_BOOT_DATA *bootstruct) { -- cgit