From f6eda7f80ccc13d658020268c507d7173cf2e8aa Mon Sep 17 00:00:00 2001
From: Dave Liu <daveliu@freescale.com>
Date: Wed, 25 Oct 2006 14:41:21 -0500
Subject: mpc83xx: Changed to unified mpx83xx names and added common 83xx
 changes

Incorporated the common unified variable names and the changes in preparation
for releasing mpc8360 patches.

Signed-off-by: Dave Liu <daveliu@freescale.com>
---
 cpu/mpc83xx/spd_sdram.c | 313 +++++++++++++++++++++++++++++-------------------
 1 file changed, 188 insertions(+), 125 deletions(-)

(limited to 'cpu/mpc83xx/spd_sdram.c')

diff --git a/cpu/mpc83xx/spd_sdram.c b/cpu/mpc83xx/spd_sdram.c
index 48624feca6..153848d343 100644
--- a/cpu/mpc83xx/spd_sdram.c
+++ b/cpu/mpc83xx/spd_sdram.c
@@ -1,4 +1,6 @@
 /*
+ * (C) Copyright 2006 Freescale Semiconductor, Inc.
+ *
  * (C) Copyright 2006
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
@@ -28,6 +30,10 @@
  *
  * 20050101: Eran Liberty (liberty@freescale.com)
  *           Initial file creating (porting from 85XX & 8260)
+ * 20060601: Dave Liu (daveliu@freescale.com)
+ *           DDR ECC support
+ *           unify variable names for 83xx
+ *           code cleanup
  */
 
 #include <common.h>
@@ -39,7 +45,7 @@
 
 #ifdef CONFIG_SPD_EEPROM
 
-#if defined(CONFIG_DDR_ECC)
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
 extern void dma_init(void);
 extern uint dma_check(void);
 extern int dma_xfer(void *dest, uint count, void *src);
@@ -52,15 +58,18 @@ extern int dma_xfer(void *dest, uint count, void *src);
 /*
  * Convert picoseconds into clock cycles (rounding up if needed).
  */
+extern ulong get_ddr_clk(ulong dummy);
 
 int
 picos_to_clk(int picos)
 {
+	unsigned int ddr_bus_clk;
 	int clks;
 
-	clks = picos / (2000000000 / (get_bus_freq(0) / 1000));
-	if (picos % (2000000000 / (get_bus_freq(0) / 1000)) != 0) {
-	clks++;
+	ddr_bus_clk = get_ddr_clk(0) >> 1;
+	clks = picos / ((1000000000 / ddr_bus_clk) * 1000);
+	if (picos % ((1000000000 / ddr_bus_clk) * 1000) !=0) {
+		clks++;
 	}
 
 	return clks;
@@ -104,32 +113,53 @@ static void spd_debug(spd_eeprom_t *spd)
 long int spd_sdram()
 {
 	volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
-	volatile ddr8349_t *ddr = &immap->ddr;
-	volatile law8349_t *ecm = &immap->sysconf.ddrlaw[0];
+	volatile ddr83xx_t *ddr = &immap->ddr;
+	volatile law83xx_t *ecm = &immap->sysconf.ddrlaw[0];
 	spd_eeprom_t spd;
-	unsigned tmp, tmp1;
+	unsigned tmp;
 	unsigned int memsize;
 	unsigned int law_size;
-	unsigned char caslat;
-	unsigned int trfc, trfc_clk, trfc_low;
+	unsigned char caslat, caslat_ctrl;
+	unsigned char burstlen;
+	unsigned int max_bus_clk;
+	unsigned int max_data_rate, effective_data_rate;
+	unsigned int ddrc_clk;
+	unsigned int refresh_clk;
+	unsigned sdram_cfg;
+	unsigned int ddrc_ecc_enable;
 
+
+        /* Read SPD parameters with I2C */
 	CFG_READ_SPD(SPD_EEPROM_ADDRESS, 0, 1, (uchar *) & spd, sizeof (spd));
 #ifdef SPD_DEBUG
 	spd_debug(&spd);
 #endif
+	/* Check the memory type */
+	if (spd.mem_type != SPD_MEMTYPE_DDR) {
+		printf("DDR: Module mem type is %02X\n", spd.mem_type);
+		return 0;
+	}
+
+	/* Check the number of physical bank */
 	if (spd.nrows > 2) {
-		puts("DDR:Only two chip selects are supported on ADS.\n");
+		printf("DDR: The number of physical bank is %02X\n", spd.nrows);
 		return 0;
 	}
 
-	if (spd.nrow_addr < 12
-	    || spd.nrow_addr > 14
-	    || spd.ncol_addr < 8
-	    || spd.ncol_addr > 11) {
-		puts("DDR:Row or Col number unsupported.\n");
+	/* Check if the number of row of the module is in the range of DDRC */
+	if (spd.nrow_addr < 12 || spd.nrow_addr > 14) {
+		printf("DDR: Row number is out of range of DDRC, row=%02X\n",
+							 spd.nrow_addr);
 		return 0;
 	}
 
+	/* Check if the number of col of the module is in the range of DDRC */
+	if (spd.ncol_addr < 8 || spd.ncol_addr > 11) {
+		printf("DDR: Col number is out of range of DDRC, col=%02X\n",
+							 spd.ncol_addr);
+		return 0;
+	}
+        /* Setup DDR chip select register */
 	ddr->csbnds[2].csbnds = (banksize(spd.row_dens) >> 24) - 1;
 	ddr->cs_config[2] = ( 1 << 31
 			    | (spd.nrow_addr - 12) << 8
@@ -172,54 +202,84 @@ long int spd_sdram()
 	debug("DDR:ar=0x%08x\n", ecm->ar);
 
 	/*
-	 * find the largest CAS
+	 * Find the largest CAS by locating the highest 1 bit
+	 * in the spd.cas_lat field.  Translate it to a DDR
+	 * controller field value:
+	 *
+	 *	CAS Lat	 DDR I	   Ctrl
+	 *	Clocks	 SPD Bit   Value
+	 *	-------+--------+---------
+	 *	1.0        0        001
+	 *	1.5        1        010
+	 *	2.0        2        011
+	 *	2.5        3        100
+	 *	3.0        4        101
+	 *	3.5        5        110
+	 *	4.0        6        111
 	 */
-	if(spd.cas_lat & 0x40) {
-		caslat = 7;
-	} else if (spd.cas_lat & 0x20) {
-		caslat = 6;
-	} else if (spd.cas_lat & 0x10) {
-		caslat = 5;
-	} else if (spd.cas_lat & 0x08) {
-		caslat = 4;
-	} else if (spd.cas_lat & 0x04) {
-		caslat = 3;
-	} else if (spd.cas_lat & 0x02) {
-		caslat = 2;
-	} else if (spd.cas_lat & 0x01) {
-		caslat = 1;
-	} else {
-		puts("DDR:no valid CAS Latency information.\n");
+	caslat = __ilog2(spd.cas_lat);
+
+	if (caslat > 4 ) {
+		printf("DDR: Invalid SPD CAS Latency, caslat=%02X\n", caslat);
 		return 0;
 	}
+	max_bus_clk = 1000 *10 / (((spd.clk_cycle & 0xF0) >> 4) * 10
+			+ (spd.clk_cycle & 0x0f));
+	max_data_rate = max_bus_clk * 2;
+
+	debug("DDR:Module maximum data rate is: %dMhz\n", max_data_rate);
+
+	ddrc_clk = get_ddr_clk(0) / 1000000;
 
-	tmp = 20000 / (((spd.clk_cycle & 0xF0) >> 4) * 10
-		       + (spd.clk_cycle & 0x0f));
-	debug("DDR:Module maximum data rate is: %dMhz\n", tmp);
-
-	tmp1 = get_bus_freq(0) / 1000000;
-	if (tmp1 < 230 && tmp1 >= 90 && tmp >= 230) {
-		/* 90~230 range, treated as DDR 200 */
-		if (spd.clk_cycle3 == 0xa0)
-			caslat -= 2;
-		else if(spd.clk_cycle2 == 0xa0)
-			caslat--;
-	} else if (tmp1 < 280 && tmp1 >= 230 && tmp >= 280) {
-		/* 230-280 range, treated as DDR 266 */
-		if (spd.clk_cycle3 == 0x75)
-			caslat -= 2;
-		else if (spd.clk_cycle2 == 0x75)
-			caslat--;
-	} else if (tmp1 < 350 && tmp1 >= 280 && tmp >= 350) {
-		/* 280~350 range, treated as DDR 333 */
-		if (spd.clk_cycle3 == 0x60)
-			caslat -= 2;
-		else if (spd.clk_cycle2 == 0x60)
-			caslat--;
-	} else if (tmp1 < 90 || tmp1 >= 350) {
-		/* DDR rate out-of-range */
-		puts("DDR:platform frequency is not fit for DDR rate\n");
+	if (max_data_rate >= 390) { /* it is DDR 400 */
+		printf("DDR: platform not support DDR 400\n");
 		return 0;
+	} else if (max_data_rate >= 323) { /* it is DDR 333 */
+		if (ddrc_clk <= 350 && ddrc_clk > 280) {
+			/* DDRC clk at 280~350 */
+			effective_data_rate = 333; /* 6ns */
+			caslat = caslat;
+		} else if (ddrc_clk <= 280 && ddrc_clk > 230) {
+			/* DDRC clk at 230~280 */
+			if (spd.clk_cycle2 == 0x75) {
+				effective_data_rate = 266; /* 7.5ns */
+				caslat = caslat - 1;
+			}
+		} else if (ddrc_clk <= 230 && ddrc_clk > 90) {
+			/* DDRC clk at 90~230 */
+			if (spd.clk_cycle3 == 0xa0) {
+				effective_data_rate = 200; /* 10ns */
+				caslat = caslat - 2;
+			}
+		}
+	} else if (max_data_rate >= 256) { /* it is DDR 266 */
+		if (ddrc_clk <= 350 && ddrc_clk > 280) {
+			/* DDRC clk at 280~350 */
+			printf("DDR: DDR controller freq is more than "
+				"max data rate of the module\n");
+			return 0;
+		} else if (ddrc_clk <= 280 && ddrc_clk > 230) {
+			/* DDRC clk at 230~280 */
+			effective_data_rate = 266; /* 7.5ns */
+			caslat = caslat;
+		} else if (ddrc_clk <= 230 && ddrc_clk > 90) {
+			/* DDRC clk at 90~230 */
+			if (spd.clk_cycle2 == 0xa0) {
+				effective_data_rate = 200; /* 10ns */
+				caslat = caslat - 1;
+			}
+		}
+	} else if (max_data_rate >= 190) { /* it is DDR 200 */
+		if (ddrc_clk <= 350 && ddrc_clk > 230) {
+			/* DDRC clk at 230~350 */
+			printf("DDR: DDR controller freq is more than "
+				"max data rate of the module\n");
+			return 0;
+		} else if (ddrc_clk <= 230 && ddrc_clk > 90) {
+			/* DDRC clk at 90~230 */
+			effective_data_rate = 200; /* 10ns */
+			caslat = caslat;
+		}
 	}
 
 	/*
@@ -229,16 +289,14 @@ long int spd_sdram()
 	 * note: WRREC(Twr) and WRTORD(Twtr) are not in SPD,
 	 * use conservative value here.
 	 */
-	trfc = spd.trfc * 1000;         /* up to ps */
-	trfc_clk = picos_to_clk(trfc);
-	trfc_low = (trfc_clk - 8) & 0xf;
+	caslat_ctrl = (caslat + 1) & 0x07; /* see as above */
 
 	ddr->timing_cfg_1 =
 	    (((picos_to_clk(spd.trp * 250) & 0x07) << 28 ) |
 	     ((picos_to_clk(spd.tras * 1000) & 0x0f ) << 24 ) |
 	     ((picos_to_clk(spd.trcd * 250) & 0x07) << 20 ) |
-	     ((caslat & 0x07) << 16 ) |
-	     (trfc_low << 12 ) |
+	     ((caslat_ctrl & 0x07) << 16 ) |
+	     (((picos_to_clk(spd.trfc * 1000) - 8) & 0x0f) << 12 ) |
 	     ( 0x300 ) |
 	     ((picos_to_clk(spd.trrd * 250) & 0x07) << 4) | 1);
 
@@ -246,36 +304,49 @@ long int spd_sdram()
 
 	debug("DDR:timing_cfg_1=0x%08x\n", ddr->timing_cfg_1);
 	debug("DDR:timing_cfg_2=0x%08x\n", ddr->timing_cfg_2);
+	/* Setup init value, but not enable */
+	ddr->sdram_cfg = 0x42000000;
+
+	/* Check DIMM data bus width */
+	if (spd.dataw_lsb == 0x20)
+	{
+		burstlen = 0x03; /* 32 bit data bus, burst len is 8 */
+		printf("\n   DDR DIMM: data bus width is 32 bit");
+	}
+	else
+	{
+		burstlen = 0x02; /* Others act as 64 bit bus, burst len is 4 */
+		printf("\n   DDR DIMM: data bus width is 64 bit");
+	}
 
-	/*
-	 * Only DDR I is supported
-	 * DDR I and II have different mode-register-set definition
+	/* Is this an ECC DDR chip? */
+	if (spd.config == 0x02) {
+		printf(" with ECC\n");
+	}
+	else
+		printf(" without ECC\n");
+
+	/* Burst length is always 4 for 64 bit data bus, 8 for 32 bit data bus,
+	   Burst type is sequential
 	 */
 	switch(caslat) {
+	case 1:
+		ddr->sdram_mode = 0x50 | burstlen; /* CL=1.5 */
+		break;
 	case 2:
-		tmp = 0x50; /* 1.5 */
+		ddr->sdram_mode = 0x20 | burstlen; /* CL=2.0 */
 		break;
 	case 3:
-		tmp = 0x20; /* 2.0 */
+		ddr->sdram_mode = 0x60 | burstlen; /* CL=2.5 */
 		break;
 	case 4:
-		tmp = 0x60; /* 2.5 */
-		break;
-	case 5:
-		tmp = 0x30; /* 3.0 */
+		ddr->sdram_mode = 0x30 | burstlen; /* CL=3.0 */
 		break;
 	default:
-		puts("DDR:only CAS Latency 1.5, 2.0, 2.5, 3.0 is supported.\n");
+		printf("DDR:only CAS Latency 1.5, 2.0, 2.5, 3.0 "
+					"is supported.\n");
 		return 0;
 	}
-#if defined (CONFIG_DDR_32BIT)
-	/* set burst length to 8 for 32-bit data path */
-	tmp |= 0x03;
-#else
-	/* set burst length to 4 - default for 64-bit data path */
-	tmp |= 0x02;
-#endif
-	ddr->sdram_mode = tmp;
 	debug("DDR:sdram_mode=0x%08x\n", ddr->sdram_mode);
 
 	switch(spd.refresh) {
@@ -315,33 +386,15 @@ long int spd_sdram()
 	ddr->sdram_interval = ((tmp & 0x3fff) << 16) | 0x100;
 	debug("DDR:sdram_interval=0x%08x\n", ddr->sdram_interval);
 
-	/*
-	 * Is this an ECC DDR chip?
-	 */
-#if defined(CONFIG_DDR_ECC)
-	if (spd.config == 0x02) {
-		/* disable error detection */
-		ddr->err_disable = ~ECC_ERROR_ENABLE;
+	/* SS_EN = 0, source synchronous disable
+	 * CLK_ADJST = 0, MCK/MCK# is launched aligned with addr/cmd
+         */
+	ddr->sdram_clk_cntl = 0x00000000;
+	debug("DDR:sdram_clk_cntl=0x%08x\n", ddr->sdram_clk_cntl);
 
-		/* set single bit error threshold to maximum value,
-		 * reset counter to zero */
-		ddr->err_sbe = (255 << ECC_ERROR_MAN_SBET_SHIFT) |
-			(0 << ECC_ERROR_MAN_SBEC_SHIFT);
-	}
-	debug("DDR:err_disable=0x%08x\n", ddr->err_disable);
-	debug("DDR:err_sbe=0x%08x\n", ddr->err_sbe);
-#endif
 	asm("sync;isync");
 
-	udelay(500);
-
-	/*
-	 * SS_EN=1,
-	 * CLK_ADJST = 2-MCK/MCK_B, is lauched 1/2 of one SDRAM
-	 * clock cycle after address/command
-	 */
-	/*ddr->sdram_clk_cntl = 0x82000000;*/
-	ddr->sdram_clk_cntl = (DDR_SDRAM_CLK_CNTL_SS_EN|DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05);
+	udelay(600);
 
 	/*
 	 * Figure out the settings for the sdram_cfg register.  Build up
@@ -352,38 +405,48 @@ long int spd_sdram()
 	 * sdram_cfg[0]   = 1 (ddr sdram logic enable)
 	 * sdram_cfg[1]   = 1 (self-refresh-enable)
 	 * sdram_cfg[6:7] = 2 (SDRAM type = DDR SDRAM)
+	 * sdram_cfg[12] = 0 (32_BE =0 , 64 bit bus mode)
+	 * sdram_cfg[13] = 0 (8_BE =0, 4-beat bursts)
 	 */
-	tmp = 0xc2000000;
+	sdram_cfg = 0xC2000000;
 
-#if defined (CONFIG_DDR_32BIT)
-	/* in 32-Bit mode burst len is 8 beats */
-	tmp |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE);
-#endif
-	/*
-	 * sdram_cfg[3] = RD_EN - registered DIMM enable
-	 *   A value of 0x26 indicates micron registered DIMMS (micron.com)
-	 */
-	if (spd.mod_attr == 0x26) {
-		tmp |= 0x10000000;
+	/* sdram_cfg[3] = RD_EN - registered DIMM enable */
+	if (spd.mod_attr & 0x02) {
+		sdram_cfg |= 0x10000000;
 	}
 
+	/* The DIMM is 32bit width */
+	if (spd.dataw_lsb == 0x20) {
+		sdram_cfg |= 0x000C0000;
+	}
+	ddrc_ecc_enable = 0;
+
 #if defined(CONFIG_DDR_ECC)
-	/*
-	 * If the user wanted ECC (enabled via sdram_cfg[2])
-	 */
+	/* Enable ECC with sdram_cfg[2] */
 	if (spd.config == 0x02) {
-		tmp |= SDRAM_CFG_ECC_EN;
+		sdram_cfg |= 0x20000000;
+		ddrc_ecc_enable = 1;
+		/* disable error detection */
+		ddr->err_disable = ~ECC_ERROR_ENABLE;
+		/* set single bit error threshold to maximum value,
+		 * reset counter to zero */
+		ddr->err_sbe = (255 << ECC_ERROR_MAN_SBET_SHIFT) |
+			(0 << ECC_ERROR_MAN_SBEC_SHIFT);
 	}
+
+	debug("DDR:err_disable=0x%08x\n", ddr->err_disable);
+	debug("DDR:err_sbe=0x%08x\n", ddr->err_sbe);
 #endif
+	printf("   DDRC ECC mode: %s", ddrc_ecc_enable ? "ON":"OFF");
 
 #if defined(CONFIG_DDR_2T_TIMING)
 	/*
 	 * Enable 2T timing by setting sdram_cfg[16].
 	 */
-	tmp |= SDRAM_CFG_2T_EN;
+	sdram_cfg |= SDRAM_CFG_2T_EN;
 #endif
-
-	ddr->sdram_cfg = tmp;
+	/* Enable controller, and GO! */
+	ddr->sdram_cfg = sdram_cfg;
 	asm("sync;isync");
 	udelay(500);
 
@@ -393,7 +456,7 @@ long int spd_sdram()
 #endif /* CONFIG_SPD_EEPROM */
 
 
-#if defined(CONFIG_DDR_ECC)
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
 /*
  * Use timebase counter, get_timer() is not availabe
  * at this point of initialization yet.
@@ -431,7 +494,7 @@ void ddr_enable_ecc(unsigned int dram_size)
 {
 	uint *p;
 	volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
-	volatile ddr8349_t *ddr = &immap->ddr;
+	volatile ddr83xx_t *ddr= &immap->ddr;
 	unsigned long t_start, t_end;
 #if defined(CONFIG_DDR_ECC_INIT_VIA_DMA)
 	uint i;
-- 
cgit 


From bed85caf872714ebf53013967a695c9d63acfc68 Mon Sep 17 00:00:00 2001
From: Timur Tabi <timur@freescale.com>
Date: Tue, 31 Oct 2006 18:13:36 -0600
Subject: mpc83xx: Add support for Errata DDR6 on MPC 834x systems

CHANGELOG:

* Errata DDR6, which affects all current MPC 834x processors, lists changes
  required to maintain compatibility with various types of DDR memory.  This
  patch implements those changes.

Signed-off-by: Timur Tabi <timur@freescale.com>
---
 cpu/mpc83xx/spd_sdram.c | 43 ++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 42 insertions(+), 1 deletion(-)

(limited to 'cpu/mpc83xx/spd_sdram.c')

diff --git a/cpu/mpc83xx/spd_sdram.c b/cpu/mpc83xx/spd_sdram.c
index 153848d343..8ee4234631 100644
--- a/cpu/mpc83xx/spd_sdram.c
+++ b/cpu/mpc83xx/spd_sdram.c
@@ -112,11 +112,14 @@ static void spd_debug(spd_eeprom_t *spd)
 
 long int spd_sdram()
 {
+#ifdef CONFIG_MPC834X
+	int caslat_83xx;  /* For Errata DDR6 */
+#endif
 	volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
 	volatile ddr83xx_t *ddr = &immap->ddr;
 	volatile law83xx_t *ecm = &immap->sysconf.ddrlaw[0];
 	spd_eeprom_t spd;
-	unsigned tmp;
+	unsigned int tmp, tmp1;
 	unsigned int memsize;
 	unsigned int law_size;
 	unsigned char caslat, caslat_ctrl;
@@ -282,6 +285,40 @@ long int spd_sdram()
 		}
 	}
 
+#ifdef CONFIG_MPC834X
+/* Errata DDR6
+   This errata affects all MPC8349E, MPC8343E and MPC8347E processors.
+*/
+	if ((tmp1 >= 280) && (tmp1 < 350)) /* CSB=333 */
+	{
+		if (spd.mid[0] == 0x2c) {
+			/* Micron memory running at 333 MHz */
+			/* Chances are, U-Boot will crash before we get here,
+			   but just in case, display a message and return error. */
+			printf("Micron DDR not supported at 333MHz CSB\n");
+			return 0;
+		} else if (spd.mid[0] == 0xad) {
+			printf("Hynix DDR does not require Errata DDR6\n");
+		} else {
+			/* enable 2 cycle Earlier for CL=2.5 or 3 */
+			ddr->debug_reg = 0x202c0000;
+			printf("Errata DDR6 (debug_reg=0x%x)\n", ddr->debug_reg);
+		}
+		caslat_83xx = caslat;
+	}
+
+	if ((tmp1 >= 230) && (tmp1 < 280)) {  /* CSB=266 */
+		if (spd.mid[0] != 0x2c) /* non-Micron */
+			caslat_83xx = caslat - 1;
+
+	}
+
+	if ((tmp1 >= 90) && (tmp1 < 230)) {  /* CSB=200 */
+		caslat = 3;
+		caslat_83xx = 2;
+	}
+#endif
+
 	/*
 	 * note: caslat must also be programmed into ddr->sdram_mode
 	 * register.
@@ -295,7 +332,11 @@ long int spd_sdram()
 	    (((picos_to_clk(spd.trp * 250) & 0x07) << 28 ) |
 	     ((picos_to_clk(spd.tras * 1000) & 0x0f ) << 24 ) |
 	     ((picos_to_clk(spd.trcd * 250) & 0x07) << 20 ) |
+#ifdef CONFIG_MPC834x
+	     ((caslat_83xx & 0x07) << 16 ) |
+#else
 	     ((caslat_ctrl & 0x07) << 16 ) |
+#endif
 	     (((picos_to_clk(spd.trfc * 1000) - 8) & 0x0f) << 12 ) |
 	     ( 0x300 ) |
 	     ((picos_to_clk(spd.trrd * 250) & 0x07) << 4) | 1);
-- 
cgit 


From 2ad6b513b31070bd0c003792ed1c3e7f5d740357 Mon Sep 17 00:00:00 2001
From: Timur Tabi <timur@freescale.com>
Date: Tue, 31 Oct 2006 18:44:42 -0600
Subject: mpc83xx: Add support for the MPC8349E-mITX

PREREQUISITE PATCHES:

* This patch can only be applied after the following patches have been applied:

  1) DNX#2006090742000024 "Add support for multiple I2C buses"
  2) DNX#2006090742000033 "Multi-bus I2C implementation of MPC834x"
  3) DNX#2006091242000041 "Additional MPC8349 support for multibus i2c"
  4) DNX#2006091242000078 "Add support for variable flash memory sizes on 83xx systems"
  5) DNX#2006091242000069 "Add support for Errata DDR6 on MPC 834x systems"

CHANGELOG:

* Add support for the Freescale MPC8349E-mITX reference design platform.
  The second TSEC (Vitesse 7385 switch) is not supported at this time.

Signed-off-by: Timur Tabi <timur@freescale.com>
---
 cpu/mpc83xx/spd_sdram.c | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

(limited to 'cpu/mpc83xx/spd_sdram.c')

diff --git a/cpu/mpc83xx/spd_sdram.c b/cpu/mpc83xx/spd_sdram.c
index 8ee4234631..3dfde8ac04 100644
--- a/cpu/mpc83xx/spd_sdram.c
+++ b/cpu/mpc83xx/spd_sdram.c
@@ -133,6 +133,26 @@ long int spd_sdram()
 
 
         /* Read SPD parameters with I2C */
+#ifdef CFG_83XX_DDR_USES_CS0
+	ddr->csbnds[0].csbnds = (banksize(spd.row_dens) >> 24) - 1;
+	ddr->cs_config[0] = ( 1 << 31
+			    | (spd.nrow_addr - 12) << 8
+			    | (spd.ncol_addr - 8) );
+	debug("\n");
+	debug("cs0_bnds = 0x%08x\n",ddr->csbnds[0].csbnds);
+	debug("cs0_config = 0x%08x\n",ddr->cs_config[0]);
+
+	if (spd.nrows == 2) {
+		ddr->csbnds[1].csbnds = ( (banksize(spd.row_dens) >> 8)
+				  | ((banksize(spd.row_dens) >> 23) - 1) );
+		ddr->cs_config[1] = ( 1<<31
+				    | (spd.nrow_addr-12) << 8
+				    | (spd.ncol_addr-8) );
+		debug("cs1_bnds = 0x%08x\n",ddr->csbnds[1].csbnds);
+		debug("cs1_config = 0x%08x\n",ddr->cs_config[1]);
+	}
+
+#else
 	CFG_READ_SPD(SPD_EEPROM_ADDRESS, 0, 1, (uchar *) & spd, sizeof (spd));
 #ifdef SPD_DEBUG
 	spd_debug(&spd);
@@ -180,6 +200,7 @@ long int spd_sdram()
 		debug("cs3_bnds = 0x%08x\n",ddr->csbnds[3].csbnds);
 		debug("cs3_config = 0x%08x\n",ddr->cs_config[3]);
 	}
+#endif
 
 	if (spd.mem_type != 0x07) {
 		puts("No DDR module found!\n");
-- 
cgit 


From 5f8204394e39bbe8cd9f08b8f8d145b6c01f7c73 Mon Sep 17 00:00:00 2001
From: Dave Liu <daveliu@freescale.com>
Date: Fri, 3 Nov 2006 19:33:44 -0600
Subject: mpc83xx: Add MPC8360EMDS basic board support

Add support for the Freescale MPC8360EMDS board.
Includes DDR, DUART, Local Bus, PCI.
---
 cpu/mpc83xx/spd_sdram.c | 304 ++++++++++++++++++++++++------------------------
 1 file changed, 151 insertions(+), 153 deletions(-)

(limited to 'cpu/mpc83xx/spd_sdram.c')

diff --git a/cpu/mpc83xx/spd_sdram.c b/cpu/mpc83xx/spd_sdram.c
index 3dfde8ac04..acc8c9e79b 100644
--- a/cpu/mpc83xx/spd_sdram.c
+++ b/cpu/mpc83xx/spd_sdram.c
@@ -4,7 +4,7 @@
  * (C) Copyright 2006
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
- * Copyright 2004 Freescale Semiconductor.
+ * Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
  * (C) Copyright 2003 Motorola Inc.
  * Xianghua Xiao (X.Xiao@motorola.com)
  *
@@ -112,14 +112,10 @@ static void spd_debug(spd_eeprom_t *spd)
 
 long int spd_sdram()
 {
-#ifdef CONFIG_MPC834X
-	int caslat_83xx;  /* For Errata DDR6 */
-#endif
 	volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
 	volatile ddr83xx_t *ddr = &immap->ddr;
 	volatile law83xx_t *ecm = &immap->sysconf.ddrlaw[0];
 	spd_eeprom_t spd;
-	unsigned int tmp, tmp1;
 	unsigned int memsize;
 	unsigned int law_size;
 	unsigned char caslat, caslat_ctrl;
@@ -131,28 +127,7 @@ long int spd_sdram()
 	unsigned sdram_cfg;
 	unsigned int ddrc_ecc_enable;
 
-
         /* Read SPD parameters with I2C */
-#ifdef CFG_83XX_DDR_USES_CS0
-	ddr->csbnds[0].csbnds = (banksize(spd.row_dens) >> 24) - 1;
-	ddr->cs_config[0] = ( 1 << 31
-			    | (spd.nrow_addr - 12) << 8
-			    | (spd.ncol_addr - 8) );
-	debug("\n");
-	debug("cs0_bnds = 0x%08x\n",ddr->csbnds[0].csbnds);
-	debug("cs0_config = 0x%08x\n",ddr->cs_config[0]);
-
-	if (spd.nrows == 2) {
-		ddr->csbnds[1].csbnds = ( (banksize(spd.row_dens) >> 8)
-				  | ((banksize(spd.row_dens) >> 23) - 1) );
-		ddr->cs_config[1] = ( 1<<31
-				    | (spd.nrow_addr-12) << 8
-				    | (spd.ncol_addr-8) );
-		debug("cs1_bnds = 0x%08x\n",ddr->csbnds[1].csbnds);
-		debug("cs1_config = 0x%08x\n",ddr->cs_config[1]);
-	}
-
-#else
 	CFG_READ_SPD(SPD_EEPROM_ADDRESS, 0, 1, (uchar *) & spd, sizeof (spd));
 #ifdef SPD_DEBUG
 	spd_debug(&spd);
@@ -183,6 +158,26 @@ long int spd_sdram()
 		return 0;
 	}
         /* Setup DDR chip select register */
+#ifdef CFG_83XX_DDR_USES_CS0
+	ddr->csbnds[0].csbnds = (banksize(spd.row_dens) >> 24) - 1;
+	ddr->cs_config[0] = ( 1 << 31
+			    | (spd.nrow_addr - 12) << 8
+			    | (spd.ncol_addr - 8) );
+	debug("\n");
+	debug("cs0_bnds = 0x%08x\n",ddr->csbnds[0].csbnds);
+	debug("cs0_config = 0x%08x\n",ddr->cs_config[0]);
+
+	if (spd.nrows == 2) {
+		ddr->csbnds[1].csbnds = ( (banksize(spd.row_dens) >> 8)
+				  | ((banksize(spd.row_dens) >> 23) - 1) );
+		ddr->cs_config[1] = ( 1<<31
+				    | (spd.nrow_addr-12) << 8
+				    | (spd.ncol_addr-8) );
+		debug("cs1_bnds = 0x%08x\n",ddr->csbnds[1].csbnds);
+		debug("cs1_config = 0x%08x\n",ddr->cs_config[1]);
+	}
+
+#else
 	ddr->csbnds[2].csbnds = (banksize(spd.row_dens) >> 24) - 1;
 	ddr->cs_config[2] = ( 1 << 31
 			    | (spd.nrow_addr - 12) << 8
@@ -243,8 +238,9 @@ long int spd_sdram()
 	 */
 	caslat = __ilog2(spd.cas_lat);
 
-	if (caslat > 4 ) {
-		printf("DDR: Invalid SPD CAS Latency, caslat=%02X\n", caslat);
+	if (caslat > 6 ) {
+		printf("DDR: Invalid SPD CAS Latency, caslat=%02X\n",
+			spd.cas_lat);
 		return 0;
 	}
 	max_bus_clk = 1000 *10 / (((spd.clk_cycle & 0xF0) >> 4) * 10
@@ -256,89 +252,110 @@ long int spd_sdram()
 	ddrc_clk = get_ddr_clk(0) / 1000000;
 
 	if (max_data_rate >= 390) { /* it is DDR 400 */
-		printf("DDR: platform not support DDR 400\n");
-		return 0;
+		if (ddrc_clk <= 410 && ddrc_clk > 350) {
+			/* DDR controller clk at 350~410 */
+			effective_data_rate = 400; /* 5ns */
+			caslat = caslat;
+		} else if (ddrc_clk <= 350 && ddrc_clk > 280) {
+			/* DDR controller clk at 280~350 */
+			effective_data_rate = 333; /* 6ns */
+			if (spd.clk_cycle2 == 0x60) {
+				caslat = caslat - 1;
+			} else {
+				caslat = caslat;
+			}
+		} else if (ddrc_clk <= 280 && ddrc_clk > 230) {
+			/* DDR controller clk at 230~280 */
+			effective_data_rate = 266; /* 7.5ns */
+			if (spd.clk_cycle3 == 0x75) {
+				caslat = caslat - 2;
+			} else if (spd.clk_cycle2 == 0x60) {
+				caslat = caslat - 1;
+			} else {
+				caslat = caslat;
+			}
+		} else if (ddrc_clk <= 230 && ddrc_clk > 90) {
+			/* DDR controller clk at 90~230 */
+			effective_data_rate = 200; /* 10ns */
+			if (spd.clk_cycle3 == 0x75) {
+				caslat = caslat - 2;
+			} else if (spd.clk_cycle2 == 0x60) {
+				caslat = caslat - 1;
+			} else {
+				caslat = caslat;
+			}
+		}
 	} else if (max_data_rate >= 323) { /* it is DDR 333 */
 		if (ddrc_clk <= 350 && ddrc_clk > 280) {
-			/* DDRC clk at 280~350 */
+			/* DDR controller clk at 280~350 */
 			effective_data_rate = 333; /* 6ns */
 			caslat = caslat;
 		} else if (ddrc_clk <= 280 && ddrc_clk > 230) {
-			/* DDRC clk at 230~280 */
+			/* DDR controller clk at 230~280 */
+			effective_data_rate = 266; /* 7.5ns */
 			if (spd.clk_cycle2 == 0x75) {
-				effective_data_rate = 266; /* 7.5ns */
 				caslat = caslat - 1;
+			} else {
+				caslat = caslat;
 			}
 		} else if (ddrc_clk <= 230 && ddrc_clk > 90) {
-			/* DDRC clk at 90~230 */
+			/* DDR controller clk at 90~230 */
+			effective_data_rate = 200; /* 10ns */
 			if (spd.clk_cycle3 == 0xa0) {
-				effective_data_rate = 200; /* 10ns */
 				caslat = caslat - 2;
+			} else if (spd.clk_cycle2 == 0x75) {
+				caslat = caslat - 1;
+			} else {
+				caslat = caslat;
 			}
 		}
 	} else if (max_data_rate >= 256) { /* it is DDR 266 */
 		if (ddrc_clk <= 350 && ddrc_clk > 280) {
-			/* DDRC clk at 280~350 */
+			/* DDR controller clk at 280~350 */
 			printf("DDR: DDR controller freq is more than "
 				"max data rate of the module\n");
 			return 0;
 		} else if (ddrc_clk <= 280 && ddrc_clk > 230) {
-			/* DDRC clk at 230~280 */
+			/* DDR controller clk at 230~280 */
 			effective_data_rate = 266; /* 7.5ns */
 			caslat = caslat;
 		} else if (ddrc_clk <= 230 && ddrc_clk > 90) {
-			/* DDRC clk at 90~230 */
+			/* DDR controller clk at 90~230 */
+			effective_data_rate = 200; /* 10ns */
 			if (spd.clk_cycle2 == 0xa0) {
-				effective_data_rate = 200; /* 10ns */
 				caslat = caslat - 1;
 			}
 		}
 	} else if (max_data_rate >= 190) { /* it is DDR 200 */
 		if (ddrc_clk <= 350 && ddrc_clk > 230) {
-			/* DDRC clk at 230~350 */
+			/* DDR controller clk at 230~350 */
 			printf("DDR: DDR controller freq is more than "
 				"max data rate of the module\n");
 			return 0;
 		} else if (ddrc_clk <= 230 && ddrc_clk > 90) {
-			/* DDRC clk at 90~230 */
+			/* DDR controller clk at 90~230 */
 			effective_data_rate = 200; /* 10ns */
 			caslat = caslat;
 		}
 	}
 
-#ifdef CONFIG_MPC834X
-/* Errata DDR6
-   This errata affects all MPC8349E, MPC8343E and MPC8347E processors.
-*/
-	if ((tmp1 >= 280) && (tmp1 < 350)) /* CSB=333 */
-	{
-		if (spd.mid[0] == 0x2c) {
-			/* Micron memory running at 333 MHz */
-			/* Chances are, U-Boot will crash before we get here,
-			   but just in case, display a message and return error. */
-			printf("Micron DDR not supported at 333MHz CSB\n");
-			return 0;
-		} else if (spd.mid[0] == 0xad) {
-			printf("Hynix DDR does not require Errata DDR6\n");
-		} else {
-			/* enable 2 cycle Earlier for CL=2.5 or 3 */
-			ddr->debug_reg = 0x202c0000;
-			printf("Errata DDR6 (debug_reg=0x%x)\n", ddr->debug_reg);
-		}
-		caslat_83xx = caslat;
-	}
-
-	if ((tmp1 >= 230) && (tmp1 < 280)) {  /* CSB=266 */
-		if (spd.mid[0] != 0x2c) /* non-Micron */
-			caslat_83xx = caslat - 1;
+	debug("DDR:Effective data rate is: %dMhz\n", effective_data_rate);
+	debug("DDR:The MSB 1 of CAS Latency is: %d\n", caslat);
 
+	/*
+	 * Errata DDR6 work around: input enable 2 cycles earlier.
+	 * including MPC834x Rev1.0/1.1 and MPC8360 Rev1.1/1.2.
+	 */
+	if (caslat == 2) {
+		ddr->debug_reg = 0x201c0000; /* CL=2 */
+	} else if (caslat == 3) {
+		ddr->debug_reg = 0x202c0000; /* CL=2.5 */
+	} else if (caslat == 4) {
+		ddr->debug_reg = 0x202c0000; /* CL=3.0 */
 	}
+	__asm__ __volatile__ ("sync");
 
-	if ((tmp1 >= 90) && (tmp1 < 230)) {  /* CSB=200 */
-		caslat = 3;
-		caslat_83xx = 2;
-	}
-#endif
+	debug("Errata DDR6 (debug_reg=0x%08x)\n", ddr->debug_reg);
 
 	/*
 	 * note: caslat must also be programmed into ddr->sdram_mode
@@ -353,11 +370,7 @@ long int spd_sdram()
 	    (((picos_to_clk(spd.trp * 250) & 0x07) << 28 ) |
 	     ((picos_to_clk(spd.tras * 1000) & 0x0f ) << 24 ) |
 	     ((picos_to_clk(spd.trcd * 250) & 0x07) << 20 ) |
-#ifdef CONFIG_MPC834x
-	     ((caslat_83xx & 0x07) << 16 ) |
-#else
 	     ((caslat_ctrl & 0x07) << 16 ) |
-#endif
 	     (((picos_to_clk(spd.trfc * 1000) - 8) & 0x0f) << 12 ) |
 	     ( 0x300 ) |
 	     ((picos_to_clk(spd.trrd * 250) & 0x07) << 4) | 1);
@@ -370,13 +383,10 @@ long int spd_sdram()
 	ddr->sdram_cfg = 0x42000000;
 
 	/* Check DIMM data bus width */
-	if (spd.dataw_lsb == 0x20)
-	{
+	if (spd.dataw_lsb == 0x20) {
 		burstlen = 0x03; /* 32 bit data bus, burst len is 8 */
 		printf("\n   DDR DIMM: data bus width is 32 bit");
-	}
-	else
-	{
+	} else {
 		burstlen = 0x02; /* Others act as 64 bit bus, burst len is 4 */
 		printf("\n   DDR DIMM: data bus width is 64 bit");
 	}
@@ -384,68 +394,67 @@ long int spd_sdram()
 	/* Is this an ECC DDR chip? */
 	if (spd.config == 0x02) {
 		printf(" with ECC\n");
-	}
-	else
+	} else {
 		printf(" without ECC\n");
+	}
 
 	/* Burst length is always 4 for 64 bit data bus, 8 for 32 bit data bus,
 	   Burst type is sequential
 	 */
-	switch(caslat) {
-	case 1:
-		ddr->sdram_mode = 0x50 | burstlen; /* CL=1.5 */
-		break;
-	case 2:
-		ddr->sdram_mode = 0x20 | burstlen; /* CL=2.0 */
-		break;
-	case 3:
-		ddr->sdram_mode = 0x60 | burstlen; /* CL=2.5 */
-		break;
-	case 4:
-		ddr->sdram_mode = 0x30 | burstlen; /* CL=3.0 */
-		break;
-	default:
-		printf("DDR:only CAS Latency 1.5, 2.0, 2.5, 3.0 "
-					"is supported.\n");
-		return 0;
+	switch (caslat) {
+		case 1:
+			ddr->sdram_mode = 0x50 | burstlen; /* CL=1.5 */
+			break;
+		case 2:
+			ddr->sdram_mode = 0x20 | burstlen; /* CL=2.0 */
+			break;
+		case 3:
+			ddr->sdram_mode = 0x60 | burstlen; /* CL=2.5 */
+			break;
+		case 4:
+			ddr->sdram_mode = 0x30 | burstlen; /* CL=3.0 */
+			break;
+		default:
+			printf("DDR:only CL 1.5, 2.0, 2.5, 3.0 is supported\n");
+			return 0;
 	}
 	debug("DDR:sdram_mode=0x%08x\n", ddr->sdram_mode);
 
-	switch(spd.refresh) {
-	case 0x00:
-	case 0x80:
-		tmp = picos_to_clk(15625000);
-		break;
-	case 0x01:
-	case 0x81:
-		tmp = picos_to_clk(3900000);
-		break;
-	case 0x02:
-	case 0x82:
-		tmp = picos_to_clk(7800000);
-		break;
-	case 0x03:
-	case 0x83:
-		tmp = picos_to_clk(31300000);
-		break;
-	case 0x04:
-	case 0x84:
-		tmp = picos_to_clk(62500000);
-		break;
-	case 0x05:
-	case 0x85:
-		tmp = picos_to_clk(125000000);
-		break;
-	default:
-		tmp = 0x512;
-		break;
+	switch (spd.refresh) {
+		case 0x00:
+		case 0x80:
+			refresh_clk = picos_to_clk(15625000);
+			break;
+		case 0x01:
+		case 0x81:
+			refresh_clk = picos_to_clk(3900000);
+			break;
+		case 0x02:
+		case 0x82:
+			refresh_clk = picos_to_clk(7800000);
+			break;
+		case 0x03:
+		case 0x83:
+			refresh_clk = picos_to_clk(31300000);
+			break;
+		case 0x04:
+		case 0x84:
+			refresh_clk = picos_to_clk(62500000);
+			break;
+		case 0x05:
+		case 0x85:
+			refresh_clk = picos_to_clk(125000000);
+			break;
+		default:
+			refresh_clk = 0x512;
+			break;
 	}
 
 	/*
 	 * Set BSTOPRE to 0x100 for page mode
 	 * If auto-charge is used, set BSTOPRE = 0
 	 */
-	ddr->sdram_interval = ((tmp & 0x3fff) << 16) | 0x100;
+	ddr->sdram_interval = ((refresh_clk & 0x3fff) << 16) | 0x100;
 	debug("DDR:sdram_interval=0x%08x\n", ddr->sdram_interval);
 
 	/* SS_EN = 0, source synchronous disable
@@ -459,8 +468,8 @@ long int spd_sdram()
 	udelay(600);
 
 	/*
-	 * Figure out the settings for the sdram_cfg register.  Build up
-	 * the entire register in 'tmp' before writing since the write into
+	 * Figure out the settings for the sdram_cfg register. Build up
+	 * the value in 'sdram_cfg' before writing since the write into
 	 * the register will actually enable the memory controller, and all
 	 * settings must be done before enabling.
 	 *
@@ -493,13 +502,13 @@ long int spd_sdram()
 		/* set single bit error threshold to maximum value,
 		 * reset counter to zero */
 		ddr->err_sbe = (255 << ECC_ERROR_MAN_SBET_SHIFT) |
-			(0 << ECC_ERROR_MAN_SBEC_SHIFT);
+				(0 << ECC_ERROR_MAN_SBEC_SHIFT);
 	}
 
 	debug("DDR:err_disable=0x%08x\n", ddr->err_disable);
 	debug("DDR:err_sbe=0x%08x\n", ddr->err_sbe);
 #endif
-	printf("   DDRC ECC mode: %s", ddrc_ecc_enable ? "ON":"OFF");
+	printf("   DDRC ECC mode: %s\n", ddrc_ecc_enable ? "ON":"OFF");
 
 #if defined(CONFIG_DDR_2T_TIMING)
 	/*
@@ -517,7 +526,6 @@ long int spd_sdram()
 }
 #endif /* CONFIG_SPD_EEPROM */
 
-
 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
 /*
  * Use timebase counter, get_timer() is not availabe
@@ -602,26 +610,16 @@ void ddr_enable_ecc(unsigned int dram_size)
 		}
 	}
 
-	/* 8K */
-	dma_xfer((uint *)0x2000, 0x2000, (uint *)0);
-	/* 16K */
-	dma_xfer((uint *)0x4000, 0x4000, (uint *)0);
-	/* 32K */
-	dma_xfer((uint *)0x8000, 0x8000, (uint *)0);
-	/* 64K */
-	dma_xfer((uint *)0x10000, 0x10000, (uint *)0);
-	/* 128k */
-	dma_xfer((uint *)0x20000, 0x20000, (uint *)0);
-	/* 256k */
-	dma_xfer((uint *)0x40000, 0x40000, (uint *)0);
-	/* 512k */
-	dma_xfer((uint *)0x80000, 0x80000, (uint *)0);
-	/* 1M */
-	dma_xfer((uint *)0x100000, 0x100000, (uint *)0);
-	/* 2M */
-	dma_xfer((uint *)0x200000, 0x200000, (uint *)0);
-	/* 4M */
-	dma_xfer((uint *)0x400000, 0x400000, (uint *)0);
+	dma_xfer((uint *)0x2000, 0x2000, (uint *)0); /* 8K */
+	dma_xfer((uint *)0x4000, 0x4000, (uint *)0); /* 16K */
+	dma_xfer((uint *)0x8000, 0x8000, (uint *)0); /* 32K */
+	dma_xfer((uint *)0x10000, 0x10000, (uint *)0); /* 64K */
+	dma_xfer((uint *)0x20000, 0x20000, (uint *)0); /* 128K */
+	dma_xfer((uint *)0x40000, 0x40000, (uint *)0); /* 256K */
+	dma_xfer((uint *)0x80000, 0x80000, (uint *)0); /* 512K */
+	dma_xfer((uint *)0x100000, 0x100000, (uint *)0); /* 1M */
+	dma_xfer((uint *)0x200000, 0x200000, (uint *)0); /* 2M */
+	dma_xfer((uint *)0x400000, 0x400000, (uint *)0); /* 4M */
 
 	for (i = 1; i < dram_size / 0x800000; i++) {
 		dma_xfer((uint *)(0x800000*i), 0x800000, (uint *)0);
-- 
cgit 


From 90f30a710a3c619b5405860a686c4ddfc495d4b6 Mon Sep 17 00:00:00 2001
From: Dave Liu <daveliu@freescale.com>
Date: Thu, 2 Nov 2006 18:05:50 -0600
Subject: mpc83xx: Fix the incorrect dcbz operation

The 834x rev1.x silicon has one CPU5 errata.

The issue is when the data cache locked with
HID0[DLOCK], the dcbz instruction looks like no-op inst.

The right behavior of the data cache is when the data cache
Locked with HID0[DLOCK], the dcbz instruction allocates
new tags in cache.

The 834x rev3.0 and later and 8360 have not this bug inside.

So, when 834x rev3.0/8360 are working with ECC, the dcbz
instruction will corrupt the stack in cache, the processor will
checkstop reset.

However, the 834x rev1.x can work with ECC with these code,
because the sillicon has this cache bug. The dcbz will not
corrupt the stack in cache.
Really, it is the fault code running on fault sillicon.

This patch fix the incorrect dcbz operation. Instead of
CPU FP writing to initialise the ECC.

CHANGELOG:
* Fix the incorrect dcbz operation instead of CPU FP
writing to initialise the ECC memory. Otherwise, it
will corrupt the stack in cache, The processor will checkstop
reset.

Signed-off-by: Dave Liu <daveliu@freescale.com>
---
 cpu/mpc83xx/spd_sdram.c | 52 +++++++++++++++++--------------------------------
 1 file changed, 18 insertions(+), 34 deletions(-)

(limited to 'cpu/mpc83xx/spd_sdram.c')

diff --git a/cpu/mpc83xx/spd_sdram.c b/cpu/mpc83xx/spd_sdram.c
index acc8c9e79b..b91c6130e7 100644
--- a/cpu/mpc83xx/spd_sdram.c
+++ b/cpu/mpc83xx/spd_sdram.c
@@ -562,54 +562,38 @@ static __inline__ unsigned long get_tbms (void)
 /* #define CONFIG_DDR_ECC_INIT_VIA_DMA */
 void ddr_enable_ecc(unsigned int dram_size)
 {
-	uint *p;
 	volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
 	volatile ddr83xx_t *ddr= &immap->ddr;
 	unsigned long t_start, t_end;
+	register u64 *p;
+	register uint size;
+	unsigned int pattern[2];
 #if defined(CONFIG_DDR_ECC_INIT_VIA_DMA)
 	uint i;
 #endif
-
-	debug("Initialize a Cachline in DRAM\n");
 	icache_enable();
-
-#if defined(CONFIG_DDR_ECC_INIT_VIA_DMA)
-	/* Initialise DMA for direct Transfers */
-	dma_init();
-#endif
-
 	t_start = get_tbms();
+	pattern[0] = 0xdeadbeef;
+	pattern[1] = 0xdeadbeef;
 
 #if !defined(CONFIG_DDR_ECC_INIT_VIA_DMA)
-	debug("DDR init: Cache flush method\n");
-	for (p = 0; p < (uint *)(dram_size); p++) {
-		if (((unsigned int)p & 0x1f) == 0) {
-			ppcDcbz((unsigned long) p);
-		}
-
-		/* write pattern to cache and flush */
-		*p = (unsigned int)0xdeadbeef;
-
-		if (((unsigned int)p & 0x1c) == 0x1c) {
-			ppcDcbf((unsigned long) p);
-		}
+	debug("ddr init: CPU FP write method\n");
+	size = dram_size;
+	for (p = 0; p < (u64*)(size); p++) {
+		ppcDWstore((u32*)p, pattern);
 	}
+	__asm__ __volatile__ ("sync");
 #else
-	printf("DDR init: DMA method\n");
-	for (p = 0; p < (uint *)(8 * 1024); p++) {
-		/* zero one data cache line */
-		if (((unsigned int)p & 0x1f) == 0) {
-			ppcDcbz((unsigned long)p);
-		}
-
-		/* write pattern to it and flush */
-		*p = (unsigned int)0xdeadbeef;
-
-		if (((unsigned int)p & 0x1c) == 0x1c) {
-			ppcDcbf((unsigned long)p);
-		}
+	debug("ddr init: DMA method\n");
+	size = 0x2000;
+	for (p = 0; p < (u64*)(size); p++) {
+		ppcDWstore((u32*)p, pattern);
 	}
+	__asm__ __volatile__ ("sync");
 
+	/* Initialise DMA for direct transfer */
+	dma_init();
+	/* Start DMA to transfer */
 	dma_xfer((uint *)0x2000, 0x2000, (uint *)0); /* 8K */
 	dma_xfer((uint *)0x4000, 0x4000, (uint *)0); /* 16K */
 	dma_xfer((uint *)0x8000, 0x8000, (uint *)0); /* 32K */
-- 
cgit 


From d239d74b1c937984bc519083a8e7de373a390f06 Mon Sep 17 00:00:00 2001
From: Timur Tabi <timur@freescale.com>
Date: Fri, 3 Nov 2006 12:00:28 -0600
Subject: mpc83xx: Replace CFG_IMMRBAR with CFG_IMMR

Replace all instances of CFG_IMMRBAR with CFG_IMMR, so that the 83xx
tree matches the other 8xxx trees.

Signed-off-by: Timur Tabi <timur@freescale.com>
---
 cpu/mpc83xx/spd_sdram.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'cpu/mpc83xx/spd_sdram.c')

diff --git a/cpu/mpc83xx/spd_sdram.c b/cpu/mpc83xx/spd_sdram.c
index b91c6130e7..dc8f6790a6 100644
--- a/cpu/mpc83xx/spd_sdram.c
+++ b/cpu/mpc83xx/spd_sdram.c
@@ -112,7 +112,7 @@ static void spd_debug(spd_eeprom_t *spd)
 
 long int spd_sdram()
 {
-	volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
 	volatile ddr83xx_t *ddr = &immap->ddr;
 	volatile law83xx_t *ecm = &immap->sysconf.ddrlaw[0];
 	spd_eeprom_t spd;
@@ -562,7 +562,7 @@ static __inline__ unsigned long get_tbms (void)
 /* #define CONFIG_DDR_ECC_INIT_VIA_DMA */
 void ddr_enable_ecc(unsigned int dram_size)
 {
-	volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
 	volatile ddr83xx_t *ddr= &immap->ddr;
 	unsigned long t_start, t_end;
 	register u64 *p;
-- 
cgit 


From e857a5bdb3954b896c0920cb9d8d2b1b9c107ce5 Mon Sep 17 00:00:00 2001
From: Timur Tabi <timur@freescale.com>
Date: Tue, 28 Nov 2006 12:09:35 -0600
Subject: mpc83xx: Miscellaneous code style fixes

Implement various code style fixes and similar changes.

Signed-off-by: Timur Tabi <timur@freescale.com>
---
 cpu/mpc83xx/spd_sdram.c | 74 +++++++++++++++++++------------------------------
 1 file changed, 28 insertions(+), 46 deletions(-)

(limited to 'cpu/mpc83xx/spd_sdram.c')

diff --git a/cpu/mpc83xx/spd_sdram.c b/cpu/mpc83xx/spd_sdram.c
index dc8f6790a6..cfc42c4a83 100644
--- a/cpu/mpc83xx/spd_sdram.c
+++ b/cpu/mpc83xx/spd_sdram.c
@@ -25,15 +25,6 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
- *
- * Change log:
- *
- * 20050101: Eran Liberty (liberty@freescale.com)
- *           Initial file creating (porting from 85XX & 8260)
- * 20060601: Dave Liu (daveliu@freescale.com)
- *           DDR ECC support
- *           unify variable names for 83xx
- *           code cleanup
  */
 
 #include <common.h>
@@ -45,6 +36,8 @@
 
 #ifdef CONFIG_SPD_EEPROM
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
 extern void dma_init(void);
 extern uint dma_check(void);
@@ -58,19 +51,16 @@ extern int dma_xfer(void *dest, uint count, void *src);
 /*
  * Convert picoseconds into clock cycles (rounding up if needed).
  */
-extern ulong get_ddr_clk(ulong dummy);
-
 int
 picos_to_clk(int picos)
 {
 	unsigned int ddr_bus_clk;
 	int clks;
 
-	ddr_bus_clk = get_ddr_clk(0) >> 1;
+	ddr_bus_clk = gd->ddr_clk >> 1;
 	clks = picos / ((1000000000 / ddr_bus_clk) * 1000);
-	if (picos % ((1000000000 / ddr_bus_clk) * 1000) !=0) {
+	if (picos % ((1000000000 / ddr_bus_clk) * 1000) != 0)
 		clks++;
-	}
 
 	return clks;
 }
@@ -249,7 +239,7 @@ long int spd_sdram()
 
 	debug("DDR:Module maximum data rate is: %dMhz\n", max_data_rate);
 
-	ddrc_clk = get_ddr_clk(0) / 1000000;
+	ddrc_clk = gd->ddr_clk / 1000000;
 
 	if (max_data_rate >= 390) { /* it is DDR 400 */
 		if (ddrc_clk <= 410 && ddrc_clk > 350) {
@@ -259,31 +249,28 @@ long int spd_sdram()
 		} else if (ddrc_clk <= 350 && ddrc_clk > 280) {
 			/* DDR controller clk at 280~350 */
 			effective_data_rate = 333; /* 6ns */
-			if (spd.clk_cycle2 == 0x60) {
+			if (spd.clk_cycle2 == 0x60)
 				caslat = caslat - 1;
-			} else {
+			else
 				caslat = caslat;
-			}
 		} else if (ddrc_clk <= 280 && ddrc_clk > 230) {
 			/* DDR controller clk at 230~280 */
 			effective_data_rate = 266; /* 7.5ns */
-			if (spd.clk_cycle3 == 0x75) {
+			if (spd.clk_cycle3 == 0x75)
 				caslat = caslat - 2;
-			} else if (spd.clk_cycle2 == 0x60) {
+			else if (spd.clk_cycle2 == 0x60)
 				caslat = caslat - 1;
-			} else {
+			else
 				caslat = caslat;
-			}
 		} else if (ddrc_clk <= 230 && ddrc_clk > 90) {
 			/* DDR controller clk at 90~230 */
 			effective_data_rate = 200; /* 10ns */
-			if (spd.clk_cycle3 == 0x75) {
+			if (spd.clk_cycle3 == 0x75)
 				caslat = caslat - 2;
-			} else if (spd.clk_cycle2 == 0x60) {
+			else if (spd.clk_cycle2 == 0x60)
 				caslat = caslat - 1;
-			} else {
+			else
 				caslat = caslat;
-			}
 		}
 	} else if (max_data_rate >= 323) { /* it is DDR 333 */
 		if (ddrc_clk <= 350 && ddrc_clk > 280) {
@@ -293,21 +280,19 @@ long int spd_sdram()
 		} else if (ddrc_clk <= 280 && ddrc_clk > 230) {
 			/* DDR controller clk at 230~280 */
 			effective_data_rate = 266; /* 7.5ns */
-			if (spd.clk_cycle2 == 0x75) {
+			if (spd.clk_cycle2 == 0x75)
 				caslat = caslat - 1;
-			} else {
+			else
 				caslat = caslat;
-			}
 		} else if (ddrc_clk <= 230 && ddrc_clk > 90) {
 			/* DDR controller clk at 90~230 */
 			effective_data_rate = 200; /* 10ns */
-			if (spd.clk_cycle3 == 0xa0) {
+			if (spd.clk_cycle3 == 0xa0)
 				caslat = caslat - 2;
-			} else if (spd.clk_cycle2 == 0x75) {
+			else if (spd.clk_cycle2 == 0x75)
 				caslat = caslat - 1;
-			} else {
+			else
 				caslat = caslat;
-			}
 		}
 	} else if (max_data_rate >= 256) { /* it is DDR 266 */
 		if (ddrc_clk <= 350 && ddrc_clk > 280) {
@@ -322,9 +307,8 @@ long int spd_sdram()
 		} else if (ddrc_clk <= 230 && ddrc_clk > 90) {
 			/* DDR controller clk at 90~230 */
 			effective_data_rate = 200; /* 10ns */
-			if (spd.clk_cycle2 == 0xa0) {
+			if (spd.clk_cycle2 == 0xa0)
 				caslat = caslat - 1;
-			}
 		}
 	} else if (max_data_rate >= 190) { /* it is DDR 200 */
 		if (ddrc_clk <= 350 && ddrc_clk > 230) {
@@ -346,13 +330,13 @@ long int spd_sdram()
 	 * Errata DDR6 work around: input enable 2 cycles earlier.
 	 * including MPC834x Rev1.0/1.1 and MPC8360 Rev1.1/1.2.
 	 */
-	if (caslat == 2) {
+	if (caslat == 2)
 		ddr->debug_reg = 0x201c0000; /* CL=2 */
-	} else if (caslat == 3) {
+	else if (caslat == 3)
 		ddr->debug_reg = 0x202c0000; /* CL=2.5 */
-	} else if (caslat == 4) {
+	else if (caslat == 4)
 		ddr->debug_reg = 0x202c0000; /* CL=3.0 */
-	}
+
 	__asm__ __volatile__ ("sync");
 
 	debug("Errata DDR6 (debug_reg=0x%08x)\n", ddr->debug_reg);
@@ -392,11 +376,10 @@ long int spd_sdram()
 	}
 
 	/* Is this an ECC DDR chip? */
-	if (spd.config == 0x02) {
+	if (spd.config == 0x02)
 		printf(" with ECC\n");
-	} else {
+	else
 		printf(" without ECC\n");
-	}
 
 	/* Burst length is always 4 for 64 bit data bus, 8 for 32 bit data bus,
 	   Burst type is sequential
@@ -482,14 +465,13 @@ long int spd_sdram()
 	sdram_cfg = 0xC2000000;
 
 	/* sdram_cfg[3] = RD_EN - registered DIMM enable */
-	if (spd.mod_attr & 0x02) {
+	if (spd.mod_attr & 0x02)
 		sdram_cfg |= 0x10000000;
-	}
 
 	/* The DIMM is 32bit width */
-	if (spd.dataw_lsb == 0x20) {
+	if (spd.dataw_lsb == 0x20)
 		sdram_cfg |= 0x000C0000;
-	}
+
 	ddrc_ecc_enable = 0;
 
 #if defined(CONFIG_DDR_ECC)
-- 
cgit 


From dd520bf314c7add4183c5191692180f576f96b60 Mon Sep 17 00:00:00 2001
From: Wolfgang Denk <wd@pollux.denx.de>
Date: Thu, 30 Nov 2006 18:02:20 +0100
Subject: Code cleanup.

---
 cpu/mpc83xx/spd_sdram.c | 20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)

(limited to 'cpu/mpc83xx/spd_sdram.c')

diff --git a/cpu/mpc83xx/spd_sdram.c b/cpu/mpc83xx/spd_sdram.c
index cfc42c4a83..0d93f2e1ea 100644
--- a/cpu/mpc83xx/spd_sdram.c
+++ b/cpu/mpc83xx/spd_sdram.c
@@ -117,7 +117,7 @@ long int spd_sdram()
 	unsigned sdram_cfg;
 	unsigned int ddrc_ecc_enable;
 
-        /* Read SPD parameters with I2C */
+	/* Read SPD parameters with I2C */
 	CFG_READ_SPD(SPD_EEPROM_ADDRESS, 0, 1, (uchar *) & spd, sizeof (spd));
 #ifdef SPD_DEBUG
 	spd_debug(&spd);
@@ -147,7 +147,7 @@ long int spd_sdram()
 							 spd.ncol_addr);
 		return 0;
 	}
-        /* Setup DDR chip select register */
+	/* Setup DDR chip select register */
 #ifdef CFG_83XX_DDR_USES_CS0
 	ddr->csbnds[0].csbnds = (banksize(spd.row_dens) >> 24) - 1;
 	ddr->cs_config[0] = ( 1 << 31
@@ -218,13 +218,13 @@ long int spd_sdram()
 	 *	CAS Lat	 DDR I	   Ctrl
 	 *	Clocks	 SPD Bit   Value
 	 *	-------+--------+---------
-	 *	1.0        0        001
-	 *	1.5        1        010
-	 *	2.0        2        011
-	 *	2.5        3        100
-	 *	3.0        4        101
-	 *	3.5        5        110
-	 *	4.0        6        111
+	 *	1.0	   0	    001
+	 *	1.5	   1	    010
+	 *	2.0	   2	    011
+	 *	2.5	   3	    100
+	 *	3.0	   4	    101
+	 *	3.5	   5	    110
+	 *	4.0	   6	    111
 	 */
 	caslat = __ilog2(spd.cas_lat);
 
@@ -442,7 +442,7 @@ long int spd_sdram()
 
 	/* SS_EN = 0, source synchronous disable
 	 * CLK_ADJST = 0, MCK/MCK# is launched aligned with addr/cmd
-         */
+	 */
 	ddr->sdram_clk_cntl = 0x00000000;
 	debug("DDR:sdram_clk_cntl=0x%08x\n", ddr->sdram_clk_cntl);
 
-- 
cgit