From ff88229549e08fdd3f9127c1cc4db11a3576250f Mon Sep 17 00:00:00 2001 From: Dave Liu Date: Sat, 31 Oct 2009 07:59:55 +0800 Subject: ppc/85xx: Fix misc L2 cache enabling bug We need loop-check the flash clear lock and enable bit for L2 cache. Signed-off-by: Dave Liu Signed-off-by: Kumar Gala --- cpu/mpc85xx/release.S | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) (limited to 'cpu/mpc85xx/release.S') diff --git a/cpu/mpc85xx/release.S b/cpu/mpc85xx/release.S index a1ae78a7f5..433ff02544 100644 --- a/cpu/mpc85xx/release.S +++ b/cpu/mpc85xx/release.S @@ -102,18 +102,22 @@ __secondary_start_page: #ifdef CONFIG_BACKSIDE_L2_CACHE /* Enable/invalidate the L2 cache */ msync - lis r3,(L2CSR0_L2FI|L2CSR0_L2LFC)@h - ori r3,r3,(L2CSR0_L2FI|L2CSR0_L2LFC)@l - mtspr SPRN_L2CSR0,r3 + lis r2,(L2CSR0_L2FI|L2CSR0_L2LFC)@h + ori r2,r2,(L2CSR0_L2FI|L2CSR0_L2LFC)@l + mtspr SPRN_L2CSR0,r2 1: mfspr r3,SPRN_L2CSR0 - andis. r1,r3,L2CSR0_L2FI@h + and. r1,r3,r2 bne 1b lis r3,CONFIG_SYS_INIT_L2CSR0@h ori r3,r3,CONFIG_SYS_INIT_L2CSR0@l mtspr SPRN_L2CSR0,r3 isync +2: + mfspr r3,SPRN_L2CSR0 + andis. r1,r3,L2CSR0_L2E@h + beq 2b #endif #define EPAPR_MAGIC (0x45504150) -- cgit