From b38dbd4622a2abeedf9fcb1806958d9afac0bbd4 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Mon, 13 Mar 2006 00:46:05 +0100 Subject: Fix bug in [id]cache_status commands for MPC85xx processors; should look at LSB of L1CSRn registers to determine if L1 cache is enabled, not the MSB. Patch by Murray Jensen, 19 Jul 2005 --- cpu/mpc85xx/start.S | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'cpu/mpc85xx/start.S') diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S index 7ac65736bc..f96a4c3f8b 100644 --- a/cpu/mpc85xx/start.S +++ b/cpu/mpc85xx/start.S @@ -715,7 +715,7 @@ icache_disable: .globl icache_status icache_status: mfspr r3,L1CSR1 - srwi r3, r3, 31 /* >>31 => select bit 0 */ + andi. r3,r3,1 blr .globl dcache_enable @@ -748,7 +748,7 @@ dcache_disable: .globl dcache_status dcache_status: mfspr r3,L1CSR0 - srwi r3, r3, 31 /* >>31 => select bit 0 */ + andi. r3,r3,1 blr .globl get_pir -- cgit