From 3b9519fc50802436e417c839e69df7b2016cade5 Mon Sep 17 00:00:00 2001 From: Becky Bruce Date: Wed, 14 May 2008 13:10:04 -0500 Subject: MPC85xx: Change traps.c to not reference non-addressable memory Currently, END_OF_RAM is used by the trap code to determine if we should attempt to access the stack pointer or not. However, on systems with a lot of RAM, only a subset of the RAM is guaranteed to be mapped in and accessible. Change END_OF_RAM to use get_effective_memsize() instead of using the raw ram size out of the bd. Signed-off-by: Becky Bruce --- cpu/mpc85xx/traps.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) (limited to 'cpu/mpc85xx') diff --git a/cpu/mpc85xx/traps.c b/cpu/mpc85xx/traps.c index 2381fb0654..fd36658cb0 100644 --- a/cpu/mpc85xx/traps.c +++ b/cpu/mpc85xx/traps.c @@ -50,10 +50,12 @@ int (*debugger_exception_handler)(struct pt_regs *) = 0; extern unsigned long search_exception_table(unsigned long); /* - * End of memory as shown by board info and determined by DDR setup. + * End of addressable memory. This may be less than the actual + * amount of memory on the system if we're unable to keep all + * the memory mapped in. */ -#define END_OF_MEM (gd->bd->bi_memstart + gd->bd->bi_memsize) - +extern ulong get_effective_memsize(void); +#define END_OF_MEM (gd->bd->bi_memstart + get_effective_memsize()) static __inline__ void set_tsr(unsigned long val) { -- cgit From ee1e35bede91debc8bff9b02f75574486033b652 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 29 May 2008 01:21:24 -0500 Subject: 85xx: Only use PORPLLSR[DDR_Ratio] on platforms that define it Signed-off-by: Kumar Gala --- cpu/mpc85xx/cpu.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'cpu/mpc85xx') diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index 98733834e0..58d23f4cce 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -75,8 +75,12 @@ int checkcpu (void) uint ver; uint major, minor; int i; - u32 ddr_ratio; +#ifdef CONFIG_DDR_CLK_FREQ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); + u32 ddr_ratio = ((gur->porpllsr) & 0x00003e00) >> 9; +#else + u32 ddr_ratio = 0; +#endif svr = get_svr(); ver = SVR_SOC_VER(svr); @@ -118,7 +122,7 @@ int checkcpu (void) puts("Clock Configuration:\n"); printf(" CPU:%4lu MHz, ", DIV_ROUND_UP(sysinfo.freqProcessor,1000000)); printf("CCB:%4lu MHz,\n", DIV_ROUND_UP(sysinfo.freqSystemBus,1000000)); - ddr_ratio = ((gur->porpllsr) & 0x00003e00) >> 9; + switch (ddr_ratio) { case 0x0: printf(" DDR:%4lu MHz (%lu MT/s data rate), ", -- cgit From 4dbdb7681e243431530df0725627192a0c4aefda Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Tue, 10 Jun 2008 16:53:46 -0500 Subject: 85xx: expose cpu identification The current cpu identification code is used just to return the name of the processor at boot. There are some other locations that the name is useful (device tree setup). Expose the functionality to other bits of code. Also, drop the 'E' suffix and add it on by looking at the SVR version when we print this out. This is mainly to allow the most flexible use of the name. The device tree code tends to not care about the 'E' suffix. Signed-off-by: Kumar Gala --- cpu/mpc85xx/cpu.c | 76 +++++++++++++++++++++++++++++-------------------------- 1 file changed, 40 insertions(+), 36 deletions(-) (limited to 'cpu/mpc85xx') diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index 58d23f4cce..d585e87995 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -32,38 +32,41 @@ DECLARE_GLOBAL_DATA_PTR; -struct cpu_type { - char name[15]; - u32 soc_ver; +struct cpu_type cpu_type_list [] = { + CPU_TYPE_ENTRY(8533, 8533), + CPU_TYPE_ENTRY(8533, 8533_E), + CPU_TYPE_ENTRY(8540, 8540), + CPU_TYPE_ENTRY(8541, 8541), + CPU_TYPE_ENTRY(8541, 8541_E), + CPU_TYPE_ENTRY(8543, 8543), + CPU_TYPE_ENTRY(8543, 8543_E), + CPU_TYPE_ENTRY(8544, 8544), + CPU_TYPE_ENTRY(8544, 8544_E), + CPU_TYPE_ENTRY(8545, 8545), + CPU_TYPE_ENTRY(8545, 8545_E), + CPU_TYPE_ENTRY(8547, 8547_E), + CPU_TYPE_ENTRY(8548, 8548), + CPU_TYPE_ENTRY(8548, 8548_E), + CPU_TYPE_ENTRY(8555, 8555), + CPU_TYPE_ENTRY(8555, 8555_E), + CPU_TYPE_ENTRY(8560, 8560), + CPU_TYPE_ENTRY(8567, 8567), + CPU_TYPE_ENTRY(8567, 8567_E), + CPU_TYPE_ENTRY(8568, 8568), + CPU_TYPE_ENTRY(8568, 8568_E), + CPU_TYPE_ENTRY(8572, 8572), + CPU_TYPE_ENTRY(8572, 8572_E), }; -#define CPU_TYPE_ENTRY(x) {#x, SVR_##x} +struct cpu_type *identify_cpu(uint ver) +{ + int i; + for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++) + if (cpu_type_list[i].soc_ver == ver) + return &cpu_type_list[i]; -struct cpu_type cpu_type_list [] = { - CPU_TYPE_ENTRY(8533), - CPU_TYPE_ENTRY(8533_E), - CPU_TYPE_ENTRY(8540), - CPU_TYPE_ENTRY(8541), - CPU_TYPE_ENTRY(8541_E), - CPU_TYPE_ENTRY(8543), - CPU_TYPE_ENTRY(8543_E), - CPU_TYPE_ENTRY(8544), - CPU_TYPE_ENTRY(8544_E), - CPU_TYPE_ENTRY(8545), - CPU_TYPE_ENTRY(8545_E), - CPU_TYPE_ENTRY(8547_E), - CPU_TYPE_ENTRY(8548), - CPU_TYPE_ENTRY(8548_E), - CPU_TYPE_ENTRY(8555), - CPU_TYPE_ENTRY(8555_E), - CPU_TYPE_ENTRY(8560), - CPU_TYPE_ENTRY(8567), - CPU_TYPE_ENTRY(8567_E), - CPU_TYPE_ENTRY(8568), - CPU_TYPE_ENTRY(8568_E), - CPU_TYPE_ENTRY(8572), - CPU_TYPE_ENTRY(8572_E), -}; + return NULL; +} int checkcpu (void) { @@ -74,7 +77,7 @@ int checkcpu (void) uint fam; uint ver; uint major, minor; - int i; + struct cpu_type *cpu; #ifdef CONFIG_DDR_CLK_FREQ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); u32 ddr_ratio = ((gur->porpllsr) & 0x00003e00) >> 9; @@ -89,14 +92,15 @@ int checkcpu (void) puts("CPU: "); - for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++) - if (cpu_type_list[i].soc_ver == ver) { - puts(cpu_type_list[i].name); - break; - } + cpu = identify_cpu(ver); + if (cpu) { + puts(cpu->name); - if (i == ARRAY_SIZE(cpu_type_list)) + if (svr & 0x80000) + puts("E"); + } else { puts("Unknown"); + } printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr); -- cgit From 730b2fcf6fcd9eec3ea86fbb087c3f98aa23a769 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 29 May 2008 11:22:06 -0500 Subject: 85xx: Add setting of cache props in the device tree. Signed-off-by: Kumar Gala --- cpu/mpc85xx/fdt.c | 128 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 128 insertions(+) (limited to 'cpu/mpc85xx') diff --git a/cpu/mpc85xx/fdt.c b/cpu/mpc85xx/fdt.c index bb87740baa..92952e6d6e 100644 --- a/cpu/mpc85xx/fdt.c +++ b/cpu/mpc85xx/fdt.c @@ -26,6 +26,7 @@ #include #include #include +#include extern void ft_qe_setup(void *blob); #ifdef CONFIG_MP @@ -77,6 +78,131 @@ void ft_fixup_cpu(void *blob, u64 memory_limit) } #endif +#ifdef CONFIG_L2_CACHE +/* return size in kilobytes */ +static inline u32 l2cache_size(void) +{ + volatile ccsr_l2cache_t *l2cache = (void *)CFG_MPC85xx_L2_ADDR; + volatile u32 l2siz_field = (l2cache->l2ctl >> 28) & 0x3; + u32 ver = SVR_SOC_VER(get_svr()); + + switch (l2siz_field) { + case 0x0: + break; + case 0x1: + if (ver == SVR_8540 || ver == SVR_8560 || + ver == SVR_8541 || ver == SVR_8541_E || + ver == SVR_8555 || ver == SVR_8555_E) + return 128; + else + return 256; + break; + case 0x2: + if (ver == SVR_8540 || ver == SVR_8560 || + ver == SVR_8541 || ver == SVR_8541_E || + ver == SVR_8555 || ver == SVR_8555_E) + return 256; + else + return 512; + break; + case 0x3: + return 1024; + break; + } + + return 0; +} + +static inline void ft_fixup_l2cache(void *blob) +{ + int len, off; + u32 *ph; + struct cpu_type *cpu = identify_cpu(SVR_SOC_VER(get_svr())); + char compat_buf[38]; + + const u32 line_size = 32; + const u32 num_ways = 8; + const u32 size = l2cache_size() * 1024; + const u32 num_sets = size / (line_size * num_ways); + + off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); + if (off < 0) { + debug("no cpu node fount\n"); + return; + } + + ph = (u32 *)fdt_getprop(blob, off, "next-level-cache", 0); + + if (ph == NULL) { + debug("no next-level-cache property\n"); + return ; + } + + off = fdt_node_offset_by_phandle(blob, *ph); + if (off < 0) { + printf("%s: %s\n", __func__, fdt_strerror(off)); + return ; + } + + if (cpu) { + len = sprintf(compat_buf, "fsl,mpc%s-l2-cache-controller", + cpu->name); + sprintf(&compat_buf[len + 1], "cache"); + } + fdt_setprop(blob, off, "cache-unified", NULL, 0); + fdt_setprop_cell(blob, off, "cache-block-size", line_size); + fdt_setprop_cell(blob, off, "cache-line-size", line_size); + fdt_setprop_cell(blob, off, "cache-size", size); + fdt_setprop_cell(blob, off, "cache-sets", num_sets); + fdt_setprop_cell(blob, off, "cache-level", 2); + fdt_setprop(blob, off, "compatible", compat_buf, sizeof(compat_buf)); +} +#else +#define ft_fixup_l2cache(x) +#endif + +static inline void ft_fixup_cache(void *blob) +{ + int off; + + off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); + + while (off != -FDT_ERR_NOTFOUND) { + u32 l1cfg0 = mfspr(SPRN_L1CFG0); + u32 l1cfg1 = mfspr(SPRN_L1CFG1); + u32 isize, iline_size, inum_sets, inum_ways; + u32 dsize, dline_size, dnum_sets, dnum_ways; + + /* d-side config */ + dsize = (l1cfg0 & 0x7ff) * 1024; + dnum_ways = ((l1cfg0 >> 11) & 0xff) + 1; + dline_size = (((l1cfg0 >> 23) & 0x3) + 1) * 32; + dnum_sets = dsize / (dline_size * dnum_ways); + + fdt_setprop_cell(blob, off, "d-cache-block-size", dline_size); + fdt_setprop_cell(blob, off, "d-cache-line-size", dline_size); + fdt_setprop_cell(blob, off, "d-cache-size", dsize); + fdt_setprop_cell(blob, off, "d-cache-sets", dnum_sets); + + /* i-side config */ + isize = (l1cfg1 & 0x7ff) * 1024; + inum_ways = ((l1cfg1 >> 11) & 0xff) + 1; + iline_size = (((l1cfg1 >> 23) & 0x3) + 1) * 32; + inum_sets = isize / (iline_size * inum_ways); + + fdt_setprop_cell(blob, off, "i-cache-block-size", iline_size); + fdt_setprop_cell(blob, off, "i-cache-line-size", iline_size); + fdt_setprop_cell(blob, off, "i-cache-size", isize); + fdt_setprop_cell(blob, off, "i-cache-sets", inum_sets); + + off = fdt_node_offset_by_prop_value(blob, off, + "device_type", "cpu", 4); + } + + ft_fixup_l2cache(blob); +} + + void ft_cpu_setup(void *blob, bd_t *bd) { #if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) ||\ @@ -114,4 +240,6 @@ void ft_cpu_setup(void *blob, bd_t *bd) #ifdef CONFIG_MP ft_fixup_cpu(blob, (u64)bd->bi_memstart + (u64)bd->bi_memsize); #endif + + ft_fixup_cache(blob); } -- cgit From 6beecfbb542992eede5831240cd58678274683a9 Mon Sep 17 00:00:00 2001 From: Wolfgang Grandegger Date: Thu, 5 Jun 2008 13:11:59 +0200 Subject: MPC85xx: Beautify boot output of L2 cache configuration The boot output is now aligned poperly with other boot output lines, e.g.: FLASH: 128 MB L2: 512 KB enabled Signed-off-by: Wolfgang Grandegger --- cpu/mpc85xx/cpu.c | 2 +- cpu/mpc85xx/cpu_init.c | 18 ++++++++++-------- 2 files changed, 11 insertions(+), 9 deletions(-) (limited to 'cpu/mpc85xx') diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index d585e87995..c64bf1050b 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -167,7 +167,7 @@ int checkcpu (void) } #ifdef CONFIG_CPM2 - printf("CPM: %lu Mhz\n", sysinfo.freqSystemBus / 1000000); + printf("CPM: %lu Mhz\n", sysinfo.freqSystemBus / 1000000); #endif puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n"); diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c index e3240b519e..0fb36c4e36 100644 --- a/cpu/mpc85xx/cpu_init.c +++ b/cpu/mpc85xx/cpu_init.c @@ -265,6 +265,8 @@ int cpu_init_r(void) #endif #endif + puts ("L2: "); + #if defined(CONFIG_L2_CACHE) volatile ccsr_l2cache_t *l2cache = (void *)CFG_MPC85xx_L2_ADDR; volatile uint cache_ctl; @@ -281,17 +283,17 @@ int cpu_init_r(void) case 0x20000000: if (ver == SVR_8548 || ver == SVR_8548_E || ver == SVR_8544 || ver == SVR_8568_E) { - printf ("L2 cache 512KB:"); + puts ("512 KB "); /* set L2E=1, L2I=1, & L2SRAM=0 */ cache_ctl = 0xc0000000; } else { - printf ("L2 cache 256KB:"); + puts("256 KB "); /* set L2E=1, L2I=1, & L2BLKSZ=2 (256 Kbyte) */ cache_ctl = 0xc8000000; } break; case 0x10000000: - printf ("L2 cache 256KB:"); + puts("256 KB "); if (ver == SVR_8544 || ver == SVR_8544_E) { cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */ } @@ -299,18 +301,18 @@ int cpu_init_r(void) case 0x30000000: case 0x00000000: default: - printf ("L2 cache unknown size (0x%08x)\n", cache_ctl); + printf(" unknown size (0x%08x)\n", cache_ctl); return -1; } if (l2cache->l2ctl & 0x80000000) { - printf(" already enabled."); + puts("already enabled"); l2srbar = l2cache->l2srbar0; #ifdef CFG_INIT_L2_ADDR if (l2cache->l2ctl & 0x00010000 && l2srbar >= CFG_FLASH_BASE) { l2srbar = CFG_INIT_L2_ADDR; l2cache->l2srbar0 = l2srbar; - printf(" Moving to 0x%08x", CFG_INIT_L2_ADDR); + printf("moving to 0x%08x", CFG_INIT_L2_ADDR); } #endif /* CFG_INIT_L2_ADDR */ puts("\n"); @@ -318,10 +320,10 @@ int cpu_init_r(void) asm("msync;isync"); l2cache->l2ctl = cache_ctl; /* invalidate & enable */ asm("msync;isync"); - printf(" enabled\n"); + puts("enabled\n"); } #else - printf("L2 cache: disabled\n"); + puts("disabled\n"); #endif #ifdef CONFIG_QE uint qe_base = CFG_IMMR + 0x00080000; /* QE immr base */ -- cgit From 740280e68ccc0b971e613face7eaaa8bd1382b8c Mon Sep 17 00:00:00 2001 From: Sergei Poselenov Date: Fri, 6 Jun 2008 15:42:40 +0200 Subject: Added the upmconfig() function for 85xx. Signed-off-by: Sergei Poselenov Signed-off-by: Andy Fleming --- cpu/mpc85xx/cpu.c | 66 +++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 66 insertions(+) (limited to 'cpu/mpc85xx') diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index c64bf1050b..2b7e753ece 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -29,6 +29,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -287,3 +288,68 @@ int dma_xfer(void *dest, uint count, void *src) { return dma_check(); } #endif +/* + * Configures a UPM. Currently, the loop fields in MxMR (RLF, WLF and TLF) + * are hardcoded as "1"."size" is the number or entries, not a sizeof. + */ +void upmconfig (uint upm, uint * table, uint size) +{ + int i, mdr, mad, old_mad = 0; + volatile u32 *mxmr; + volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); + int loopval = 0x00004440; + volatile u32 *brp,*orp; + volatile u8* dummy = NULL; + int upmmask; + + switch (upm) { + case UPMA: + mxmr = &lbc->mamr; + upmmask = BR_MS_UPMA; + break; + case UPMB: + mxmr = &lbc->mbmr; + upmmask = BR_MS_UPMB; + break; + case UPMC: + mxmr = &lbc->mcmr; + upmmask = BR_MS_UPMC; + break; + default: + printf("%s: Bad UPM index %d to configure\n", __FUNCTION__, upm); + hang(); + } + + /* Find the address for the dummy write transaction */ + for (brp = &lbc->br0, orp = &lbc->or0, i = 0; i < 8; + i++, brp += 2, orp += 2) { + + /* Look for a valid BR with selected UPM */ + if ((in_be32(brp) & (BR_V | upmmask)) == (BR_V | upmmask)) { + dummy = (volatile u8*)(in_be32(brp) >> BR_BA_SHIFT); + break; + } + } + + if (i == 8) { + printf("Error: %s() could not find matching BR\n", __FUNCTION__); + hang(); + } + + for (i = 0; i < size; i++) { + /* 1 */ + out_be32(mxmr, loopval | 0x10000000 | i); /* OP_WRITE */ + /* 2 */ + out_be32(&lbc->mdr, table[i]); + /* 3 */ + mdr = in_be32(&lbc->mdr); + /* 4 */ + *(volatile u8 *)dummy = 0; + /* 5 */ + do { + mad = in_be32(mxmr) & 0x3f; + } while (mad <= old_mad && !(!mad && i == (size-1))); + old_mad = mad; + } + out_be32(mxmr, loopval); /* OP_NORMAL */ +} -- cgit From f060054dadbbe7027ca088eed806a3ef1f82fdb7 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 11 Jun 2008 00:44:10 -0500 Subject: FSL LAW: Keep track of LAW allocations Make it so we keep track of which LAWs have allocated and provide a function (set_next_law) which can allocate a LAW for us if one is free. In the future we will move to doing more "dynamic" LAW allocation since the majority of users dont really care about what LAW number they are at. Also, add CONFIG_MPC8540 or CONFIG_MPC8560 to those boards which needed them Signed-off-by: Kumar Gala Signed-off-by: Andy Fleming --- cpu/mpc85xx/cpu_init.c | 23 ++++++----------------- 1 file changed, 6 insertions(+), 17 deletions(-) (limited to 'cpu/mpc85xx') diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c index 0fb36c4e36..736aef1725 100644 --- a/cpu/mpc85xx/cpu_init.c +++ b/cpu/mpc85xx/cpu_init.c @@ -148,6 +148,12 @@ void cpu_init_early_f(void) } #endif + /* Pointer is writable since we allocated a register for it */ + gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET); + + /* Clear initial global data */ + memset ((void *) gd, 0, sizeof (gd_t)); + init_laws(); invalidate_tlb(0); init_tlbs(); @@ -168,12 +174,6 @@ void cpu_init_f (void) disable_tlb(14); disable_tlb(15); - /* Pointer is writable since we allocated a register for it */ - gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET); - - /* Clear initial global data */ - memset ((void *) gd, 0, sizeof (gd_t)); - #ifdef CONFIG_CPM2 config_8560_ioports((ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR); #endif @@ -254,17 +254,6 @@ void cpu_init_f (void) int cpu_init_r(void) { -#ifdef CONFIG_CLEAR_LAW0 -#ifdef CONFIG_FSL_LAW - disable_law(0); -#else - volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR); - - /* clear alternate boot location LAW (used for sdram, or ddr bank) */ - ecm->lawar0 = 0; -#endif -#endif - puts ("L2: "); #if defined(CONFIG_L2_CACHE) -- cgit From 859a86a25c569d3665ff413d1d923394b8a961f3 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 11 Jun 2008 00:51:45 -0500 Subject: 85xx/86xx: Move to dynamic mgmt of LAWs With the new LAW interface (set_next_law) we can move to letting the system allocate which LAWs are used for what purpose. This makes life a bit easier going forward with the new DDR code. Signed-off-by: Kumar Gala Signed-off-by: Andy Fleming Acked-by: Jon Loeliger Acked-by: Becky Bruce --- cpu/mpc85xx/spd_sdram.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'cpu/mpc85xx') diff --git a/cpu/mpc85xx/spd_sdram.c b/cpu/mpc85xx/spd_sdram.c index e3a824999c..8e321eb073 100644 --- a/cpu/mpc85xx/spd_sdram.c +++ b/cpu/mpc85xx/spd_sdram.c @@ -1090,7 +1090,7 @@ setup_laws_and_tlbs(unsigned int memsize) */ #ifdef CONFIG_FSL_LAW - set_law(1, CFG_DDR_SDRAM_BASE, law_size, LAW_TRGT_IF_DDR); + set_next_law(CFG_DDR_SDRAM_BASE, law_size, LAW_TRGT_IF_DDR); #endif /* -- cgit