From 2146cf56821c3364786ca94a7306008c5824b238 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 19 Dec 2007 01:18:15 -0600 Subject: Reworked FSL Book-E TLB macros to be more readable The old macros made it difficult to know what WIMGE and perm bits were set for a TLB entry. Actually use the bit masks for these items since they are only a single bit. Also moved the macros into mmu.h out of e500.h since they aren't specific to e500. Signed-off-by: Kumar Gala --- cpu/mpc85xx/spd_sdram.c | 23 ++++++++++------------- 1 file changed, 10 insertions(+), 13 deletions(-) (limited to 'cpu/mpc85xx') diff --git a/cpu/mpc85xx/spd_sdram.c b/cpu/mpc85xx/spd_sdram.c index 553f736a56..adc9c4dd40 100644 --- a/cpu/mpc85xx/spd_sdram.c +++ b/cpu/mpc85xx/spd_sdram.c @@ -1071,22 +1071,19 @@ setup_laws_and_tlbs(unsigned int memsize) ram_tlb_address = (unsigned int)CFG_DDR_SDRAM_BASE; while (ram_tlb_address < (memsize * 1024 * 1024) && ram_tlb_index < 16) { - mtspr(MAS0, TLB1_MAS0(1, ram_tlb_index, 0)); - mtspr(MAS1, TLB1_MAS1(1, 1, 0, 0, tlb_size)); - mtspr(MAS2, TLB1_MAS2(E500_TLB_EPN(ram_tlb_address), - 0, 0, 0, 0, 0, 0, 0, 0)); - mtspr(MAS3, TLB1_MAS3(E500_TLB_RPN(ram_tlb_address), - 0, 0, 0, 0, 0, 1, 0, 1, 0, 1)); + mtspr(MAS0, FSL_BOOKE_MAS0(1, ram_tlb_index, 0)); + mtspr(MAS1, FSL_BOOKE_MAS1(1, 1, 0, 0, tlb_size)); + mtspr(MAS2, FSL_BOOKE_MAS2(ram_tlb_address, 0)); + mtspr(MAS3, FSL_BOOKE_MAS3(ram_tlb_address, 0, + (MAS3_SX|MAS3_SW|MAS3_SR))); asm volatile("isync;msync;tlbwe;isync"); - debug("DDR: MAS0=0x%08x\n", TLB1_MAS0(1, ram_tlb_index, 0)); - debug("DDR: MAS1=0x%08x\n", TLB1_MAS1(1, 1, 0, 0, tlb_size)); - debug("DDR: MAS2=0x%08x\n", - TLB1_MAS2(E500_TLB_EPN(ram_tlb_address), - 0, 0, 0, 0, 0, 0, 0, 0)); + debug("DDR: MAS0=0x%08x\n", FSL_BOOKE_MAS0(1, ram_tlb_index, 0)); + debug("DDR: MAS1=0x%08x\n", FSL_BOOKE_MAS1(1, 1, 0, 0, tlb_size)); + debug("DDR: MAS2=0x%08x\n", FSL_BOOKE_MAS2(ram_tlb_address, 0)); debug("DDR: MAS3=0x%08x\n", - TLB1_MAS3(E500_TLB_RPN(ram_tlb_address), - 0, 0, 0, 0, 0, 1, 0, 1, 0, 1)); + FSL_BOOKE_MAS3(ram_tlb_address, 0, + (MAS3_SX|MAS3_SW|MAS3_SR))); ram_tlb_address += (0x1000 << ((tlb_size - 1) * 2)); ram_tlb_index++; -- cgit From b009f3eca99bb7b9e6ba6639a8909a138dd5e9fe Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Tue, 8 Jan 2008 01:22:21 -0600 Subject: 85xx: Remove cache config from configs.h Either use the standard defines in asm/cache.h or grab the information at runtime from the L1CFG SPR. Also, minor cleanup in cache.h to make the code a bit more readable. Signed-off-by: Kumar Gala --- cpu/mpc85xx/start.S | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) (limited to 'cpu/mpc85xx') diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S index b769ef8a76..b489d2ff0c 100644 --- a/cpu/mpc85xx/start.S +++ b/cpu/mpc85xx/start.S @@ -268,7 +268,10 @@ _start_e500: */ lis r3,CFG_INIT_RAM_ADDR@h ori r3,r3,CFG_INIT_RAM_ADDR@l - li r2,(CFG_DCACHE_SIZE / (2 * CFG_CACHELINE_SIZE)) + mfspr r2, L1CFG0 + andi. r2, r2, 0x1ff + /* cache size * 1024 / (2 * L1 line size) */ + slwi r2, r2, (10 - 1 - L1_CACHE_SHIFT) mtctr r2 li r0,0 1: @@ -1061,7 +1064,9 @@ unlock_ram_in_cache: /* invalidate the INIT_RAM section */ lis r3,(CFG_INIT_RAM_ADDR & ~31)@h ori r3,r3,(CFG_INIT_RAM_ADDR & ~31)@l - li r4,(CFG_DCACHE_SIZE / (2 * CFG_CACHELINE_SIZE)) + mfspr r4,L1CFG0 + andi. r4,r4,0x1ff + slwi r4,r4,(10 - 1 - L1_CACHE_SHIFT) mtctr r4 1: icbi r0,r3 dcbi r0,r3 -- cgit From b8ec2385038c094b07ec5b49336289a46b6e9cc6 Mon Sep 17 00:00:00 2001 From: Timur Tabi Date: Mon, 7 Jan 2008 13:31:19 -0600 Subject: 85xx: add ability to upload QE firmware Define the layout of a binary blob that contains a QE firmware and instructions on how to upload it. Add function qe_upload_firmware() to parse the blob and perform the actual upload. Add command-line command "qe fw" to take a firmware blob in memory and upload it. Update ft_cpu_setup() on 85xx to create the 'firmware' device tree node if U-Boot has uploaded a firmware. Fully define 'struct rsp' in immap_qe.h to include the actual RISC Special Registers. Signed-off-by: Timur Tabi --- cpu/mpc85xx/fdt.c | 1 + 1 file changed, 1 insertion(+) (limited to 'cpu/mpc85xx') diff --git a/cpu/mpc85xx/fdt.c b/cpu/mpc85xx/fdt.c index 737a6c485a..0812c89a2e 100644 --- a/cpu/mpc85xx/fdt.c +++ b/cpu/mpc85xx/fdt.c @@ -45,6 +45,7 @@ void ft_cpu_setup(void *blob, bd_t *bd) #ifdef CONFIG_QE do_fixup_by_prop_u32(blob, "device_type", "soc", 4, "bus-frequency", bd->bi_busfreq, 1); + fdt_fixup_qe_firmware(blob); #endif #ifdef CFG_NS16550 -- cgit From 17a41e4492121ccf9fa2c10c2cb1a6d1c18d74f7 Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Wed, 9 Jan 2008 16:56:54 -0600 Subject: Add QE brg freq and correct qe bus freq fdt update code Signed-off-by: Kim Phillips Signed-off-by: Andy Fleming --- cpu/mpc85xx/fdt.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'cpu/mpc85xx') diff --git a/cpu/mpc85xx/fdt.c b/cpu/mpc85xx/fdt.c index 0812c89a2e..0ce17e7f57 100644 --- a/cpu/mpc85xx/fdt.c +++ b/cpu/mpc85xx/fdt.c @@ -43,8 +43,10 @@ void ft_cpu_setup(void *blob, bd_t *bd) do_fixup_by_prop_u32(blob, "device_type", "soc", 4, "bus-frequency", bd->bi_busfreq, 1); #ifdef CONFIG_QE - do_fixup_by_prop_u32(blob, "device_type", "soc", 4, + do_fixup_by_prop_u32(blob, "device_type", "qe", 4, "bus-frequency", bd->bi_busfreq, 1); + do_fixup_by_prop_u32(blob, "device_type", "qe", 4, + "brg-frequency", bd->bi_busfreq / 2, 1); fdt_fixup_qe_firmware(blob); #endif -- cgit