From 5ab884b254ca2e707ab50545cd705f30108cf491 Mon Sep 17 00:00:00 2001 From: "Lawrence R. Johnson" Date: Thu, 3 Jan 2008 18:54:00 -0500 Subject: ppc4xx: Add functionality to GPIO support This patch makes two additions to GPIO support: First, it adds function gpio_read_in_bit() to read the a bit from the GPIO Input Register (GPIOx_IR) in the same way that function gpio_read_out_bit() reads a bit from the GPIO Output Register (GPIOx_OR). Second, it modifies function gpio_set_chip_configuration() to provide an additional option for configuring the GPIO from the "CFG_4xx_GPIO_TABLE". According to the 440EPx User's Manual, when an alternate output is used, the three-state control is configured in one of two ways, depending on the particular output. The first option is to select the corresponding alternate three-state control in the GPIOx_TRSH/L registers. The second option is to select the GPIO Three-State Control Register (GPIOx_TCR) in the GPIOx_TRSH/L registers, and set the corresponding bit in the GPIOx_TCR register to enable the output. For example, the Manual specifies configuring the GPIO00 Alternate 1 Signal (PreAddr07) to use the alternate three-state control (first option), and specifies configuring the GPIO32 Alternate 1 Signal (USB2OM0) with the output enabled in the GPIOx_TCR register (second option). Currently, gpio_set_chip_configuration() configures all alternate signal outputs to use the first option. This patch allow the second option to be selected by setting the "out_val" element in the table entry to "GPIO_OUT_1". The first option is used when the "out_val" element is set to "GPIO_OUT_0". Because "out_val" is not currently used when an alternate signal is selected, and because all current GPIO tables set "out_val" to "GPIO_OUT_0" for all alternate signals, this patch should not change any existing configurations. Signed-off-by: Larry Johnson --- cpu/ppc4xx/gpio.c | 63 +++++++++++++++++++++++++++++++++++-------------------- 1 file changed, 40 insertions(+), 23 deletions(-) (limited to 'cpu') diff --git a/cpu/ppc4xx/gpio.c b/cpu/ppc4xx/gpio.c index 7b09a2f7d3..37d3fa8ef7 100644 --- a/cpu/ppc4xx/gpio.c +++ b/cpu/ppc4xx/gpio.c @@ -27,7 +27,7 @@ #include #if defined(CFG_4xx_GPIO_TABLE) -gpio_param_s gpio_tab[GPIO_GROUP_MAX][GPIO_MAX] = CFG_4xx_GPIO_TABLE; +gpio_param_s const gpio_tab[GPIO_GROUP_MAX][GPIO_MAX] = CFG_4xx_GPIO_TABLE; #endif #if defined(GPIO0_OSRL) @@ -120,6 +120,18 @@ int gpio_read_out_bit(int pin) return (in_be32((void *)GPIO0_OR + offs) & GPIO_VAL(pin) ? 1 : 0); } +int gpio_read_in_bit(int pin) +{ + u32 offs = 0; + + if (pin >= GPIO_MAX) { + offs = 0x100; + pin -= GPIO_MAX; + } + + return (in_be32((void *)GPIO0_IR + offs) & GPIO_VAL(pin) ? 1 : 0); +} + #if defined(CFG_4xx_GPIO_TABLE) void gpio_set_chip_configuration(void) { @@ -171,6 +183,8 @@ void gpio_set_chip_configuration(void) if ((gpio_tab[gpio_core][i].in_out == GPIO_OUT) || (gpio_tab[gpio_core][i].in_out == GPIO_BI)) { + u32 gpio_alt_sel = 0; + switch (gpio_tab[gpio_core][i].alt_nb) { case GPIO_SEL: /* @@ -199,37 +213,40 @@ void gpio_set_chip_configuration(void) break; case GPIO_ALT1: - reg = in_be32((void *)GPIO_OS(core_add+offs)) - & ~(GPIO_MASK >> (j*2)); - reg = reg | (GPIO_ALT1_SEL >> (j*2)); - out_be32((void *)GPIO_OS(core_add+offs), reg); - reg = in_be32((void *)GPIO_TS(core_add+offs)) - & ~(GPIO_MASK >> (j*2)); - reg = reg | (GPIO_ALT1_SEL >> (j*2)); - out_be32((void *)GPIO_TS(core_add+offs), reg); + gpio_alt_sel = GPIO_ALT1_SEL; break; case GPIO_ALT2: - reg = in_be32((void *)GPIO_OS(core_add+offs)) - & ~(GPIO_MASK >> (j*2)); - reg = reg | (GPIO_ALT2_SEL >> (j*2)); - out_be32((void *)GPIO_OS(core_add+offs), reg); - reg = in_be32((void *)GPIO_TS(core_add+offs)) - & ~(GPIO_MASK >> (j*2)); - reg = reg | (GPIO_ALT2_SEL >> (j*2)); - out_be32((void *)GPIO_TS(core_add+offs), reg); + gpio_alt_sel = GPIO_ALT2_SEL; break; case GPIO_ALT3: + gpio_alt_sel = GPIO_ALT3_SEL; + break; + } + + if (0 != gpio_alt_sel) { reg = in_be32((void *)GPIO_OS(core_add+offs)) & ~(GPIO_MASK >> (j*2)); - reg = reg | (GPIO_ALT3_SEL >> (j*2)); + reg = reg | (gpio_alt_sel >> (j*2)); out_be32((void *)GPIO_OS(core_add+offs), reg); - reg = in_be32((void *)GPIO_TS(core_add+offs)) - & ~(GPIO_MASK >> (j*2)); - reg = reg | (GPIO_ALT3_SEL >> (j*2)); - out_be32((void *)GPIO_TS(core_add+offs), reg); - break; + + if (gpio_tab[gpio_core][i].out_val == GPIO_OUT_1) { + reg = in_be32((void *)GPIO_TCR(core_add)) + | (0x80000000 >> (i)); + out_be32((void *)GPIO_TCR(core_add), reg); + reg = in_be32((void *)GPIO_TS(core_add+offs)) + & ~(GPIO_MASK >> (j*2)); + out_be32((void *)GPIO_TS(core_add+offs), reg); + } else { + reg = in_be32((void *)GPIO_TCR(core_add)) + & ~(0x80000000 >> (i)); + out_be32((void *)GPIO_TCR(core_add), reg); + reg = in_be32((void *)GPIO_TS(core_add+offs)) + & ~(GPIO_MASK >> (j*2)); + reg = reg | (gpio_alt_sel >> (j*2)); + out_be32((void *)GPIO_TS(core_add+offs), reg); + } } } } -- cgit From 845c6c95dbfe6c915ce68a0a115852fa17932fb4 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Sat, 5 Jan 2008 09:12:41 +0100 Subject: ppc4xx: Update Katmai/44x_spd_ddr2.c code for optimal DDR2 setup On Katmai the complete auto-calibration somehow doesn't seem to produce the best results, meaning optimal values for RQFD/RFFD. This was discovered by GDA using a high bandwidth scope, analyzing the DDR2 signals. GDA provided a fixed value for RQFD, so now on Katmai "only" RFFD is auto-calibrated. This patch also adds RDCC calibration as mentioned on page 7 of the AMCC PowerPC440SP/SPe DDR2 application note: "DDR1/DDR2 Initialization Sequence and Dynamic Tuning" Signed-off-by: Stefan Roese --- cpu/ppc4xx/44x_spd_ddr2.c | 52 +++++++++++++++++++++++++++++++++-------------- 1 file changed, 37 insertions(+), 15 deletions(-) (limited to 'cpu') diff --git a/cpu/ppc4xx/44x_spd_ddr2.c b/cpu/ppc4xx/44x_spd_ddr2.c index e19929437e..2475ed95ec 100644 --- a/cpu/ppc4xx/44x_spd_ddr2.c +++ b/cpu/ppc4xx/44x_spd_ddr2.c @@ -3,7 +3,7 @@ * This SPD SDRAM detection code supports AMCC PPC44x cpu's with a * DDR2 controller (non Denali Core). Those are 440SP/SPe. * - * (C) Copyright 2007 + * (C) Copyright 2007-2008 * Stefan Roese, DENX Software Engineering, sr@denx.de. * * COPYRIGHT AMCC CORPORATION 2004 @@ -2409,17 +2409,10 @@ static void program_DQS_calibration(unsigned long *dimm_populated, * Read sample cycle auto-update enable *-----------------------------------------------------------------*/ - /* - * Modified for the Katmai platform: with some DIMMs, the DDR2 - * controller automatically selects the T2 read cycle, but this - * proves unreliable. Go ahead and force the DDR2 controller - * to use the T4 sample and disable the automatic update of the - * RDSS field. - */ mfsdram(SDRAM_RDCC, val); mtsdram(SDRAM_RDCC, (val & ~(SDRAM_RDCC_RDSS_MASK | SDRAM_RDCC_RSAE_MASK)) - | (SDRAM_RDCC_RDSS_T4 | SDRAM_RDCC_RSAE_DISABLE)); + | SDRAM_RDCC_RSAE_ENABLE); /*------------------------------------------------------------------ * Program RQDC register @@ -2512,10 +2505,7 @@ static void DQS_calibration_process(void) { unsigned long rfdc_reg; unsigned long rffd; - unsigned long rqdc_reg; - unsigned long rqfd; unsigned long val; - long rqfd_average; long rffd_average; long max_start; long min_end; @@ -2533,10 +2523,14 @@ static void DQS_calibration_process(void) long max_end; unsigned char fail_found; unsigned char pass_found; +#if !defined(CONFIG_DDR_RQDC_FIXED) + u32 rqdc_reg; + u32 rqfd; u32 rqfd_start; + u32 rqfd_average; + int loopi = 0; char str[] = "Auto calibration -"; char slash[] = "\\|/-\\|/-"; - int loopi = 0; /*------------------------------------------------------------------ * Test to determine the best read clock delay tuning bits. @@ -2571,6 +2565,16 @@ calibration_loop: mfsdram(SDRAM_RQDC, rqdc_reg); mtsdram(SDRAM_RQDC, (rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) | SDRAM_RQDC_RQFD_ENCODE(rqfd_start)); +#else /* CONFIG_DDR_RQDC_FIXED */ + /* + * On Katmai the complete auto-calibration somehow doesn't seem to + * produce the best results, meaning optimal values for RQFD/RFFD. + * This was discovered by GDA using a high bandwidth scope, + * analyzing the DDR2 signals. GDA provided a fixed value for RQFD, + * so now on Katmai "only" RFFD is auto-calibrated. + */ + mtsdram(SDRAM_RQDC, CONFIG_DDR_RQDC_FIXED); +#endif /* CONFIG_DDR_RQDC_FIXED */ max_start = 0; min_end = 0; @@ -2655,6 +2659,7 @@ calibration_loop: /* now fix RFDC[RFFD] found and find RQDC[RQFD] */ mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd_average)); +#if !defined(CONFIG_DDR_RQDC_FIXED) max_pass_length = 0; max_start = 0; max_end = 0; @@ -2727,8 +2732,6 @@ calibration_loop: spd_ddr_init_hang (); } - blank_string(strlen(str)); - if (rqfd_average < 0) rqfd_average = 0; @@ -2739,12 +2742,31 @@ calibration_loop: (rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) | SDRAM_RQDC_RQFD_ENCODE(rqfd_average)); + blank_string(strlen(str)); +#endif /* CONFIG_DDR_RQDC_FIXED */ + + /* + * Now complete RDSS configuration as mentioned on page 7 of the AMCC + * PowerPC440SP/SPe DDR2 application note: + * "DDR1/DDR2 Initialization Sequence and Dynamic Tuning" + */ + mfsdram(SDRAM_RTSR, val); + if ((val & SDRAM_RTSR_TRK1SM_MASK) == SDRAM_RTSR_TRK1SM_ATPLS1) { + mfsdram(SDRAM_RDCC, val); + if ((val & SDRAM_RDCC_RDSS_MASK) != SDRAM_RDCC_RDSS_T4) { + val += 0x40000000; + mtsdram(SDRAM_RDCC, val); + } + } + mfsdram(SDRAM_DLCR, val); debug("%s[%d] DLCR: 0x%08X\n", __FUNCTION__, __LINE__, val); mfsdram(SDRAM_RQDC, val); debug("%s[%d] RQDC: 0x%08X\n", __FUNCTION__, __LINE__, val); mfsdram(SDRAM_RFDC, val); debug("%s[%d] RFDC: 0x%08X\n", __FUNCTION__, __LINE__, val); + mfsdram(SDRAM_RDCC, val); + debug("%s[%d] RDCC: 0x%08X\n", __FUNCTION__, __LINE__, val); } #else /* calibration test with hardvalues */ /*-----------------------------------------------------------------------------+ -- cgit From 5ba576c01602fd328800a427964c36a0a05c5dce Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Sat, 5 Jan 2008 09:13:46 +0100 Subject: ppc4xx: Remove unused CONFIG_ECC_ERROR_RESET from 44x_spd_ddr2.c Signed-off-by: Stefan Roese --- cpu/ppc4xx/44x_spd_ddr2.c | 44 -------------------------------------------- 1 file changed, 44 deletions(-) (limited to 'cpu') diff --git a/cpu/ppc4xx/44x_spd_ddr2.c b/cpu/ppc4xx/44x_spd_ddr2.c index 2475ed95ec..3ac2cdcf7f 100644 --- a/cpu/ppc4xx/44x_spd_ddr2.c +++ b/cpu/ppc4xx/44x_spd_ddr2.c @@ -111,8 +111,6 @@ #define NUMMEMWORDS 8 #define NUMLOOPS 64 /* memory test loops */ -#undef CONFIG_ECC_ERROR_RESET /* test-only: see description below, at check_ecc() */ - /* * This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory * region. Right now the cache should still be disabled in U-Boot because of the @@ -2268,39 +2266,6 @@ static void program_ecc(unsigned long *dimm_populated, return; } -#ifdef CONFIG_ECC_ERROR_RESET -/* - * Check for ECC errors and reset board upon any error here - * - * On the Katmai 440SPe eval board, from time to time, the first - * lword write access after DDR2 initializazion with ECC checking - * enabled, leads to an ECC error. I couldn't find a configuration - * without this happening. On my board with the current setup it - * happens about 1 from 10 times. - * - * The ECC modules used for testing are: - * - Kingston ValueRAM KVR667D2E5/512 (tested with 1 and 2 DIMM's) - * - * This has to get fixed for the Katmai and tested for the other - * board (440SP/440SPe) that will eventually use this code in the - * future. - * - * 2007-03-01, sr - */ -static void check_ecc(void) -{ - u32 val; - - mfsdram(SDRAM_ECCCR, val); - if (val != 0) { - printf("\nECC error: MCIF0_ECCES=%08lx MQ0_ESL=%08lx address=%08lx\n", - val, mfdcr(0x4c), mfdcr(0x4e)); - printf("ECC error occured, resetting board...\n"); - do_reset(NULL, 0, 0, NULL); - } -} -#endif - static void wait_ddr_idle(void) { u32 val; @@ -2375,15 +2340,6 @@ static void program_ecc_addr(unsigned long start_address, sync(); eieio(); wait_ddr_idle(); - -#ifdef CONFIG_ECC_ERROR_RESET - /* - * One write to 0 is enough to trigger this ECC error - * (see description above) - */ - out_be32(0, 0x12345678); - check_ecc(); -#endif } } #endif -- cgit From e05329516a13616b53240cd85b739217c2bf87f1 Mon Sep 17 00:00:00 2001 From: Larry Johnson Date: Fri, 4 Jan 2008 13:27:02 -0500 Subject: ppc4xx: Remove weak binding from common Denali data-eye search code Now that there are no board-specific versions of "denali_core_search_data_eye()", the weak binding on the common version can be removed. Signed-off-by: Larry Johnson --- cpu/ppc4xx/denali_data_eye.c | 7 ------- 1 file changed, 7 deletions(-) (limited to 'cpu') diff --git a/cpu/ppc4xx/denali_data_eye.c b/cpu/ppc4xx/denali_data_eye.c index 6c949a0fe1..967e61bd41 100644 --- a/cpu/ppc4xx/denali_data_eye.c +++ b/cpu/ppc4xx/denali_data_eye.c @@ -99,14 +99,7 @@ static int wait_for_dram_init_complete(void) /*-----------------------------------------------------------------------------+ * denali_core_search_data_eye. +----------------------------------------------------------------------------*/ -/* - * Avoid conflict with implementations of denali_core_search_data_eye in board- - * specific code. - */ void denali_core_search_data_eye(void) - __attribute__ ((weak, alias("__denali_core_search_data_eye"))); - -void __denali_core_search_data_eye(void) { int k, j; u32 val; -- cgit