From 6876609446980c3055bbd32c195a63330e21d8e6 Mon Sep 17 00:00:00 2001 From: wdenk Date: Thu, 29 Jan 2004 09:22:58 +0000 Subject: * Implement adaptive SDRAM timing configuration based on actual CPU clock frequency for INCA-IP; fix problem with board hanging when switching from 150MHz to 100MHz * Add PCMCIA CS support for BMS2003 board --- doc/README.MPC866 | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) create mode 100644 doc/README.MPC866 (limited to 'doc/README.MPC866') diff --git a/doc/README.MPC866 b/doc/README.MPC866 new file mode 100644 index 0000000000..1464a408ca --- /dev/null +++ b/doc/README.MPC866 @@ -0,0 +1,19 @@ +The current implementation allows the user to specify the desired CPU +clock value, in MHz, via an environment variable "cpuclk". + +Three compile-time constants are used: + + CFG_866_OSCCLK - input quartz clock + CFG_866_CPUCLK_MIN - minimum allowed CPU clock + CFG_866_CPUCLK_MAX - maximum allowed CPU clock + CFG_866_CPUCLK_DEFAULT - default CPU clock value + +If the "cpuclk" environment variable value is within the CPUCLK_MIN / +CPUCLK_MAX limits, the specified value is used. Otherwise, the +default CPU clock value is set. + +Please note that for now the new clock-handling code has been enabled +for the TQM866M board only, even though it should be pretty much +common for other MPC859 / MPC866 based boards also. Our intention +here was to move in small steps and not to break the existing code +for other boards. -- cgit