From 9dc054bb442f900c5d40c964110c5ba3247c2983 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Thu, 18 Jul 2019 00:34:05 -0700 Subject: doc: board: Add Intel Crown Bay board doc This extracts Intel Crown Bay board specific information from README.x86, converts plain text documentation to reST format and adds it to Sphinx TOC tree. No essential content change. Signed-off-by: Bin Meng --- doc/board/intel/crownbay.rst | 43 +++++++++++++++++++++++++++++++++++++++++++ doc/board/intel/index.rst | 9 +++++++++ 2 files changed, 52 insertions(+) create mode 100644 doc/board/intel/crownbay.rst create mode 100644 doc/board/intel/index.rst (limited to 'doc/board/intel') diff --git a/doc/board/intel/crownbay.rst b/doc/board/intel/crownbay.rst new file mode 100644 index 0000000000..4fcf9811c1 --- /dev/null +++ b/doc/board/intel/crownbay.rst @@ -0,0 +1,43 @@ +.. SPDX-License-Identifier: GPL-2.0+ +.. sectionauthor:: Bin Meng + +Crown Bay CRB +============= + +U-Boot support of Intel `Crown Bay`_ board relies on a binary blob called +Firmware Support Package (`FSP`_) to perform all the necessary initialization +steps as documented in the BIOS Writer Guide, including initialization of the +CPU, memory controller, chipset and certain bus interfaces. + +Download the Intel FSP for Atom E6xx series and Platform Controller Hub EG20T, +install it on your host and locate the FSP binary blob. Note this platform +also requires a Chipset Micro Code (CMC) state machine binary to be present in +the SPI flash where u-boot.rom resides, and this CMC binary blob can be found +in this FSP package too. + + * ./FSP/QUEENSBAY_FSP_GOLD_001_20-DECEMBER-2013.fd + * ./Microcode/C0_22211.BIN + +Rename the first one to fsp.bin and second one to cmc.bin and put them in the +board directory. + +Note the FSP release version 001 has a bug which could cause random endless +loop during the FspInit call. This bug was published by Intel although Intel +did not describe any details. We need manually apply the patch to the FSP +binary using any hex editor (eg: bvi). Go to the offset 0x1fcd8 of the FSP +binary, change the following five bytes values from orginally E8 42 FF FF FF +to B8 00 80 0B 00. + +As for the video ROM, you need manually extract it from the Intel provided +BIOS for Crown Bay `here`_, using the AMI `MMTool`_. Check PCI option +ROM ID 8086:4108, extract and save it as vga.bin in the board directory. + +Now you can build U-Boot and obtain u-boot.rom:: + + $ make crownbay_defconfig + $ make all + +.. _`Crown Bay`: http://www.intel.com/content/www/us/en/embedded/design-tools/evaluation-platforms/atom-e660-eg20t-development-kit.html +.. _`FSP`: http://www.intel.com/fsp +.. _`here`: http://www.intel.com/content/www/us/en/secure/intelligent-systems/privileged/e6xx-35-b1-cmc22211.html +.. _`MMTool`: http://www.ami.com/products/bios-uefi-tools-and-utilities/bios-uefi-utilities/ diff --git a/doc/board/intel/index.rst b/doc/board/intel/index.rst new file mode 100644 index 0000000000..93b8ba26aa --- /dev/null +++ b/doc/board/intel/index.rst @@ -0,0 +1,9 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Intel +===== + +.. toctree:: + :maxdepth: 2 + + crownbay -- cgit From 14afa22e25a62c13da9456cee89ab1fb661e7266 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Thu, 18 Jul 2019 00:34:06 -0700 Subject: doc: board: Add Intel Bay Trail based board docs This extracts Intel Bay Trail based board specific information from README.x86, converts plain text documentation to reST format and adds them to Sphinx TOC tree. No essential content change. Signed-off-by: Bin Meng --- doc/board/intel/bayleybay.rst | 29 ++++++++++++++++++ doc/board/intel/index.rst | 2 ++ doc/board/intel/minnowmax.rst | 70 +++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 101 insertions(+) create mode 100644 doc/board/intel/bayleybay.rst create mode 100644 doc/board/intel/minnowmax.rst (limited to 'doc/board/intel') diff --git a/doc/board/intel/bayleybay.rst b/doc/board/intel/bayleybay.rst new file mode 100644 index 0000000000..db97f645fd --- /dev/null +++ b/doc/board/intel/bayleybay.rst @@ -0,0 +1,29 @@ +.. SPDX-License-Identifier: GPL-2.0+ +.. sectionauthor:: Bin Meng + +Bayley Bay CRB +============== + +This uses as FSP as with Crown Bay, except it is for the Atom E3800 series. +Download this and get the .fd file (BAYTRAIL_FSP_GOLD_003_16-SEP-2014.fd at +the time of writing). Put it in the corresponding board directory and rename +it to fsp.bin. + +Obtain the VGA RAM (Vga.dat at the time of writing) and put it into the same +board directory as vga.bin. + +You still need two more binary blobs. For Bayley Bay, they can be extracted +from the sample SPI image provided in the FSP (SPI.bin at the time of writing):: + + $ ./tools/ifdtool -x BayleyBay/SPI.bin + $ cp flashregion_0_flashdescriptor.bin board/intel/bayleybay/descriptor.bin + $ cp flashregion_2_intel_me.bin board/intel/bayleybay/me.bin + +Now you can build U-Boot and obtain u-boot.rom:: + + $ make bayleybay_defconfig + $ make all + +Note that the debug version of the FSP is bigger in size. If this version +is used, CONFIG_FSP_ADDR needs to be configured to 0xfffb0000 instead of +the default value 0xfffc0000. diff --git a/doc/board/intel/index.rst b/doc/board/intel/index.rst index 93b8ba26aa..af24760b78 100644 --- a/doc/board/intel/index.rst +++ b/doc/board/intel/index.rst @@ -6,4 +6,6 @@ Intel .. toctree:: :maxdepth: 2 + bayleybay crownbay + minnowmax diff --git a/doc/board/intel/minnowmax.rst b/doc/board/intel/minnowmax.rst new file mode 100644 index 0000000000..028121735a --- /dev/null +++ b/doc/board/intel/minnowmax.rst @@ -0,0 +1,70 @@ +.. SPDX-License-Identifier: GPL-2.0+ +.. sectionauthor:: Simon Glass + +Minnowboard MAX +=============== + +This uses as FSP as with Crown Bay, except it is for the Atom E3800 series. +Download this and get the .fd file (BAYTRAIL_FSP_GOLD_003_16-SEP-2014.fd at +the time of writing). Put it in the corresponding board directory and rename +it to fsp.bin. + +Obtain the VGA RAM (Vga.dat at the time of writing) and put it into the same +board directory as vga.bin. + +You still need two more binary blobs. For Minnowboard MAX, we can reuse the +same ME firmware above, but for flash descriptor, we need get that somewhere +else, as the one above does not seem to work, probably because it is not +designed for the Minnowboard MAX. Now download the original firmware image +for this board from: + + * http://firmware.intel.com/sites/default/files/2014-WW42.4-MinnowBoardMax.73-64-bit.bin_Release.zip + +Unzip it:: + + $ unzip 2014-WW42.4-MinnowBoardMax.73-64-bit.bin_Release.zip + +Use ifdtool in the U-Boot tools directory to extract the images from that +file, for example:: + + $ ./tools/ifdtool -x MNW2MAX1.X64.0073.R02.1409160934.bin + +This will provide the descriptor file - copy this into the correct place:: + + $ cp flashregion_0_flashdescriptor.bin board/intel/minnowmax/descriptor.bin + +Now you can build U-Boot and obtain u-boot.rom:: + + $ make minnowmax_defconfig + $ make all + +Checksums are as follows (but note that newer versions will invalidate this):: + + $ md5sum -b board/intel/minnowmax/*.bin + ffda9a3b94df5b74323afb328d51e6b4 board/intel/minnowmax/descriptor.bin + 69f65b9a580246291d20d08cbef9d7c5 board/intel/minnowmax/fsp.bin + 894a97d371544ec21de9c3e8e1716c4b board/intel/minnowmax/me.bin + a2588537da387da592a27219d56e9962 board/intel/minnowmax/vga.bin + +The ROM image is broken up into these parts: + +====== ================== ============================ +Offset Description Controlling config +====== ================== ============================ +000000 descriptor.bin Hard-coded to 0 in ifdtool +001000 me.bin Set by the descriptor +500000 +6ef000 Environment CONFIG_ENV_OFFSET +6f0000 MRC cache CONFIG_ENABLE_MRC_CACHE +700000 u-boot-dtb.bin CONFIG_SYS_TEXT_BASE +7b0000 vga.bin CONFIG_VGA_BIOS_ADDR +7c0000 fsp.bin CONFIG_FSP_ADDR +7f8000 (depends on size of fsp.bin) +7ff800 U-Boot 16-bit boot CONFIG_SYS_X86_START16 +====== ================== ============================ + +Overall ROM image size is controlled by CONFIG_ROM_SIZE. + +Note that the debug version of the FSP is bigger in size. If this version +is used, CONFIG_FSP_ADDR needs to be configured to 0xfffb0000 instead of +the default value 0xfffc0000. -- cgit From 5656d04537a9d047aee66683200d909b7e0cfc04 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Thu, 18 Jul 2019 00:34:07 -0700 Subject: doc: board: Add Intel Cherry Hill board doc This extracts Intel Cherry Hill board specific information from README.x86, converts plain text documentation to reST format and adds it to Sphinx TOC tree. No essential content change. Signed-off-by: Bin Meng --- doc/board/intel/cherryhill.rst | 30 ++++++++++++++++++++++++++++++ doc/board/intel/index.rst | 1 + 2 files changed, 31 insertions(+) create mode 100644 doc/board/intel/cherryhill.rst (limited to 'doc/board/intel') diff --git a/doc/board/intel/cherryhill.rst b/doc/board/intel/cherryhill.rst new file mode 100644 index 0000000000..151f0613f8 --- /dev/null +++ b/doc/board/intel/cherryhill.rst @@ -0,0 +1,30 @@ +.. SPDX-License-Identifier: GPL-2.0+ +.. sectionauthor:: Bin Meng + +Cherry Hill CRB +=============== + +This uses Intel FSP for Braswell platform. Download it from Intel FSP website, +put the .fd file to the board directory and rename it to fsp.bin. + +Extract descriptor.bin and me.bin from the original BIOS on the board using +ifdtool and put them to the board directory as well. + +Note the FSP package for Braswell does not ship a traditional legacy VGA BIOS +image for the integrated graphics device. Instead a new binary called Video +BIOS Table (VBT) is shipped. Put it to the board directory and rename it to +vbt.bin if you want graphics support in U-Boot. + +Now you can build U-Boot and obtain u-boot.rom:: + + $ make cherryhill_defconfig + $ make all + +An important note for programming u-boot.rom to the on-board SPI flash is that +you need make sure the SPI flash's 'quad enable' bit in its status register +matches the settings in the descriptor.bin, otherwise the board won't boot. + +For the on-board SPI flash MX25U6435F, this can be done by writing 0x40 to the +status register by DediProg in: Config > Modify Status Register > Write Status +Register(s) > Register1 Value(Hex). This is is a one-time change. Once set, it +persists in SPI flash part regardless of the u-boot.rom image burned. diff --git a/doc/board/intel/index.rst b/doc/board/intel/index.rst index af24760b78..d30debb7f0 100644 --- a/doc/board/intel/index.rst +++ b/doc/board/intel/index.rst @@ -7,5 +7,6 @@ Intel :maxdepth: 2 bayleybay + cherryhill crownbay minnowmax -- cgit From 87fdda62cd15c9231b3b7c1da7f9c333497ae17e Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Thu, 18 Jul 2019 00:34:08 -0700 Subject: doc: board: Add Intel Cougar Canyon 2 board doc This extracts Intel Cougar Canyon 2 board specific information from README.x86, converts plain text documentation to reST format and adds it to Sphinx TOC tree. No essential content change. Signed-off-by: Bin Meng --- doc/board/intel/cougarcanyon2.rst | 24 ++++++++++++++++++++++++ doc/board/intel/index.rst | 1 + 2 files changed, 25 insertions(+) create mode 100644 doc/board/intel/cougarcanyon2.rst (limited to 'doc/board/intel') diff --git a/doc/board/intel/cougarcanyon2.rst b/doc/board/intel/cougarcanyon2.rst new file mode 100644 index 0000000000..5e3e7a1820 --- /dev/null +++ b/doc/board/intel/cougarcanyon2.rst @@ -0,0 +1,24 @@ +.. SPDX-License-Identifier: GPL-2.0+ +.. sectionauthor:: Bin Meng + +Cougar Canyon 2 CRB +=================== + +This uses Intel FSP for 3rd generation Intel Core and Intel Celeron processors +with mobile Intel HM76 and QM77 chipsets platform. Download it from Intel FSP +website and put the .fd file (CHIEFRIVER_FSP_GOLD_001_09-OCTOBER-2013.fd at the +time of writing) in the board directory and rename it to fsp.bin. + +Now build U-Boot and obtain u-boot.rom:: + + $ make cougarcanyon2_defconfig + $ make all + +The board has two 8MB SPI flashes mounted, which are called SPI-0 and SPI-1 in +the board manual. The SPI-0 flash should have flash descriptor plus ME firmware +and SPI-1 flash is used to store U-Boot. For convenience, the complete 8MB SPI-0 +flash image is included in the FSP package (named Rom00_8M_MB_PPT.bin). Program +this image to the SPI-0 flash according to the board manual just once and we are +all set. For programming U-Boot we just need to program SPI-1 flash. Since the +default u-boot.rom image for this board is set to 2MB, it should be programmed +to the last 2MB of the 8MB chip, address range [600000, 7FFFFF]. diff --git a/doc/board/intel/index.rst b/doc/board/intel/index.rst index d30debb7f0..521e6e6baa 100644 --- a/doc/board/intel/index.rst +++ b/doc/board/intel/index.rst @@ -8,5 +8,6 @@ Intel bayleybay cherryhill + cougarcanyon2 crownbay minnowmax -- cgit From 225b87c26d13af3c556d12e4837d5a3863d0ff84 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Thu, 18 Jul 2019 00:34:09 -0700 Subject: doc: board: Add Intel Edison board doc This extracts Intel Edison board specific information from README.x86, converts plain text documentation to reST format and adds it to Sphinx TOC tree. No essential content change. Signed-off-by: Bin Meng Acked-by: Andy Shevchenko --- doc/board/intel/edison.rst | 41 +++++++++++++++++++++++++++++++++++++++++ doc/board/intel/index.rst | 1 + 2 files changed, 42 insertions(+) create mode 100644 doc/board/intel/edison.rst (limited to 'doc/board/intel') diff --git a/doc/board/intel/edison.rst b/doc/board/intel/edison.rst new file mode 100644 index 0000000000..1aee2a1fc0 --- /dev/null +++ b/doc/board/intel/edison.rst @@ -0,0 +1,41 @@ +.. SPDX-License-Identifier: GPL-2.0+ +.. sectionauthor:: Andy Shevchenko + +Edison +====== + +Build Instructions for U-Boot as main bootloader +------------------------------------------------ + +Simple you can build U-Boot and obtain u-boot.bin:: + + $ make edison_defconfig + $ make all + +Updating U-Boot on Edison +------------------------- + +By default Intel Edison boards are shipped with preinstalled heavily +patched U-Boot v2014.04. Though it supports DFU which we may be able to +use. + +1. Prepare u-boot.bin as described in chapter above. You still need one + more step (if and only if you have original U-Boot), i.e. run the + following command:: + + $ truncate -s %4096 u-boot.bin + +2. Run your board and interrupt booting to U-Boot console. In the console + call:: + + => run do_force_flash_os + +3. Wait for few seconds, it will prepare environment variable and runs + DFU. Run DFU command from the host system:: + + $ dfu-util -v -d 8087:0a99 --alt u-boot0 -D u-boot.bin + +4. Return to U-Boot console and following hint. i.e. push Ctrl+C, and + reset the board:: + + => reset diff --git a/doc/board/intel/index.rst b/doc/board/intel/index.rst index 521e6e6baa..482e01b425 100644 --- a/doc/board/intel/index.rst +++ b/doc/board/intel/index.rst @@ -10,4 +10,5 @@ Intel cherryhill cougarcanyon2 crownbay + edison minnowmax -- cgit From f0312aeea3d339012425b0edf89254869dd526e2 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Thu, 18 Jul 2019 00:34:10 -0700 Subject: doc: board: Add Intel Galileo board doc This extracts Intel Galileo board specific information from README.x86, converts plain text documentation to reST format and adds it to Sphinx TOC tree. No essential content change. Signed-off-by: Bin Meng --- doc/board/intel/galileo.rst | 22 ++++++++++++++++++++++ doc/board/intel/index.rst | 1 + 2 files changed, 23 insertions(+) create mode 100644 doc/board/intel/galileo.rst (limited to 'doc/board/intel') diff --git a/doc/board/intel/galileo.rst b/doc/board/intel/galileo.rst new file mode 100644 index 0000000000..f51a06bb9e --- /dev/null +++ b/doc/board/intel/galileo.rst @@ -0,0 +1,22 @@ +.. SPDX-License-Identifier: GPL-2.0+ +.. sectionauthor:: Bin Meng + +Galileo +======= + +Only one binary blob is needed for Remote Management Unit (RMU) within Intel +Quark SoC. Not like FSP, U-Boot does not call into the binary. The binary is +needed by the Quark SoC itself. + +You can get the binary blob from Quark Board Support Package from Intel website: + + * ./QuarkSocPkg/QuarkNorthCluster/Binary/QuarkMicrocode/RMU.bin + +Rename the file and put it to the board directory by:: + + $ cp RMU.bin board/intel/galileo/rmu.bin + +Now you can build U-Boot and obtain u-boot.rom:: + + $ make galileo_defconfig + $ make all diff --git a/doc/board/intel/index.rst b/doc/board/intel/index.rst index 482e01b425..f416801910 100644 --- a/doc/board/intel/index.rst +++ b/doc/board/intel/index.rst @@ -11,4 +11,5 @@ Intel cougarcanyon2 crownbay edison + galileo minnowmax -- cgit