From 79e4e6480b359cb28129cecfa2cae0ef9cccf803 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 14 Jul 2010 10:04:21 -0500 Subject: powerpc/8xxx: Enabled hwconfig for memory interleaving Replace environmental variables memctl_intlv_ctl and ba_intlv_ctl with hwconfig parameters. The syntax is setenv hwconfig "fsl_ddr:ctlr_intlv=,bank_intlv=" The mode values for memory controller interleaving are cacheline page bank superbank The mode values for bank interleaving are cs0_cs1 cs2_cs3 cs0_cs1_and_cs2_cs3 cs0_cs1_cs2_cs3 Signed-off-by: York Sun --- doc/README.fsl-ddr | 25 ++++++++++++++----------- 1 file changed, 14 insertions(+), 11 deletions(-) (limited to 'doc') diff --git a/doc/README.fsl-ddr b/doc/README.fsl-ddr index 9c2224fea1..6e4f6e9244 100644 --- a/doc/README.fsl-ddr +++ b/doc/README.fsl-ddr @@ -32,38 +32,41 @@ The ways to configure the ddr interleaving mode 1. In board header file(e.g.MPC8572DS.h), add default interleaving setting under "CONFIG_EXTRA_ENV_SETTINGS", like: #define CONFIG_EXTRA_ENV_SETTINGS \ - "memctl_intlv_ctl=2\0" \ + "hwconfig=fsl_ddr:ctlr_intlv=bank" \ ...... 2. Run u-boot "setenv" command to configure the memory interleaving mode. Either numerical or string value is accepted. # disable memory controller interleaving - setenv memctl_intlv_ctl + setenv hwconfig "fsl_ddr:ctlr_intlv=null" # cacheline interleaving - setenv memctl_intlv_ctl 0 or setenv memctl_intlv_ctl cacheline + setenv hwconfig "fsl_ddr:ctlr_intlv=cacheline" # page interleaving - setenv memctl_intlv_ctl 1 or setenv memctl_intlv_ctl page + setenv hwconfig "fsl_ddr:ctlr_intlv=page" # bank interleaving - setenv memctl_intlv_ctl 2 or setenv memctl_intlv_ctl bank + setenv hwconfig "fsl_ddr:ctlr_intlv=bank" # superbank - setenv memctl_intlv_ctl 3 or setenv memctl_intlv_ctl superbank + setenv hwconfig "fsl_ddr:ctlr_intlv=superbank" # disable bank (chip-select) interleaving - setenv ba_intlv_ctl + setenv hwconfig "fsl_ddr:bank_intlv=null" # bank(chip-select) interleaving cs0+cs1 - setenv ba_intlv_ctl 0x40 or setenv ba_intlv_ctl cs0_cs1 + setenv hwconfig "fsl_ddr:bank_intlv=cs0_cs1" # bank(chip-select) interleaving cs2+cs3 - setenv ba_intlv_ctl 0x20 or setenv ba_intlv_ctl cs2_cs3 + setenv hwconfig "fsl_ddr:bank_intlv=cs2_cs3" # bank(chip-select) interleaving (cs0+cs1) and (cs2+cs3) (2x2) - setenv ba_intlv_ctl 0x60 or setenv ba_intlv_ctl cs0_cs1_and_cs2_cs3 + setenv hwconfig "fsl_ddr:bank_intlv=cs0_cs1_and_cs2_cs3" # bank(chip-select) interleaving (cs0+cs1+cs2+cs3) (4x1) - setenv ba_intlv_ctl 0x04 or setenv ba_intlv_ctl cs0_cs1_cs2_cs3 + setenv hwconfig "fsl_ddr:bank_intlv=cs0_cs1_cs2_cs3" + + The above memory controller interleaving and bank interleaving can be mixed. The syntax is + setenv hwconfig "fsl_ddr:ctlr_intlv=cacheline,bank_intlv=cs0_cs1" -- cgit From 076bff8f4746baf7c83b96049d97e9dd4454dace Mon Sep 17 00:00:00 2001 From: york Date: Fri, 2 Jul 2010 22:25:52 +0000 Subject: powerpc/8xxx: Fix bug in memctrl interleaving & bank interleaving on cs0~cs4 Verified on MPC8641HPCN with four DDR2 dimms. Each dimm has dual rank with 512MB each rank. Also check dimm size and rank size for memory controller interleaving Signed-off-by: York Sun --- doc/README.fsl-ddr | 3 +++ 1 file changed, 3 insertions(+) (limited to 'doc') diff --git a/doc/README.fsl-ddr b/doc/README.fsl-ddr index 6e4f6e9244..8c37bbead1 100644 --- a/doc/README.fsl-ddr +++ b/doc/README.fsl-ddr @@ -27,6 +27,9 @@ Table of interleaving modes supported in cpu/8xxx/ddr/ from each controller. {CS2+CS3} on each controller are only rank interleaved on that controller. + For memory controller interleaving, identical DIMMs are suggested. Software + doesn't check the size or organization of interleaved DIMMs. + The ways to configure the ddr interleaving mode ============================================== 1. In board header file(e.g.MPC8572DS.h), add default interleaving setting -- cgit From 7fd101c97b58dab7b0bd87f30c3dedb0db21d15f Mon Sep 17 00:00:00 2001 From: york Date: Fri, 2 Jul 2010 22:25:54 +0000 Subject: powerpc/8xxx: Enabled address hashing for 85xx For 85xx silicon which supports address hashing, it can be activated by hwconfig. Signed-off-by: York Sun --- doc/README.fsl-ddr | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) (limited to 'doc') diff --git a/doc/README.fsl-ddr b/doc/README.fsl-ddr index 8c37bbead1..e108a0d50c 100644 --- a/doc/README.fsl-ddr +++ b/doc/README.fsl-ddr @@ -71,5 +71,16 @@ The ways to configure the ddr interleaving mode # bank(chip-select) interleaving (cs0+cs1+cs2+cs3) (4x1) setenv hwconfig "fsl_ddr:bank_intlv=cs0_cs1_cs2_cs3" - The above memory controller interleaving and bank interleaving can be mixed. The syntax is - setenv hwconfig "fsl_ddr:ctlr_intlv=cacheline,bank_intlv=cs0_cs1" +Memory controller address hashing +================================== +If the DDR controller supports address hashing, it can be enabled by hwconfig. + +Syntax is: +hwconfig=fsl_ddr:addr_hash=true + +Combination of hwconfig +======================= +Hwconfig can be combined with multiple parameters, for example, on a supported +platform + +hwconfig=fsl_ddr:addr_hash=true,ctlr_intlv=cacheline,bank_intlv=cs0_cs1_cs2_cs3 -- cgit