From 58b485776698c3d71ec5a215e392123b4c15afa3 Mon Sep 17 00:00:00 2001 From: Markus Klotzbuecher Date: Mon, 27 Nov 2006 11:51:21 +0100 Subject: Add a small README with information on the generic ohci driver. --- doc/README.generic_usb_ohci | 43 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) create mode 100644 doc/README.generic_usb_ohci (limited to 'doc') diff --git a/doc/README.generic_usb_ohci b/doc/README.generic_usb_ohci new file mode 100644 index 0000000000..017c69ab07 --- /dev/null +++ b/doc/README.generic_usb_ohci @@ -0,0 +1,43 @@ +Notes on the the generic USB-OHCI driver +======================================== + +This driver (drivers/usb_ohci.[ch]) is the result of the merge of +various existing OHCI drivers that were basically identical beside +cpu/board dependant initalization. This initalization has been moved +into cpu/board directories and are called via the hooks below. + +Configuration options +---------------------- + +CONFIG_USB_OHCI_NEW: enable the new OHCI driver + +CFG_USB_OHCI_BOARD_INIT: call the board dependant hooks: + + - extern int usb_board_init(void); + - extern int usb_board_stop(void); + - extern int usb_cpu_init_fail(void); + +CFG_USB_OHCI_CPU_INIT: call the cpu dependant hooks: + + - extern int usb_cpu_init(void); + - extern int usb_cpu_stop(void); + - extern int usb_cpu_init_fail(void); + +CFG_USB_OHCI_REGS_BASE: defines the base address of the OHCI registers + +CFG_USB_OHCI_SLOT_NAME: slot name + +CFG_USB_OHCI_MAX_ROOT_PORTS: maximal number of ports of the root hub. + + +Endianness issues +------------------ + +The LITTLEENDIAN #define determines if the 'swap_16' and 'swap_32' +macros do byte swapping or not. But some cpus OHCI-controllers such as +ppc4xx and mpc5xxx operate in little endian mode, so some extra ifdefs +were necessary to make this work. + + + + -- cgit From fc43be478f2aa37ce38acd85355038866e4162af Mon Sep 17 00:00:00 2001 From: Markus Klotzbuecher Date: Wed, 6 Jun 2007 11:49:35 +0200 Subject: USB/OHCI: endianness cleanup in the generic ohci driver --- doc/README.generic_usb_ohci | 49 ++++++++++++++++++++++++++++++--------------- 1 file changed, 33 insertions(+), 16 deletions(-) (limited to 'doc') diff --git a/doc/README.generic_usb_ohci b/doc/README.generic_usb_ohci index 017c69ab07..c343dfdf90 100644 --- a/doc/README.generic_usb_ohci +++ b/doc/README.generic_usb_ohci @@ -9,35 +9,52 @@ into cpu/board directories and are called via the hooks below. Configuration options ---------------------- -CONFIG_USB_OHCI_NEW: enable the new OHCI driver + CONFIG_USB_OHCI_NEW: enable the new OHCI driver -CFG_USB_OHCI_BOARD_INIT: call the board dependant hooks: + CFG_USB_OHCI_BOARD_INIT: call the board dependant hooks: - - extern int usb_board_init(void); - - extern int usb_board_stop(void); - - extern int usb_cpu_init_fail(void); + - extern int usb_board_init(void); + - extern int usb_board_stop(void); + - extern int usb_cpu_init_fail(void); -CFG_USB_OHCI_CPU_INIT: call the cpu dependant hooks: + CFG_USB_OHCI_CPU_INIT: call the cpu dependant hooks: - - extern int usb_cpu_init(void); - - extern int usb_cpu_stop(void); - - extern int usb_cpu_init_fail(void); + - extern int usb_cpu_init(void); + - extern int usb_cpu_stop(void); + - extern int usb_cpu_init_fail(void); -CFG_USB_OHCI_REGS_BASE: defines the base address of the OHCI registers + CFG_USB_OHCI_REGS_BASE: defines the base address of the OHCI + registers -CFG_USB_OHCI_SLOT_NAME: slot name + CFG_USB_OHCI_SLOT_NAME: slot name -CFG_USB_OHCI_MAX_ROOT_PORTS: maximal number of ports of the root hub. + CFG_USB_OHCI_MAX_ROOT_PORTS: maximal number of ports of the + root hub. Endianness issues ------------------ -The LITTLEENDIAN #define determines if the 'swap_16' and 'swap_32' -macros do byte swapping or not. But some cpus OHCI-controllers such as -ppc4xx and mpc5xxx operate in little endian mode, so some extra ifdefs -were necessary to make this work. +The USB bus operates in little endian, but unfortunately there are +OHCI controllers that operate in big endian such as ppc4xx and +mpc5xxx. For these the config option + CFG_OHCI_BE_CONTROLLER + +needs to be defined. + + +PCI Controllers +---------------- + +You'll need to define + + CONFIG_PCI_OHCI + +PCI Controllers need to do byte swapping on register accesses, so they +should to define: + + CFG_OHCI_SWAP_REG_ACCESS -- cgit From b3631487105a57ab7cbadfc26efbaf9676275018 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Sun, 8 Jul 2007 15:45:08 -0500 Subject: Remove references to the old cmd_confdefs.h include file. Signed-off-by: Jon Loeliger --- doc/README.bedbug | 3 --- 1 file changed, 3 deletions(-) (limited to 'doc') diff --git a/doc/README.bedbug b/doc/README.bedbug index 9cfb4217fe..6b3fe687dd 100644 --- a/doc/README.bedbug +++ b/doc/README.bedbug @@ -31,9 +31,6 @@ can be easily implemented. if it is an illegal instruction, privileged instruction or a trap. Also added debug trap handler. -./include/cmd_confdefs.h - Added definition of CFG_CMD_BEDBUG. - ./include/config_WALNUT405.h Added CFG_CMD_BEDBUG to the CONFIG_COMMANDS for the WALNUT. -- cgit From b5501f7d720fed99ab0b42c83f5dea52868ce007 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Mon, 9 Jul 2007 19:10:03 -0500 Subject: Update README.* to reference new CONFIG_CMD_* names now. Signed-off-by: Jon Loeliger --- doc/README.SNTP | 4 ++-- doc/README.bedbug | 7 ------- doc/README.nand | 4 ++-- 3 files changed, 4 insertions(+), 11 deletions(-) (limited to 'doc') diff --git a/doc/README.SNTP b/doc/README.SNTP index fd6f2098f9..9edc957c6f 100644 --- a/doc/README.SNTP +++ b/doc/README.SNTP @@ -1,5 +1,5 @@ -To use SNTP support, add a define CFG_CMD_SNTP to CONFIG_COMMANDS in -the configuration file of the board. +To use SNTP support, add define CONFIG_CMD_SNTP to the +configuration file of the board. The "sntp" command gets network time from NTP time server and syncronize RTC of the board. This command needs the command line diff --git a/doc/README.bedbug b/doc/README.bedbug index 6b3fe687dd..2616acc653 100644 --- a/doc/README.bedbug +++ b/doc/README.bedbug @@ -31,9 +31,6 @@ can be easily implemented. if it is an illegal instruction, privileged instruction or a trap. Also added debug trap handler. -./include/config_WALNUT405.h - Added CFG_CMD_BEDBUG to the CONFIG_COMMANDS for the WALNUT. - ./include/ppc_asm.tmpl Added code to handle critical exceptions @@ -75,10 +72,6 @@ Changes: cpu/mpc8xx/traps.c Added new routine DebugException() - include/config_MBX.h - Added CFG_CMD_BEDBUG to CONFIG_COMMANDS define - - New Files: cpu/mpc8xx/bedbug_860.c diff --git a/doc/README.nand b/doc/README.nand index 5c31845a94..c5c5ef29e6 100644 --- a/doc/README.nand +++ b/doc/README.nand @@ -93,8 +93,8 @@ Commands: Configuration Options: - CFG_CMD_NAND - A good one to add to CONFIG_COMMANDS since it enables NAND support. + CONFIG_CMD_NAND + Enables NAND support and commmands. CONFIG_MTD_NAND_ECC_JFFS2 Define this if you want the Error Correction Code information in -- cgit From b3aff0cb9ecf236d7e8c93761dd1dadf6837a582 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Tue, 10 Jul 2007 11:19:50 -0500 Subject: disk/ doc/ lib_*/ and tools/: Remove lingering references to CFG_CMD_* symbols. Fixed some broken instances of "#ifdef CMD_CFG_IDE" too. Those always evaluated TRUE, and thus were always compiled even when IDE really wasn't defined/wanted. Signed-off-by: Jon Loeliger --- doc/README.JFFS2 | 2 +- doc/README.PIP405 | 14 ++++++-------- doc/README.usb | 6 +++--- 3 files changed, 10 insertions(+), 12 deletions(-) (limited to 'doc') diff --git a/doc/README.JFFS2 b/doc/README.JFFS2 index 270da9082f..c5d67fd4e0 100644 --- a/doc/README.JFFS2 +++ b/doc/README.JFFS2 @@ -2,7 +2,7 @@ JFFS2 options and usage. ----------------------- JFFS2 in U-Boot is a read only implementation of the file system in -Linux with the same name. To use JFFS2 define CFG_CMD_JFFS2. +Linux with the same name. To use JFFS2 define CONFIG_CMD_JFFS2. The module adds three new commands. fsload - load binary file from a file system image diff --git a/doc/README.PIP405 b/doc/README.PIP405 index c5ccf1875e..610ff2161d 100644 --- a/doc/README.PIP405 +++ b/doc/README.PIP405 @@ -32,10 +32,8 @@ Changed files: - include/cmd_bsp.h added PIP405 commands definitions - include/cmd_condefs.h added Floppy and SCSI support - include/cmd_disk.h changed to work with block device description -- include/config_LANTEC.h excluded CFG_CMD_FDC and CFG_CMD_SCSI from - CONFIG_CMD_FULL -- include/config_hymod.h excluded CFG_CMD_FDC and CFG_CMD_SCSI from - CONFIG_CMD_FULL +- include/config_LANTEC.h excluded CONFIG_CMD_FDC and CONFIG_CMD_SCSI +- include/config_hymod.h excluded CONFIG_CMD_FDC and CONFIG_CMD_SCSI - include/flash.h added INTEL_ID_28F320C3T 0x88C488C4 - include/i2c.h added "defined(CONFIG_PIP405)" - include/image.h added IH_OS_U_BOOT, IH_TYPE_FIRMWARE @@ -88,8 +86,8 @@ section "Changes". New Commands: ------------- -CFG_CMD_SCSI SCSI Support -CFG_CMF_FDC Floppy disk support +CONFIG_CMD_SCSI SCSI Support +CONFIG_CMF_FDC Floppy disk support IDE additions: -------------- @@ -172,8 +170,8 @@ Added Devices: Floppy support: --------------- Support of a standard floppy disk controller at address CFG_ISA_IO_BASE_ADDRESS -+ 0x3F0. Enabled with define CFG_CMD_FDC. Reads a unformated floppy disk with a -image header (see: mkimage). No interrupts and no DMA are used for this. ++ 0x3F0. Enabled with define CONFIG_CMD_FDC. Reads a unformated floppy disk +with a image header (see: mkimage). No interrupts and no DMA are used for this. Added files: - common/cmd_fdc.c - include/cmd_fdc.h diff --git a/doc/README.usb b/doc/README.usb index 41f76f4b7e..b3bcb91f40 100644 --- a/doc/README.usb +++ b/doc/README.usb @@ -73,8 +73,8 @@ Storage USB Commands: Config Switches: ---------------- -CFG_CMD_USB enables basic USB support and the usb command -CONFIG_USB_UHCI defines the lowlevel part.A lowlevel part must be defined if - using CFG_CMD_USB +CONFIG_CMD_USB enables basic USB support and the usb command +CONFIG_USB_UHCI defines the lowlevel part.A lowlevel part must be defined + if using CONFIG_CMD_USB CONFIG_USB_KEYBOARD enables the USB Keyboard CONFIG_USB_STORAGE enables the USB storage devices -- cgit From 537223afa61f64480df31ce440a9cb386df4a814 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 6 Aug 2007 21:10:17 +0200 Subject: ppc4xx: Update AMCC Bamboo README doc/README.bamboo As suggested by Eugene O'Brien , here an updated Bamboo README. Signed-off-by: Stefan Roese --- doc/README.bamboo | 62 +++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 62 insertions(+) (limited to 'doc') diff --git a/doc/README.bamboo b/doc/README.bamboo index b50be01ab7..e139c6d129 100644 --- a/doc/README.bamboo +++ b/doc/README.bamboo @@ -1,3 +1,65 @@ +The 2 important dipswitches are configured as shown below: + +SW1 (for 33MHz SysClk) +---------------------- +S1 S2 S3 S4 S5 S6 S7 S8 +OFF OFF OFF OFF OFF OFF OFF ON + +SW7 (for Op-Code Flash and Boot Option H) +----------------------------------------- +S1 S2 S3 S4 S5 S6 S7 S8 +OFF OFF OFF ON OFF OFF OFF OFF + +The EEPROM at location 0x52 is loaded with these 16 bytes: +C47042A6 05D7A190 40082350 0d050000 + +SDR0_SDSTP0[ENG]: 1 : PLL's VCO is the source for PLL forward divisors +SDR0_SDSTP0[SRC]: 1 : Feedback originates from PLLOUTB +SDR0_SDSTP0[SEL]: 0 : Feedback selection is PLL output +SDR0_SDSTP0[TUNE]: 1000111000 : 10 <= M <= 22, 600MHz < VCO <= 900MHz +SDR0_SDSTP0[FBDV]: 4 : PLL feedback divisor +SDR0_SDSTP0[FBDVA]: 2 : PLL forward divisor A +SDR0_SDSTP0[FBDVB]: 5 : PLL forward divisor B +SDR0_SDSTP0[PRBDV0]: 1 : PLL primary divisor B +SDR0_SDSTP0[OPBDV0]: 2 : OPB clock divisor +SDR0_SDSTP0[LFBDV]: 1 : PLL local feedback divisor +SDR0_SDSTP0[PERDV0]: 3 : Peripheral clock divisor 0 +SDR0_SDSTP0[MALDV0]: 2 : MAL clock divisor 0 +SDR0_SDSTP0[PCIDV0]: 2 : Sync PCI clock divisor 0 +SDR0_SDSTP0[PLLTIMER]: 7 : PLL locking timer +SDR0_SDSTP0[RW]: 1 : EBC ROM width: 16-bit +SDR0_SDSTP0[RL]: 0 : EBC ROM location: EBC +SDR0_SDSTP0[PAE]: 0 : PCI internal arbiter: disabled +SDR0_SDSTP0[PHCE]: 0 : PCI host configuration: disabled +SDR0_SDSTP0[ZM]: 3 : ZMII mode: RMII mode 100 +SDR0_SDSTP0[CTE]: 0 : CPU trace: disabled +SDR0_SDSTP0[Nto1]: 0 : CPU/PLB ratio N/P: not N to 1 +SDR0_SDSTP0[PAME]: 1 : PCI asynchronous mode: enabled +SDR0_SDSTP0[MEM]: 1 : Multiplex: EMAC +SDR0_SDSTP0[NE]: 0 : NDFC: disabled +SDR0_SDSTP0[NBW]: 0 : NDFC boot width: 8-bit +SDR0_SDSTP0[NBW]: 0 : NDFC boot page selection +SDR0_SDSTP0[NBAC]: 0 : NDFC boot address selection cycle: 3 Addr. Cycles, 1 Col. + 2 Row (512 page size) +SDR0_SDSTP0[NARE]: 0 : NDFC auto read : disabled +SDR0_SDSTP0[NRB]: 0 : NDFC Ready/Busy : Ready +SDR0_SDSTP0[NDRSC]: 33333 : NDFC device reset counter +SDR0_SDSTP0[NCG0]: 0 : NDFC/EBC chip select gating CS0 : EBC +SDR0_SDSTP0[NCG1]: 0 : NDFC/EBC chip select gating CS1 : EBC +SDR0_SDSTP0[NCG2]: 0 : NDFC/EBC chip select gating CS2 : EBC +SDR0_SDSTP0[NCG3]: 0 : NDFC/EBC chip select gating CS3 : EBC +SDR0_SDSTP0[NCRDC]: 3333 : NDFC device read count + +PPC440EP Clocking Configuration + +SysClk is 33.0MHz, M is 20, VCO is 660.0MHz, CPU is 330.0MHz, PLB is 132.0MHz +OPB is 66.0MHz, EBC is 44.0MHz, MAL is 66.0MHz, Sync PCI is 66.0MHz + +The above information is reported by Eugene O'Brien +. Thanks a lot. + +2007-08-06, Stefan Roese +--------------------------------------------------------------------- + The configuration for the AMCC 440EP eval board "Bamboo" was changed to only use 384 kbytes of FLASH for the U-Boot image. This way the redundant environment can be saved in the remaining 2 sectors of the -- cgit From 66dc2c2dc51f8b88bb8e231bc80cd92eae1d6476 Mon Sep 17 00:00:00 2001 From: Dave Liu Date: Mon, 25 Jun 2007 13:21:12 +0800 Subject: mpc83xx: Revise the MPC8360EMDS readme doc When the rev2.x silicon mount on the MPC8360EMDS baord, and if you are using the u-boot version after the commit 3fc0bd159103b536e1c54c6f4457a09b3aba66ca. to make the ethernet interface usable, we have to setup the jumpers correctly. Signed-off-by: Dave Liu Signed-off-by: Kim Phillips --- doc/README.mpc8360emds | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) (limited to 'doc') diff --git a/doc/README.mpc8360emds b/doc/README.mpc8360emds index c87469f43d..5f202475b5 100644 --- a/doc/README.mpc8360emds +++ b/doc/README.mpc8360emds @@ -21,7 +21,13 @@ Freescale MPC8360EMDS Board SW3[1:8]= 0000_0001 refers to bits labeled 1 through 6 is set as "On" and bits labeled 8 is set as "Off". -1.1 For the MPC8360E PB PROTO Board +1.1 There are three type boards for MPC8360E silicon up to now, They are + + * MPC8360E-MDS-PB PROTO (a.k.a 8360SYS PROTOTYPE) + * MPC8360E-MDS-PB PILOT (a.k.a 8360SYS PILOT) + * MPC8360EA-MDS-PB PROTO (a.k.a 8360SYS2 PROTOTYPE) + +1.2 For all the MPC8360EMDS Board First, make sure the board default setting is consistent with the document shipped with your board. Then apply the following setting: @@ -33,6 +39,21 @@ Freescale MPC8360EMDS Board JP6 1-2 on board Oscillator: 66M +1.3 Since different board/chip rev. combinations have AC timing issues, + u-boot forces RGMII-ID (RGMII with Internal Delay) mode on by default + by the patch (mpc83xx: Disable G1TXCLK, G2TXCLK h/w buffers). + + When the rev2.x silicon mount on these boards, and if you are using + u-boot version after this patch, to make the ethernet interfaces usable, + and to enable RGMII-ID on your board, you have to setup the jumpers + correctly. + + * MPC8360E-MDS-PB PROTO + nothing to do + * MPC8360E-MDS-PB PILOT + JP9 and JP8 should be ON + * MPC8360EA-MDS-PB PROTO + JP2 and JP3 should be ON 2. Memory Map -- cgit From 1c274c4e05b6dc9b24edc8aa618b02f607ee6eed Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Wed, 25 Jul 2007 19:25:33 -0500 Subject: mpc83xx: add support for the MPC8323E RDB MPC8323E based board with 64MB fixed SDRAM, 16MB flash, five 10/100 ethernet ports connected via an ICPlus IP175C switch, one PCI slot, and serial. Features not supported in this patch are SD card interface, 2 USB ports, and the two phone ports. Signed-off-by: Michael Barkowski Signed-off-by: Kim Phillips --- doc/README.mpc8323erdb | 71 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 71 insertions(+) create mode 100644 doc/README.mpc8323erdb (limited to 'doc') diff --git a/doc/README.mpc8323erdb b/doc/README.mpc8323erdb new file mode 100644 index 0000000000..6f89829373 --- /dev/null +++ b/doc/README.mpc8323erdb @@ -0,0 +1,71 @@ +Freescale MPC8323ERDB Board +----------------------------------------- + +1. Memory Map + The memory map looks like this: + + 0x0000_0000 0x03ff_ffff DDR 64M + 0x8000_0000 0x8fff_ffff PCI MEM 256M + 0x9000_0000 0x9fff_ffff PCI_MMIO 256M + 0xe000_0000 0xe00f_ffff IMMR 1M + 0xd000_0000 0xd3ff_ffff PCI IO 64M + 0xfe00_0000 0xfeff_ffff NOR FLASH (CS0) 16M + +2. Compilation + + Assuming you're using BASH (or similar) as your shell: + + export CROSS_COMPILE=your-cross-compiler-prefix- + make distclean + make MPC8323ERDB_config + make + +3. Downloading and Flashing Images + +3.1 Reflash U-boot Image using U-boot + + N.b, have an alternate means of programming + the flash available if the new u-boot doesn't boot. + + First try a: + + tftpboot $loadaddr $uboot + + to make sure that the TFTP load will succeed before + an erase goes ahead and wipes out your current firmware. + Then do a: + + run tftpflash + + which is a shorter version of the manual sequence: + + tftp $loadaddr u-boot.bin + protect off fe000000 +$filesize + erase fe000000 +$filesize + cp.b $loadaddr fe000000 $filesize + + To keep your old u-boot's environment variables, do a: + + saveenv + + prior to resetting the board. + +3.2 Downloading and Booting Linux Kernel + + Ensure that all networking-related environment variables are set + properly (including ipaddr, serverip, gatewayip (if needed), + netmask, ethaddr, eth1addr, rootpath (if using NFS root), + fdtfile, and bootfile). + + Then, do one of the following, depending on whether you + want an NFS root or a ramdisk root: + + run nfsboot + + or + + run ramboot + +4 Notes + + The console baudrate for MPC8323ERDB is 115200bps. -- cgit From 47e8bc846759e037b8af0e5f9c9f9cfa7a1050c3 Mon Sep 17 00:00:00 2001 From: Dave Liu Date: Wed, 1 Aug 2007 15:00:59 +0800 Subject: mpc83xx: Correct the README for DDR ECC Update the README for DDR ECC, change the name to README.mpc83xx.ddrecc. Signed-off-by: Dave Liu Signed-off-by: Kim Phillips --- doc/README.mpc8349emds.ddrecc | 154 ------------------------------------------ doc/README.mpc83xx.ddrecc | 154 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 154 insertions(+), 154 deletions(-) delete mode 100644 doc/README.mpc8349emds.ddrecc create mode 100644 doc/README.mpc83xx.ddrecc (limited to 'doc') diff --git a/doc/README.mpc8349emds.ddrecc b/doc/README.mpc8349emds.ddrecc deleted file mode 100644 index eb249c3956..0000000000 --- a/doc/README.mpc8349emds.ddrecc +++ /dev/null @@ -1,154 +0,0 @@ -Overview -======== - -The overall usage pattern for ECC diagnostic commands is the following: - - * (injecting errors is initially disabled) - - * define inject mask (which tells the DDR controller what type of errors - we'll be injecting: single/multiple bit etc.) - - * enable injecting errors - from now on the controller injects errors as - indicated in the inject mask - -IMPORTANT NOTICE: enabling injecting multiple-bit errors is potentially -dangerous as such errors are NOT corrected by the controller. Therefore caution -should be taken when enabling the injection of multiple-bit errors: it is only -safe when used on a carefully selected memory area and used under control of -the 'ecc test' command (see example 'Injecting Multiple-Bit Errors' below). In -particular, when you simply set the multiple-bit errors in inject mask and -enable injection, U-Boot is very likely to hang quickly as the errors will be -injected when it accesses its code, data etc. - - -Use cases for DDR 'ecc' command: -================================ - -Before executing particular tests reset target board or clear status registers: - -=> ecc captureclear -=> ecc errdetectclr all -=> ecc sbecnt 0 - - -Injecting Single-Bit Errors ---------------------------- - -1. Set 1 bit in Data Path Error Inject Mask - -=> ecc injectdatahi 1 - -2. Run test over some memory region - -=> ecc test 200000 10 - -3. Check ECC status - -=> ecc status -... -Memory Data Path Error Injection Mask High/Low: 00000001 00000000 -... -Memory Single-Bit Error Management (0..255): - Single-Bit Error Threshold: 255 - Single Bit Error Counter: 16 -... -Memory Error Detect: - Multiple Memory Errors: 0 - Multiple-Bit Error: 0 - Single-Bit Error: 0 -... - -16 errors were generated, Single-Bit Error flag was not set as Single Bit Error -Counter did not reach Single-Bit Error Threshold. - -4. Make sure used memory region got re-initialized with 0xcafecafe pattern - -=> md 200000 -00200000: cafecafe cafecafe cafecafe cafecafe ................ -00200010: cafecafe cafecafe cafecafe cafecafe ................ -00200020: cafecafe cafecafe cafecafe cafecafe ................ -00200030: cafecafe cafecafe cafecafe cafecafe ................ -00200040: cafecafe cafecafe cafecafe cafecafe ................ -00200050: cafecafe cafecafe cafecafe cafecafe ................ -00200060: cafecafe cafecafe cafecafe cafecafe ................ -00200070: cafecafe cafecafe cafecafe cafecafe ................ -00200080: deadbeef deadbeef deadbeef deadbeef ................ -00200090: deadbeef deadbeef deadbeef deadbeef ................ - - -Injecting Multiple-Bit Errors ------------------------------ - -1. Set more than 1 bit in Data Path Error Inject Mask - -=> ecc injectdatahi 5 - -2. Run test over some memory region - -=> ecc test 200000 10 - -3. Check ECC status - -=> ecc status -... -Memory Data Path Error Injection Mask High/Low: 00000005 00000000 -... -Memory Error Detect: - Multiple Memory Errors: 1 - Multiple-Bit Error: 1 - Single-Bit Error: 0 -... - -Observe that both Multiple Memory Errors and Multiple-Bit Error flags are set. - -4. Make sure used memory region got re-initialized with 0xcafecafe pattern - -=> md 200000 -00200000: cafecafe cafecafe cafecafe cafecafe ................ -00200010: cafecafe cafecafe cafecafe cafecafe ................ -00200020: cafecafe cafecafe cafecafe cafecafe ................ -00200030: cafecafe cafecafe cafecafe cafecafe ................ -00200040: cafecafe cafecafe cafecafe cafecafe ................ -00200050: cafecafe cafecafe cafecafe cafecafe ................ -00200060: cafecafe cafecafe cafecafe cafecafe ................ -00200070: cafecafe cafecafe cafecafe cafecafe ................ -00200080: deadbeef deadbeef deadbeef deadbeef ................ -00200090: deadbeef deadbeef deadbeef deadbeef ................ - - -Test Single-Bit Error Counter and Threshold -------------------------------------------- - -1. Set 1 bit in Data Path Error Inject Mask - -=> ecc injectdatahi 1 - -2. Enable error injection - -=> ecc inject en - -3. Let u-boot run for a with Single-Bit error injection enabled - -4. Disable error injection - -=> ecc inject dis - -4. Check status - -=> ecc status - -... -Memory Single-Bit Error Management (0..255): - Single-Bit Error Threshold: 255 - Single Bit Error Counter: 60 - -Memory Error Detect: - Multiple Memory Errors: 1 - Multiple-Bit Error: 0 - Single-Bit Error: 1 -... - -Observe that Single-Bit Error is 'on' which means that Single-Bit Error Counter -reached Single-Bit Error Threshold. Multiple Memory Errors bit is also 'on', that -is Counter reached Threshold more than one time (it wraps back after reaching -Threshold). diff --git a/doc/README.mpc83xx.ddrecc b/doc/README.mpc83xx.ddrecc new file mode 100644 index 0000000000..0029f08759 --- /dev/null +++ b/doc/README.mpc83xx.ddrecc @@ -0,0 +1,154 @@ +Overview +======== + +The overall usage pattern for ECC diagnostic commands is the following: + + * (injecting errors is initially disabled) + + * define inject mask (which tells the DDR controller what type of errors + we'll be injecting: single/multiple bit etc.) + + * enable injecting errors - from now on the controller injects errors as + indicated in the inject mask + +IMPORTANT NOTICE: enabling injecting multiple-bit errors is potentially +dangerous as such errors are NOT corrected by the controller. Therefore caution +should be taken when enabling the injection of multiple-bit errors: it is only +safe when used on a carefully selected memory area and used under control of +the 'ecc testdw' 'ecc testword' command (see example 'Injecting Multiple-Bit +Errors' below). In particular, when you simply set the multiple-bit errors in +inject mask and enable injection, U-Boot is very likely to hang quickly as the +errors will be injected when it accesses its code, data etc. + + +Use cases for DDR 'ecc' command: +================================ + +Before executing particular tests reset target board or clear status registers: + +=> ecc captureclear +=> ecc errdetectclr all +=> ecc sbecnt 0 + + +Injecting Single-Bit Errors +--------------------------- + +1. Set 1 bit in Data Path Error Inject Mask + +=> ecc injectdatahi 1 + +2. Run test over some memory region + +=> ecc testdw 200000 10 + +3. Check ECC status + +=> ecc status +... +Memory Data Path Error Injection Mask High/Low: 00000001 00000000 +... +Memory Single-Bit Error Management (0..255): + Single-Bit Error Threshold: 255 + Single Bit Error Counter: 16 +... +Memory Error Detect: + Multiple Memory Errors: 0 + Multiple-Bit Error: 0 + Single-Bit Error: 0 +... + +16 errors were generated, Single-Bit Error flag was not set as Single Bit Error +Counter did not reach Single-Bit Error Threshold. + +4. Make sure used memory region got re-initialized with 0x0123456789abcdef + +=> md 200000 +00200000: 01234567 89abcdef 01234567 89abcdef .#Eg.....#Eg.... +00200010: 01234567 89abcdef 01234567 89abcdef .#Eg.....#Eg.... +00200020: 01234567 89abcdef 01234567 89abcdef .#Eg.....#Eg.... +00200030: 01234567 89abcdef 01234567 89abcdef .#Eg.....#Eg.... +00200040: 01234567 89abcdef 01234567 89abcdef .#Eg.....#Eg.... +00200050: 01234567 89abcdef 01234567 89abcdef .#Eg.....#Eg.... +00200060: 01234567 89abcdef 01234567 89abcdef .#Eg.....#Eg.... +00200070: 01234567 89abcdef 01234567 89abcdef .#Eg.....#Eg.... +00200080: deadbeef deadbeef deadbeef deadbeef ................ +00200090: deadbeef deadbeef deadbeef deadbeef ................ + +Injecting Multiple-Bit Errors +----------------------------- + +1. Set more than 1 bit in Data Path Error Inject Mask + +=> ecc injectdatahi 1 +=> ecc injectdatalo 1 + +2. Run test over some memory region + +=> ecc testword 200000 1 + +3. Check ECC status + +=> ecc status +... +Memory Data Path Error Injection Mask High/Low: 00000001 00000001 +... +Memory Error Detect: + Multiple Memory Errors: 0 + Multiple-Bit Error: 1 + Single-Bit Error: 0 +... + +The Multiple Memory Errors flags not set and Multiple-Bit Error flags are set. + +4. Make sure used memory region got re-initialized with 0x0123456789abcdef + +=> md 200000 +00200000: 01234567 89abcdef 01234567 89abcdef .#Eg.....#Eg.... +00200010: 01234567 89abcdef 01234567 89abcdef .#Eg.....#Eg.... +00200020: 01234567 89abcdef 01234567 89abcdef .#Eg.....#Eg.... +00200030: 01234567 89abcdef 01234567 89abcdef .#Eg.....#Eg.... +00200040: 01234567 89abcdef 01234567 89abcdef .#Eg.....#Eg.... +00200050: 01234567 89abcdef 01234567 89abcdef .#Eg.....#Eg.... +00200060: 01234567 89abcdef 01234567 89abcdef .#Eg.....#Eg.... +00200070: 01234567 89abcdef 01234567 89abcdef .#Eg.....#Eg.... +00200080: deadbeef deadbeef deadbeef deadbeef ................ +00200090: deadbeef deadbeef deadbeef deadbeef ................ + + +Test Single-Bit Error Counter and Threshold +------------------------------------------- + +1. Set 1 bit in Data Path Error Inject Mask + +=> ecc injectdatahi 1 + +2. Enable error injection + +=> ecc inject en + +3. Let u-boot run for a with Single-Bit error injection enabled + +4. Disable error injection + +=> ecc inject dis + +4. Check status + +=> ecc status + +... +Memory Single-Bit Error Management (0..255): + Single-Bit Error Threshold: 255 + Single Bit Error Counter: 199 + +Memory Error Detect: + Multiple Memory Errors: 1 + Multiple-Bit Error: 0 + Single-Bit Error: 1 +... + +Observe that Single-Bit Error is 'on' which means that Single-Bit Error Counter +reached Single-Bit Error Threshold. Multiple Memory Errors bit is also 'on', that +is Counter reached Threshold more than one time (it wraps back after reaching +Threshold). -- cgit From c646bba6465a45c60746d4cc1602cd06c1960f2d Mon Sep 17 00:00:00 2001 From: Joe Hamman Date: Thu, 9 Aug 2007 15:11:03 -0500 Subject: Add support for SBC8641D. Config files. Add support for Wind River's SBC8641D reference board. Signed-off by: Joe Hamman Acked-by: Wolfgang Denk Acked-by: Jon Loeliger --- doc/README.sbc8641d | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 doc/README.sbc8641d (limited to 'doc') diff --git a/doc/README.sbc8641d b/doc/README.sbc8641d new file mode 100644 index 0000000000..a051466a11 --- /dev/null +++ b/doc/README.sbc8641d @@ -0,0 +1,28 @@ +Wind River SBC8641D reference board +=========================== + +Created 06/14/2007 Joe Hamman +Copyright 2007, Embedded Specialties, Inc. +Copyright 2007 Wind River Systemes, Inc. +----------------------------- + +1. Building U-Boot +------------------ +The SBC8641D code is known to build using ELDK 4.1. + + $ make sbc8641d_config + Configuring for sbc8641d board... + + $ make + + +2. Switch and Jumper Settings +----------------------------- +All Jumpers & Switches are in their default positions. Please refer to +the board documentation for details. Some settings control CPU voltages +and settings may change with board revisions. + +3. Known limitations +-------------------- +PCI: + The PCI command may hang if no boards are present in either slot. -- cgit From be5d72d10d47609326226225181e301fb9a33b58 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Mon, 13 Aug 2007 21:57:53 +0200 Subject: Minor coding style cleanup. Update CHANGELOG. Signed-off-by: Wolfgang Denk --- doc/README.generic_usb_ohci | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) (limited to 'doc') diff --git a/doc/README.generic_usb_ohci b/doc/README.generic_usb_ohci index c343dfdf90..494dd1f5d9 100644 --- a/doc/README.generic_usb_ohci +++ b/doc/README.generic_usb_ohci @@ -41,7 +41,7 @@ mpc5xxx. For these the config option CFG_OHCI_BE_CONTROLLER -needs to be defined. +needs to be defined. PCI Controllers @@ -55,6 +55,3 @@ PCI Controllers need to do byte swapping on register accesses, so they should to define: CFG_OHCI_SWAP_REG_ACCESS - - - -- cgit From 7bd30fc4a6475b41d6679ae3aafc9fa505260c47 Mon Sep 17 00:00:00 2001 From: Andy Fleming Date: Tue, 14 Aug 2007 01:33:18 -0500 Subject: Add MPC8544DS README Signed-off-by: Andy Fleming --- doc/README.mpc8544ds | 122 +++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 122 insertions(+) create mode 100644 doc/README.mpc8544ds (limited to 'doc') diff --git a/doc/README.mpc8544ds b/doc/README.mpc8544ds new file mode 100644 index 0000000000..14c7f765e4 --- /dev/null +++ b/doc/README.mpc8544ds @@ -0,0 +1,122 @@ +Overview +-------- +The MPC8544DS system is similar to the 85xx CDS systems such +as the MPC8548CDS due to the similar E500 core. However, it +is placed on the same board as the 8641 HPCN system. + + +Flash Banks +----------- +Like the 85xx CDS systems, the 8544 DS board has two flash banks. +They are both present on boot, but there locations can be swapped +using the dip-switch SW10, bit 2. + +However, unlike the CDS systems, but similar to the 8641 HPCN +board, a runtime reset through the FPGA can also affect a swap +on the flash bank mappings for the next reset cycle. + +Irrespective of the switch SW10[2], booting is always from the +boot bank at 0xfff8_0000. + + +Memory Map +---------- + +0xff80_0000 - 0xffbf_ffff Alernate bank 4MB +0xffc0_0000 - 0xffff_ffff Boot bank 4MB + +0xffb8_0000 Alternate image start 512KB +0xfff8_0000 Boot image start 512KB + + +Flashing Images +--------------- + +For example, to place a new image in the alternate flash bank +and then reset with that new image temporarily, use this: + + tftp 1000000 u-boot.bin.8544ds + erase ffb80000 ffbfffff + cp.b 1000000 ffb80000 80000 + pixis_reset altbank + + +To overwrite the image in the boot flash bank: + + tftp 1000000 u-boot.bin.8544ds + protect off all + erase fff80000 ffffffff + cp.b 1000000 fff80000 80000 + +Other example U-Boot image and flash manipulations examples +can be found in the README.mpc85xxcds file as well. + + +The pixis_reset command +----------------------- +A new command, "pixis_reset", is introduced to reset mpc8641hpcn board +using the FPGA sequencer. When the board restarts, it has the option +of using either the current or alternate flash bank as the boot +image, with or without the watchdog timer enabled, and finally with +or without frequency changes. + +Usage is; + + pixis_reset + pixis_reset altbank + pixis_reset altbank wd + pixis_reset altbank cf + pixis_reset cf + +Examples; + + /* reset to current bank, like "reset" command */ + pixis_reset + + /* reset board but use the to alternate flash bank */ + pixis_reset altbank + + /* reset board, use alternate flash bank with watchdog timer enabled*/ + pixis_reset altbank wd + + /* reset board to alternate bank with frequency changed. + * 40 is SYSCLK, 2.5 is COREPLL ratio, 10 is MPXPLL ratio + */ + pixis-reset altbank cf 40 2.5 10 + +Valid clock choices are in the 8641 Reference Manuals. + + +Using the Device Tree Source File +--------------------------------- +To create the DTB (Device Tree Binary) image file, +use a command similar to this: + + dtc -b 0 -f -I dts -O dtb mpc8544ds.dts > mpc8544ds.dtb + +Likely, that .dts file will come from here; + + linux-2.6/arch/powerpc/boot/dts/mpc8544ds.dts + +After placing the DTB file in your TFTP disk area, +you can download that dtb file using a command like: + + tftp 900000 mpc8544ds.dtb + +Burn it to flash if you want. + + +Booting Linux +------------- + +Place a linux uImage in the TFTP disk area too. + + tftp 1000000 uImage.8544 + tftp 900000 mpc8544ds.dtb + bootm 1000000 - 900000 + +Watch your ethact, netdev and bootargs U-Boot environment variables. +You may want to do something like this too: + + setenv ethact eTSEC3 + setenv netdev eth1 -- cgit From 4ef35e53c693556c54b0c22d6f873de87bade253 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Tue, 14 Aug 2007 09:54:46 +0200 Subject: Coding style cleanup, update CHANGELOG Signed-off-by: Wolfgang Denk --- doc/README.mpc8544ds | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'doc') diff --git a/doc/README.mpc8544ds b/doc/README.mpc8544ds index 14c7f765e4..bf257a0054 100644 --- a/doc/README.mpc8544ds +++ b/doc/README.mpc8544ds @@ -98,7 +98,7 @@ Likely, that .dts file will come from here; linux-2.6/arch/powerpc/boot/dts/mpc8544ds.dts -After placing the DTB file in your TFTP disk area, +After placing the DTB file in your TFTP disk area, you can download that dtb file using a command like: tftp 900000 mpc8544ds.dtb -- cgit From 779e975117a75e91fcebe226a63104dbfb924ab1 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Tue, 14 Aug 2007 14:44:41 +0200 Subject: ppc4xx: Add initial Zeus (PPC405EP) board support Signed-off-by: Stefan Roese --- doc/README.zeus | 73 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 73 insertions(+) create mode 100644 doc/README.zeus (limited to 'doc') diff --git a/doc/README.zeus b/doc/README.zeus new file mode 100644 index 0000000000..1848d8cd38 --- /dev/null +++ b/doc/README.zeus @@ -0,0 +1,73 @@ + +Storage of the board specific values (ethaddr...) +------------------------------------------------- + +The board specific environment variables that should be unique +for each individual board, can be stored in the I2C EEPROM. This +will be done from offset 0x80 with the length of 0x80 bytes. The +following command can be used to store the values here: + +=> setdef de:20:6a:ed:e2:72 de:20:6a:ed:e2:73 AB0001 + + ethaddr eth1addr serial# + +Now those 3 values are stored into the I2C EEPROM. A CRC is added +to make sure that the values get not corrupted. + + +SW-Reset Pushbutton handling: +----------------------------- + +The SW-reset push button is connected to a GPIO input too. This +way U-Boot can "see" how long the SW-reset was pressed, and a +specific action can be taken. Two different actions are supported: + +a) Release after more than 5 seconds and less then 10 seconds: + -> Run POST + + Please note, that the POST test will take a while (approx. 1 min + on the 128MByte board). This is mainly due to the system memory + test. + +b) Release after more than 10 seconds: + -> Restore factory default settings + + The factory default values are restored. The default environment + variables are restored (ipaddr, serverip...) and the board + specific values (ethaddr, eth1addr and serial#) are restored + to the environment from the I2C EEPROM. Also a bootline parameter + is added to the Linux bootline to signal the Linux kernel upon + the next startup, that the factory defaults should be restored. + +The command to check this sw-reset status and act accordingly is + +=> chkreset + +This command is added to the default "bootcmd", so that it is called +automatically upon startup. + +Also, the 2 LED's are used to indicate the current status of this +command (time passed since pushing the button). When the POST test +will be run, the green LED will be switched off, and when the +factory restore will be initiated, the reg LED will be switched off. + + +Loggin of POST results: +----------------------- + +The results of the POST tests are logged in a logbuffer located at the end +of the onboard memory. It can be accessed with the U-Boot command "log": + +=> log show +<4>POST memory PASSED +<4>POST cache PASSED +<4>POST cpu PASSED +<4>POST uart PASSED +<4>POST ethernet PASSED + +The DENX Linux kernel tree has support for this log buffer included. Exactly +this buffer is used for logging of all kernel messages too. By enabling the +compile time option "CONFIG_LOGBUFFER" this support is enabled. This way you +can access the U-Boot log messages from Linux too. + +2007-08-10, Stefan Roese -- cgit