From dedb60fb5bebb9830f76247460b02140bdeb8661 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 8 Jan 2018 16:38:51 +0100 Subject: clk: renesas: Add Gen2 clock core Add common clock code for Renesas RCar Gen2 platforms. Signed-off-by: Marek Vasut Cc: Nobuhiro Iwamatsu --- drivers/clk/renesas/rcar-gen2-cpg.h | 49 +++++++++++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) create mode 100644 drivers/clk/renesas/rcar-gen2-cpg.h (limited to 'drivers/clk/renesas/rcar-gen2-cpg.h') diff --git a/drivers/clk/renesas/rcar-gen2-cpg.h b/drivers/clk/renesas/rcar-gen2-cpg.h new file mode 100644 index 0000000000..913c932620 --- /dev/null +++ b/drivers/clk/renesas/rcar-gen2-cpg.h @@ -0,0 +1,49 @@ +/* + * R-Car Gen2 Clock Pulse Generator + * + * Copyright (C) 2016 Cogent Embedded Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation; version 2 of the License. + */ + +#ifndef __CLK_RENESAS_RCAR_GEN2_CPG_H__ +#define __CLK_RENESAS_RCAR_GEN2_CPG_H__ + +enum rcar_gen2_clk_types { + CLK_TYPE_GEN2_MAIN = CLK_TYPE_CUSTOM, + CLK_TYPE_GEN2_PLL0, + CLK_TYPE_GEN2_PLL1, + CLK_TYPE_GEN2_PLL3, + CLK_TYPE_GEN2_Z, + CLK_TYPE_GEN2_LB, + CLK_TYPE_GEN2_ADSP, + CLK_TYPE_GEN2_SDH, + CLK_TYPE_GEN2_SD0, + CLK_TYPE_GEN2_SD1, + CLK_TYPE_GEN2_QSPI, + CLK_TYPE_GEN2_RCAN, +}; + +struct rcar_gen2_cpg_pll_config { + unsigned int extal_div; + unsigned int pll1_mult; + unsigned int pll3_mult; + unsigned int pll0_mult; /* leave as zero if PLL0CR exists */ +}; + +struct gen2_clk_priv { + void __iomem *base; + struct cpg_mssr_info *info; + struct clk clk_extal; + struct clk clk_extal_usb; + const struct rcar_gen2_cpg_pll_config *cpg_pll_config; +}; + +int gen2_clk_probe(struct udevice *dev); +int gen2_clk_remove(struct udevice *dev); + +extern const struct clk_ops gen2_clk_ops; + +#endif -- cgit