From 49191d259f433f8341a71ab6f821c1d89e2f5092 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Wed, 22 May 2019 00:09:44 -0700 Subject: clk: sifive: Add clock driver for GEMGXL MGMT This adds a clock driver to support the GEMGXL management IP block found in FU540 SoCs to control GEM TX clock operation mode for 10/100/1000 Mbps. Signed-off-by: Bin Meng Reviewed-by: Lukas Auer Tested-by: Lukas Auer --- drivers/clk/sifive/Kconfig | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'drivers/clk/sifive/Kconfig') diff --git a/drivers/clk/sifive/Kconfig b/drivers/clk/sifive/Kconfig index 81fc9f8fda..644881b948 100644 --- a/drivers/clk/sifive/Kconfig +++ b/drivers/clk/sifive/Kconfig @@ -17,3 +17,10 @@ config CLK_SIFIVE_FU540_PRCI Supports the Power Reset Clock interface (PRCI) IP block found in FU540 SoCs. If this kernel is meant to run on a SiFive FU540 SoC, enable this driver. + +config CLK_SIFIVE_GEMGXL_MGMT + bool "GEMGXL management for SiFive FU540 SoCs" + depends on CLK_SIFIVE + help + Supports the GEMGXL management IP block found in FU540 SoCs to + control GEM TX clock operation mode for 10/100/1000 Mbps. -- cgit