From 49191d259f433f8341a71ab6f821c1d89e2f5092 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Wed, 22 May 2019 00:09:44 -0700 Subject: clk: sifive: Add clock driver for GEMGXL MGMT This adds a clock driver to support the GEMGXL management IP block found in FU540 SoCs to control GEM TX clock operation mode for 10/100/1000 Mbps. Signed-off-by: Bin Meng Reviewed-by: Lukas Auer Tested-by: Lukas Auer --- drivers/clk/sifive/Makefile | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/clk/sifive/Makefile') diff --git a/drivers/clk/sifive/Makefile b/drivers/clk/sifive/Makefile index 1155e07e37..f8263e79b7 100644 --- a/drivers/clk/sifive/Makefile +++ b/drivers/clk/sifive/Makefile @@ -3,3 +3,5 @@ obj-$(CONFIG_CLK_ANALOGBITS_WRPLL_CLN28HPC) += wrpll-cln28hpc.o obj-$(CONFIG_CLK_SIFIVE_FU540_PRCI) += fu540-prci.o + +obj-$(CONFIG_CLK_SIFIVE_GEMGXL_MGMT) += gemgxl-mgmt.o -- cgit