From 0d47bc70565102388c957ead7deac4b2eaa3dfba Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Sat, 22 Dec 2018 21:32:49 +0530 Subject: clk: Add Allwinner A64 CLK driver Add initial clock driver for Allwinner A64. Implement USB clock enable and disable functions for OHCI, EHCI, OTG and USBPHY gate and clock registers via ccu clk gate table. Signed-off-by: Jagan Teki Acked-by: Maxime Ripard --- drivers/clk/sunxi/Makefile | 9 +++++++++ 1 file changed, 9 insertions(+) create mode 100644 drivers/clk/sunxi/Makefile (limited to 'drivers/clk/sunxi/Makefile') diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile new file mode 100644 index 0000000000..fb20d28333 --- /dev/null +++ b/drivers/clk/sunxi/Makefile @@ -0,0 +1,9 @@ +# +# Copyright (C) 2018 Amarula Solutions. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-$(CONFIG_CLK_SUNXI) += clk_sunxi.o + +obj-$(CONFIG_CLK_SUN50I_A64) += clk_a64.o -- cgit