From ab05406e73284e194ceffb956d9bcd957b6c8c00 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 13 Oct 2017 19:22:00 +0900 Subject: clk: uniphier: add PXs3 clock data Add basic clock data for Socionext's new SoC PXs3. Signed-off-by: Masahiro Yamada --- drivers/clk/uniphier/clk-uniphier-core.c | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'drivers/clk/uniphier/clk-uniphier-core.c') diff --git a/drivers/clk/uniphier/clk-uniphier-core.c b/drivers/clk/uniphier/clk-uniphier-core.c index 3d1d411e79..9a7d03aa59 100644 --- a/drivers/clk/uniphier/clk-uniphier-core.c +++ b/drivers/clk/uniphier/clk-uniphier-core.c @@ -296,6 +296,10 @@ static const struct udevice_id uniphier_clk_match[] = { .compatible = "socionext,uniphier-ld20-clock", .data = (ulong)uniphier_ld20_sys_clk_data, }, + { + .compatible = "socionext,uniphier-pxs3-clock", + .data = (ulong)uniphier_pxs3_sys_clk_data, + }, /* Media I/O clock */ { .compatible = "socionext,uniphier-ld4-mio-clock", @@ -325,6 +329,10 @@ static const struct udevice_id uniphier_clk_match[] = { .compatible = "socionext,uniphier-ld20-sd-clock", .data = (ulong)uniphier_mio_clk_data, }, + { + .compatible = "socionext,uniphier-pxs3-sd-clock", + .data = (ulong)uniphier_mio_clk_data, + }, { /* sentinel */ } }; -- cgit