From 544acb07ecebc096c9449e675481ba280311fb0b Mon Sep 17 00:00:00 2001 From: Kevin Smith Date: Fri, 23 Oct 2015 17:53:19 +0000 Subject: arm: mvebu: a38x: Remove unsupported topologies A lot of extra configuration information was left over in the Marvell serdes and DDR3 initialization code for boards that U-boot does not support. Remove this extra config information, and the concept of fixing up board topologies with information loaded from an EEPROM. If this needs to be done, it should be handled in the board file, not in core code. Signed-off-by: Kevin Smith Acked-by: Stefan Roese Cc: Dirk Eibach Cc: Luka Perkov --- drivers/ddr/marvell/a38x/ddr3_a38x.h | 5 --- drivers/ddr/marvell/a38x/ddr3_init.c | 72 ------------------------------------ 2 files changed, 77 deletions(-) (limited to 'drivers/ddr/marvell') diff --git a/drivers/ddr/marvell/a38x/ddr3_a38x.h b/drivers/ddr/marvell/a38x/ddr3_a38x.h index 49621bc133..1ed517446f 100644 --- a/drivers/ddr/marvell/a38x/ddr3_a38x.h +++ b/drivers/ddr/marvell/a38x/ddr3_a38x.h @@ -12,11 +12,6 @@ #include "ddr3_hws_hw_training_def.h" -/* Allow topolgy update from board TWSI device*/ -#if !defined(CONFIG_CUSTOMER_BOARD_SUPPORT) -#define MV_DDR_TOPOLOGY_UPDATE_FROM_TWSI -#endif - #define ECC_SUPPORT /* right now, we're not supporting this in mainline */ diff --git a/drivers/ddr/marvell/a38x/ddr3_init.c b/drivers/ddr/marvell/a38x/ddr3_init.c index d6ed8e03e9..556f877039 100644 --- a/drivers/ddr/marvell/a38x/ddr3_init.c +++ b/drivers/ddr/marvell/a38x/ddr3_init.c @@ -96,7 +96,6 @@ u8 generic_init_controller = 1; static u32 ddr3_get_static_ddr_mode(void); #endif static int ddr3_hws_tune_training_params(u8 dev_num); -static int ddr3_update_topology_map(struct hws_topology_map *topology_map); /* device revision */ #define DEV_VERSION_ID_REG 0x1823c @@ -383,14 +382,6 @@ int ddr3_init(void) } #endif - /* Load topology for New Training IP */ - status = ddr3_load_topology_map(); - if (MV_OK != status) { - printf("%s Training Sequence topology load - FAILED\n", - ddr_type); - return status; - } - /* Tune training algo paramteres */ status = ddr3_hws_tune_training_params(0); if (MV_OK != status) @@ -539,27 +530,6 @@ u32 ddr3_get_cs_num_from_reg(void) return cs_count; } -/* - * Name: ddr3_load_topology_map - * Desc: - * Args: - * Notes: - * Returns: - */ -int ddr3_load_topology_map(void) -{ - struct hws_topology_map *tm = ddr3_get_topology_map(); - -#if defined(MV_DDR_TOPOLOGY_UPDATE_FROM_TWSI) - /* Update topology data */ - if (MV_OK != ddr3_update_topology_map(tm)) { - DEBUG_INIT_FULL_S("Failed update of DDR3 Topology map\n"); - } -#endif - - return MV_OK; -} - void get_target_freq(u32 freq_mode, u32 *ddr_freq, u32 *hclk_ps) { u32 tmp, hclk = 200; @@ -781,48 +751,6 @@ int ddr3_calc_mem_cs_size(u32 cs, u32 *cs_size) return MV_OK; } -#if defined(MV_DDR_TOPOLOGY_UPDATE_FROM_TWSI) -/* - * Name: ddr3_update_topology_map - * Desc: - * Args: - * Notes: Update topology map by Sat_r values - * Returns: - */ -static int ddr3_update_topology_map(struct hws_topology_map *tm) -{ - struct topology_update_info topology_update_info; - - topology_update_info.update_width = 0; - topology_update_info.update_ecc = 0; - topology_update_info.update_ecc_pup3_mode = 0; - sys_env_get_topology_update_info(&topology_update_info); - if (topology_update_info.update_width) { - tm->bus_act_mask &= - ~(TOPOLOGY_UPDATE_WIDTH_32BIT_MASK); - if (topology_update_info.width == TOPOLOGY_UPDATE_WIDTH_16BIT) - tm->bus_act_mask = - TOPOLOGY_UPDATE_WIDTH_16BIT_MASK; - else - tm->bus_act_mask = - TOPOLOGY_UPDATE_WIDTH_32BIT_MASK; - } - - if (topology_update_info.update_ecc) { - if (topology_update_info.ecc == TOPOLOGY_UPDATE_ECC_OFF) { - tm->bus_act_mask &= - ~(1 << topology_update_info.ecc_pup_mode_offset); - } else { - tm->bus_act_mask |= - topology_update_info. - ecc << topology_update_info.ecc_pup_mode_offset; - } - } - - return MV_OK; -} -#endif - /* * Name: ddr3_hws_tune_training_params * Desc: -- cgit From a21b4f0f9977915f9a609fe8cc8fba2d1a3ba629 Mon Sep 17 00:00:00 2001 From: Dirk Eibach Date: Wed, 28 Oct 2015 16:44:14 +0100 Subject: arm: mvebu: Fix SAR1_CPU_CORE_MASK SAR1_CPU_CORE_MASK was wrong, probably copy/paste from another architecture. Signed-off-by: Dirk Eibach Reviewed-by: Stefan Roese --- drivers/ddr/marvell/a38x/ddr3_hws_hw_training_def.h | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) (limited to 'drivers/ddr/marvell') diff --git a/drivers/ddr/marvell/a38x/ddr3_hws_hw_training_def.h b/drivers/ddr/marvell/a38x/ddr3_hws_hw_training_def.h index 7500a72403..06d0ab10aa 100644 --- a/drivers/ddr/marvell/a38x/ddr3_hws_hw_training_def.h +++ b/drivers/ddr/marvell/a38x/ddr3_hws_hw_training_def.h @@ -23,8 +23,8 @@ #define CPU_CONFIGURATION_REG(id) (0x21800 + (id * 0x100)) #define CPU_MRVL_ID_OFFSET 0x10 -#define SAR1_CPU_CORE_MASK 0x00000018 -#define SAR1_CPU_CORE_OFFSET 3 +#define SAR1_CPU_CORE_MASK 0x38000000 +#define SAR1_CPU_CORE_OFFSET 27 #define NEW_FABRIC_TWSI_ADDR 0x4e #ifdef DB_784MP_GP @@ -461,7 +461,4 @@ #define CLK_CPU_2200 13 #define CLK_CPU_2400 14 -#define SAR1_CPU_CORE_MASK 0x00000018 -#define SAR1_CPU_CORE_OFFSET 3 - #endif /* _DDR3_HWS_HW_TRAINING_DEF_H */ -- cgit