From bf1ae4426b89bd8b3e036e012acc4bc88fec4c6e Mon Sep 17 00:00:00 2001 From: Vikas Manocha Date: Mon, 10 Apr 2017 15:02:51 -0700 Subject: stm32f7: sdram: move sdram driver code to ram drivers area Signed-off-by: Vikas Manocha cc: Christophe KERELLO --- drivers/ram/stm32_sdram.c | 119 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 119 insertions(+) create mode 100644 drivers/ram/stm32_sdram.c (limited to 'drivers/ram/stm32_sdram.c') diff --git a/drivers/ram/stm32_sdram.c b/drivers/ram/stm32_sdram.c new file mode 100644 index 0000000000..13f896484e --- /dev/null +++ b/drivers/ram/stm32_sdram.c @@ -0,0 +1,119 @@ +/* + * (C) Copyright 2017 + * Vikas Manocha, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +static inline u32 _ns2clk(u32 ns, u32 freq) +{ + u32 tmp = freq/1000000; + return (tmp * ns) / 1000; +} + +#define NS2CLK(ns) (_ns2clk(ns, freq)) + +/* + * Following are timings for IS42S16400J, from corresponding datasheet + */ +#define SDRAM_CAS 3 /* 3 cycles */ +#define SDRAM_NB 1 /* Number of banks */ +#define SDRAM_MWID 1 /* 16 bit memory */ + +#define SDRAM_NR 0x1 /* 12-bit row */ +#define SDRAM_NC 0x0 /* 8-bit col */ +#define SDRAM_RBURST 0x1 /* Single read requests always as bursts */ +#define SDRAM_RPIPE 0x0 /* No HCLK clock cycle delay */ + +#define SDRAM_TRRD NS2CLK(12) +#define SDRAM_TRCD NS2CLK(18) +#define SDRAM_TRP NS2CLK(18) +#define SDRAM_TRAS NS2CLK(42) +#define SDRAM_TRC NS2CLK(60) +#define SDRAM_TRFC NS2CLK(60) +#define SDRAM_TCDL (1 - 1) +#define SDRAM_TRDL NS2CLK(12) +#define SDRAM_TBDL (1 - 1) +#define SDRAM_TREF (NS2CLK(64000000 / 8192) - 20) +#define SDRAM_TCCD (1 - 1) + +#define SDRAM_TXSR SDRAM_TRFC /* Row cycle time after precharge */ +#define SDRAM_TMRD 1 /* Page 10, Mode Register Set */ + + +/* Last data in to row precharge, need also comply ineq on page 1648 */ +#define SDRAM_TWR max(\ + (int)max((int)SDRAM_TRDL, (int)(SDRAM_TRAS - SDRAM_TRCD)), \ + (int)(SDRAM_TRC - SDRAM_TRCD - SDRAM_TRP)\ + ) + + +#define SDRAM_MODE_BL_SHIFT 0 +#define SDRAM_MODE_CAS_SHIFT 4 +#define SDRAM_MODE_BL 0 +#define SDRAM_MODE_CAS SDRAM_CAS + +int stm32_sdram_init(void) +{ + u32 freq; + + /* + * Get frequency for NS2CLK calculation. + */ + freq = clock_get(CLOCK_AHB) / CONFIG_SYS_RAM_FREQ_DIV; + + writel(CONFIG_SYS_RAM_FREQ_DIV << FMC_SDCR_SDCLK_SHIFT + | SDRAM_CAS << FMC_SDCR_CAS_SHIFT + | SDRAM_NB << FMC_SDCR_NB_SHIFT + | SDRAM_MWID << FMC_SDCR_MWID_SHIFT + | SDRAM_NR << FMC_SDCR_NR_SHIFT + | SDRAM_NC << FMC_SDCR_NC_SHIFT + | SDRAM_RPIPE << FMC_SDCR_RPIPE_SHIFT + | SDRAM_RBURST << FMC_SDCR_RBURST_SHIFT, + &STM32_SDRAM_FMC->sdcr1); + + writel(SDRAM_TRCD << FMC_SDTR_TRCD_SHIFT + | SDRAM_TRP << FMC_SDTR_TRP_SHIFT + | SDRAM_TWR << FMC_SDTR_TWR_SHIFT + | SDRAM_TRC << FMC_SDTR_TRC_SHIFT + | SDRAM_TRAS << FMC_SDTR_TRAS_SHIFT + | SDRAM_TXSR << FMC_SDTR_TXSR_SHIFT + | SDRAM_TMRD << FMC_SDTR_TMRD_SHIFT, + &STM32_SDRAM_FMC->sdtr1); + + writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_START_CLOCK, + &STM32_SDRAM_FMC->sdcmr); + udelay(200); /* 200 us delay, page 10, "Power-Up" */ + FMC_BUSY_WAIT(); + + writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_PRECHARGE, + &STM32_SDRAM_FMC->sdcmr); + udelay(100); + FMC_BUSY_WAIT(); + + writel((FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_AUTOREFRESH + | 7 << FMC_SDCMR_NRFS_SHIFT), &STM32_SDRAM_FMC->sdcmr); + udelay(100); + FMC_BUSY_WAIT(); + + writel(FMC_SDCMR_BANK_1 | (SDRAM_MODE_BL << SDRAM_MODE_BL_SHIFT + | SDRAM_MODE_CAS << SDRAM_MODE_CAS_SHIFT) + << FMC_SDCMR_MODE_REGISTER_SHIFT | FMC_SDCMR_MODE_WRITE_MODE, + &STM32_SDRAM_FMC->sdcmr); + udelay(100); + FMC_BUSY_WAIT(); + + writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_NORMAL, + &STM32_SDRAM_FMC->sdcmr); + FMC_BUSY_WAIT(); + + /* Refresh timer */ + writel(SDRAM_TREF, &STM32_SDRAM_FMC->sdrtr); + + return 0; +} -- cgit From 910a52ede3d7cf75b3157b9a3ef6f40879a38194 Mon Sep 17 00:00:00 2001 From: Vikas Manocha Date: Mon, 10 Apr 2017 15:02:52 -0700 Subject: stm32f7: dm: add driver model support for sdram Signed-off-by: Vikas Manocha cc: Christophe KERELLO --- drivers/ram/stm32_sdram.c | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) (limited to 'drivers/ram/stm32_sdram.c') diff --git a/drivers/ram/stm32_sdram.c b/drivers/ram/stm32_sdram.c index 13f896484e..67be61f01a 100644 --- a/drivers/ram/stm32_sdram.c +++ b/drivers/ram/stm32_sdram.c @@ -6,6 +6,8 @@ */ #include +#include +#include #include #include #include @@ -117,3 +119,32 @@ int stm32_sdram_init(void) return 0; } + +static int stm32_fmc_probe(struct udevice *dev) +{ + stm32_sdram_init(); + return 0; +} + +static int stm32_fmc_get_info(struct udevice *dev, struct ram_info *info) +{ + info->size = CONFIG_SYS_RAM_SIZE; + return 0; +} + +static struct ram_ops stm32_fmc_ops = { + .get_info = stm32_fmc_get_info, +}; + +static const struct udevice_id stm32_fmc_ids[] = { + { .compatible = "st,stm32-fmc" }, + { } +}; + +U_BOOT_DRIVER(stm32_fmc) = { + .name = "stm32_fmc", + .id = UCLASS_RAM, + .of_match = stm32_fmc_ids, + .ops = &stm32_fmc_ops, + .probe = stm32_fmc_probe, +}; -- cgit From d0b24c1aa96729d4d9fee02e2c60fc920068c6c5 Mon Sep 17 00:00:00 2001 From: Vikas Manocha Date: Mon, 10 Apr 2017 15:02:55 -0700 Subject: stm32f7: use clock driver to enable sdram controller clock This patch also removes the sdram/fmc clock enable from board specific code. Signed-off-by: Vikas Manocha cc: Christophe KERELLO --- drivers/ram/stm32_sdram.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'drivers/ram/stm32_sdram.c') diff --git a/drivers/ram/stm32_sdram.c b/drivers/ram/stm32_sdram.c index 67be61f01a..67d885572d 100644 --- a/drivers/ram/stm32_sdram.c +++ b/drivers/ram/stm32_sdram.c @@ -6,6 +6,7 @@ */ #include +#include #include #include #include @@ -122,6 +123,20 @@ int stm32_sdram_init(void) static int stm32_fmc_probe(struct udevice *dev) { +#ifdef CONFIG_CLK + int ret; + struct clk clk; + ret = clk_get_by_index(dev, 0, &clk); + if (ret < 0) + return ret; + + ret = clk_enable(&clk); + + if (ret) { + dev_err(dev, "failed to enable clock\n"); + return ret; + } +#endif stm32_sdram_init(); return 0; } -- cgit From 6c9a10034a21680c4b2595d9b6468a767dedebca Mon Sep 17 00:00:00 2001 From: Vikas Manocha Date: Mon, 10 Apr 2017 15:02:56 -0700 Subject: stm32f7: sdram: use sdram device tree node to configure sdram controller Signed-off-by: Vikas Manocha cc: Christophe KERELLO --- drivers/ram/stm32_sdram.c | 144 +++++++++++++++++++++++++++++----------------- 1 file changed, 91 insertions(+), 53 deletions(-) (limited to 'drivers/ram/stm32_sdram.c') diff --git a/drivers/ram/stm32_sdram.c b/drivers/ram/stm32_sdram.c index 67d885572d..eb1ab945b5 100644 --- a/drivers/ram/stm32_sdram.c +++ b/drivers/ram/stm32_sdram.c @@ -13,6 +13,31 @@ #include #include +DECLARE_GLOBAL_DATA_PTR; + +struct stm32_sdram_control { + u8 no_columns; + u8 no_rows; + u8 memory_width; + u8 no_banks; + u8 cas_latency; + u8 rd_burst; + u8 rd_pipe_delay; +}; + +struct stm32_sdram_timing { + u8 tmrd; + u8 txsr; + u8 tras; + u8 trc; + u8 trp; + u8 trcd; +}; +struct stm32_sdram_params { + u8 no_sdram_banks; + struct stm32_sdram_control sdram_control; + struct stm32_sdram_timing sdram_timing; +}; static inline u32 _ns2clk(u32 ns, u32 freq) { u32 tmp = freq/1000000; @@ -21,73 +46,53 @@ static inline u32 _ns2clk(u32 ns, u32 freq) #define NS2CLK(ns) (_ns2clk(ns, freq)) -/* - * Following are timings for IS42S16400J, from corresponding datasheet - */ -#define SDRAM_CAS 3 /* 3 cycles */ -#define SDRAM_NB 1 /* Number of banks */ -#define SDRAM_MWID 1 /* 16 bit memory */ - -#define SDRAM_NR 0x1 /* 12-bit row */ -#define SDRAM_NC 0x0 /* 8-bit col */ -#define SDRAM_RBURST 0x1 /* Single read requests always as bursts */ -#define SDRAM_RPIPE 0x0 /* No HCLK clock cycle delay */ - -#define SDRAM_TRRD NS2CLK(12) -#define SDRAM_TRCD NS2CLK(18) -#define SDRAM_TRP NS2CLK(18) -#define SDRAM_TRAS NS2CLK(42) -#define SDRAM_TRC NS2CLK(60) -#define SDRAM_TRFC NS2CLK(60) -#define SDRAM_TCDL (1 - 1) -#define SDRAM_TRDL NS2CLK(12) -#define SDRAM_TBDL (1 - 1) #define SDRAM_TREF (NS2CLK(64000000 / 8192) - 20) -#define SDRAM_TCCD (1 - 1) - -#define SDRAM_TXSR SDRAM_TRFC /* Row cycle time after precharge */ -#define SDRAM_TMRD 1 /* Page 10, Mode Register Set */ - - -/* Last data in to row precharge, need also comply ineq on page 1648 */ -#define SDRAM_TWR max(\ - (int)max((int)SDRAM_TRDL, (int)(SDRAM_TRAS - SDRAM_TRCD)), \ - (int)(SDRAM_TRC - SDRAM_TRCD - SDRAM_TRP)\ - ) - #define SDRAM_MODE_BL_SHIFT 0 #define SDRAM_MODE_CAS_SHIFT 4 #define SDRAM_MODE_BL 0 -#define SDRAM_MODE_CAS SDRAM_CAS +#define SDRAM_MODE_CAS 3 + +#define SDRAM_TRDL 12 -int stm32_sdram_init(void) +int stm32_sdram_init(struct udevice *dev) { u32 freq; + u32 sdram_twr; + struct stm32_sdram_params *params = dev_get_platdata(dev); /* * Get frequency for NS2CLK calculation. */ freq = clock_get(CLOCK_AHB) / CONFIG_SYS_RAM_FREQ_DIV; + debug("%s, sdram freq = %d\n", __func__, freq); + + /* Last data in to row precharge, need also comply ineq on page 1648 */ + sdram_twr = max( + max(SDRAM_TRDL, params->sdram_timing.tras + - params->sdram_timing.trcd), + params->sdram_timing.trc - params->sdram_timing.trcd + - params->sdram_timing.trp + ); writel(CONFIG_SYS_RAM_FREQ_DIV << FMC_SDCR_SDCLK_SHIFT - | SDRAM_CAS << FMC_SDCR_CAS_SHIFT - | SDRAM_NB << FMC_SDCR_NB_SHIFT - | SDRAM_MWID << FMC_SDCR_MWID_SHIFT - | SDRAM_NR << FMC_SDCR_NR_SHIFT - | SDRAM_NC << FMC_SDCR_NC_SHIFT - | SDRAM_RPIPE << FMC_SDCR_RPIPE_SHIFT - | SDRAM_RBURST << FMC_SDCR_RBURST_SHIFT, - &STM32_SDRAM_FMC->sdcr1); - - writel(SDRAM_TRCD << FMC_SDTR_TRCD_SHIFT - | SDRAM_TRP << FMC_SDTR_TRP_SHIFT - | SDRAM_TWR << FMC_SDTR_TWR_SHIFT - | SDRAM_TRC << FMC_SDTR_TRC_SHIFT - | SDRAM_TRAS << FMC_SDTR_TRAS_SHIFT - | SDRAM_TXSR << FMC_SDTR_TXSR_SHIFT - | SDRAM_TMRD << FMC_SDTR_TMRD_SHIFT, - &STM32_SDRAM_FMC->sdtr1); + | params->sdram_control.cas_latency << FMC_SDCR_CAS_SHIFT + | params->sdram_control.no_banks << FMC_SDCR_NB_SHIFT + | params->sdram_control.memory_width << FMC_SDCR_MWID_SHIFT + | params->sdram_control.no_rows << FMC_SDCR_NR_SHIFT + | params->sdram_control.no_columns << FMC_SDCR_NC_SHIFT + | params->sdram_control.rd_pipe_delay << FMC_SDCR_RPIPE_SHIFT + | params->sdram_control.rd_burst << FMC_SDCR_RBURST_SHIFT, + &STM32_SDRAM_FMC->sdcr1); + + writel(NS2CLK(params->sdram_timing.trcd) << FMC_SDTR_TRCD_SHIFT + | NS2CLK(params->sdram_timing.trp) << FMC_SDTR_TRP_SHIFT + | NS2CLK(sdram_twr) << FMC_SDTR_TWR_SHIFT + | NS2CLK(params->sdram_timing.trc) << FMC_SDTR_TRC_SHIFT + | NS2CLK(params->sdram_timing.tras) << FMC_SDTR_TRAS_SHIFT + | NS2CLK(params->sdram_timing.txsr) << FMC_SDTR_TXSR_SHIFT + | NS2CLK(params->sdram_timing.tmrd) << FMC_SDTR_TMRD_SHIFT, + &STM32_SDRAM_FMC->sdtr1); writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_START_CLOCK, &STM32_SDRAM_FMC->sdcmr); @@ -121,11 +126,39 @@ int stm32_sdram_init(void) return 0; } +static int stm32_fmc_ofdata_to_platdata(struct udevice *dev) +{ + int ret; + int node = dev->of_offset; + const void *blob = gd->fdt_blob; + struct stm32_sdram_params *params = dev_get_platdata(dev); + + params->no_sdram_banks = fdtdec_get_uint(blob, node, "mr-nbanks", 1); + debug("%s, no of banks = %d\n", __func__, params->no_sdram_banks); + + fdt_for_each_subnode(node, blob, node) { + ret = fdtdec_get_byte_array(blob, node, "st,sdram-control", + (u8 *)¶ms->sdram_control, + sizeof(params->sdram_control)); + if (ret) + return ret; + + ret = fdtdec_get_byte_array(blob, node, "st,sdram-timing", + (u8 *)¶ms->sdram_timing, + sizeof(params->sdram_timing)); + if (ret) + return ret; + } + + return 0; +} + static int stm32_fmc_probe(struct udevice *dev) { #ifdef CONFIG_CLK int ret; struct clk clk; + ret = clk_get_by_index(dev, 0, &clk); if (ret < 0) return ret; @@ -137,7 +170,10 @@ static int stm32_fmc_probe(struct udevice *dev) return ret; } #endif - stm32_sdram_init(); + ret = stm32_sdram_init(dev); + if (ret) + return ret; + return 0; } @@ -161,5 +197,7 @@ U_BOOT_DRIVER(stm32_fmc) = { .id = UCLASS_RAM, .of_match = stm32_fmc_ids, .ops = &stm32_fmc_ops, + .ofdata_to_platdata = stm32_fmc_ofdata_to_platdata, .probe = stm32_fmc_probe, + .platdata_auto_alloc_size = sizeof(struct stm32_sdram_params), }; -- cgit From 57af3cc32a7b39bc26987780fbca109e206d1c34 Mon Sep 17 00:00:00 2001 From: Vikas Manocha Date: Mon, 10 Apr 2017 15:03:01 -0700 Subject: stm32f7: stm32f746-disco: read memory info from device tree Signed-off-by: Vikas Manocha cc: Christophe KERELLO --- drivers/ram/stm32_sdram.c | 1 - 1 file changed, 1 deletion(-) (limited to 'drivers/ram/stm32_sdram.c') diff --git a/drivers/ram/stm32_sdram.c b/drivers/ram/stm32_sdram.c index eb1ab945b5..5e09f35b91 100644 --- a/drivers/ram/stm32_sdram.c +++ b/drivers/ram/stm32_sdram.c @@ -179,7 +179,6 @@ static int stm32_fmc_probe(struct udevice *dev) static int stm32_fmc_get_info(struct udevice *dev, struct ram_info *info) { - info->size = CONFIG_SYS_RAM_SIZE; return 0; } -- cgit From bfea69ad27936d619c0eb3c1be55cc292df8d7f5 Mon Sep 17 00:00:00 2001 From: Vikas Manocha Date: Mon, 10 Apr 2017 15:03:03 -0700 Subject: stm32f7: sdram: correct sdram configuration as per micron sdram Actually the sdram memory on stm32f746 discovery board is micron part MT48LC_4M32_B2B5_6A. This patch does the modification required in the device tree node & driver for the same. Also we are passing here all the timing parameters in terms of clock cycles, so no need to convert time(ns or ms) to cycles. Signed-off-by: Vikas Manocha cc: Christophe KERELLO --- drivers/ram/stm32_sdram.c | 55 ++++++++++++++--------------------------------- 1 file changed, 16 insertions(+), 39 deletions(-) (limited to 'drivers/ram/stm32_sdram.c') diff --git a/drivers/ram/stm32_sdram.c b/drivers/ram/stm32_sdram.c index 5e09f35b91..48b4979e62 100644 --- a/drivers/ram/stm32_sdram.c +++ b/drivers/ram/stm32_sdram.c @@ -21,6 +21,7 @@ struct stm32_sdram_control { u8 memory_width; u8 no_banks; u8 cas_latency; + u8 sdclk; u8 rd_burst; u8 rd_pipe_delay; }; @@ -31,51 +32,25 @@ struct stm32_sdram_timing { u8 tras; u8 trc; u8 trp; + u8 twr; u8 trcd; }; struct stm32_sdram_params { u8 no_sdram_banks; struct stm32_sdram_control sdram_control; struct stm32_sdram_timing sdram_timing; + u32 sdram_ref_count; }; -static inline u32 _ns2clk(u32 ns, u32 freq) -{ - u32 tmp = freq/1000000; - return (tmp * ns) / 1000; -} - -#define NS2CLK(ns) (_ns2clk(ns, freq)) - -#define SDRAM_TREF (NS2CLK(64000000 / 8192) - 20) #define SDRAM_MODE_BL_SHIFT 0 #define SDRAM_MODE_CAS_SHIFT 4 #define SDRAM_MODE_BL 0 -#define SDRAM_MODE_CAS 3 - -#define SDRAM_TRDL 12 int stm32_sdram_init(struct udevice *dev) { - u32 freq; - u32 sdram_twr; struct stm32_sdram_params *params = dev_get_platdata(dev); - /* - * Get frequency for NS2CLK calculation. - */ - freq = clock_get(CLOCK_AHB) / CONFIG_SYS_RAM_FREQ_DIV; - debug("%s, sdram freq = %d\n", __func__, freq); - - /* Last data in to row precharge, need also comply ineq on page 1648 */ - sdram_twr = max( - max(SDRAM_TRDL, params->sdram_timing.tras - - params->sdram_timing.trcd), - params->sdram_timing.trc - params->sdram_timing.trcd - - params->sdram_timing.trp - ); - - writel(CONFIG_SYS_RAM_FREQ_DIV << FMC_SDCR_SDCLK_SHIFT + writel(params->sdram_control.sdclk << FMC_SDCR_SDCLK_SHIFT | params->sdram_control.cas_latency << FMC_SDCR_CAS_SHIFT | params->sdram_control.no_banks << FMC_SDCR_NB_SHIFT | params->sdram_control.memory_width << FMC_SDCR_MWID_SHIFT @@ -85,13 +60,13 @@ int stm32_sdram_init(struct udevice *dev) | params->sdram_control.rd_burst << FMC_SDCR_RBURST_SHIFT, &STM32_SDRAM_FMC->sdcr1); - writel(NS2CLK(params->sdram_timing.trcd) << FMC_SDTR_TRCD_SHIFT - | NS2CLK(params->sdram_timing.trp) << FMC_SDTR_TRP_SHIFT - | NS2CLK(sdram_twr) << FMC_SDTR_TWR_SHIFT - | NS2CLK(params->sdram_timing.trc) << FMC_SDTR_TRC_SHIFT - | NS2CLK(params->sdram_timing.tras) << FMC_SDTR_TRAS_SHIFT - | NS2CLK(params->sdram_timing.txsr) << FMC_SDTR_TXSR_SHIFT - | NS2CLK(params->sdram_timing.tmrd) << FMC_SDTR_TMRD_SHIFT, + writel(params->sdram_timing.trcd << FMC_SDTR_TRCD_SHIFT + | params->sdram_timing.trp << FMC_SDTR_TRP_SHIFT + | params->sdram_timing.twr << FMC_SDTR_TWR_SHIFT + | params->sdram_timing.trc << FMC_SDTR_TRC_SHIFT + | params->sdram_timing.tras << FMC_SDTR_TRAS_SHIFT + | params->sdram_timing.txsr << FMC_SDTR_TXSR_SHIFT + | params->sdram_timing.tmrd << FMC_SDTR_TMRD_SHIFT, &STM32_SDRAM_FMC->sdtr1); writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_START_CLOCK, @@ -110,7 +85,7 @@ int stm32_sdram_init(struct udevice *dev) FMC_BUSY_WAIT(); writel(FMC_SDCMR_BANK_1 | (SDRAM_MODE_BL << SDRAM_MODE_BL_SHIFT - | SDRAM_MODE_CAS << SDRAM_MODE_CAS_SHIFT) + | params->sdram_control.cas_latency << SDRAM_MODE_CAS_SHIFT) << FMC_SDCMR_MODE_REGISTER_SHIFT | FMC_SDCMR_MODE_WRITE_MODE, &STM32_SDRAM_FMC->sdcmr); udelay(100); @@ -121,7 +96,7 @@ int stm32_sdram_init(struct udevice *dev) FMC_BUSY_WAIT(); /* Refresh timer */ - writel(SDRAM_TREF, &STM32_SDRAM_FMC->sdrtr); + writel((params->sdram_ref_count) << 1, &STM32_SDRAM_FMC->sdrtr); return 0; } @@ -142,12 +117,14 @@ static int stm32_fmc_ofdata_to_platdata(struct udevice *dev) sizeof(params->sdram_control)); if (ret) return ret; - ret = fdtdec_get_byte_array(blob, node, "st,sdram-timing", (u8 *)¶ms->sdram_timing, sizeof(params->sdram_timing)); if (ret) return ret; + + params->sdram_ref_count = fdtdec_get_int(blob, node, + "st,sdram-refcount", 8196); } return 0; -- cgit