From b215fb3f34befbff084550b67ee15c0363e9e9de Mon Sep 17 00:00:00 2001 From: Sanchayan Maity Date: Tue, 11 Apr 2017 11:12:09 +0530 Subject: Convert CONFIG_FSL_DCU_FB to Kconfig Rename CONFIG_FSL_DCU_FB to CONFIG_VIDEO_FSL_DCU_FB and convert it to Kconfig. Signed-off-by: Sanchayan Maity Reviewed-by: Stefan Agner Reviewed-by: Alison Wang --- drivers/video/Kconfig | 7 +++++++ drivers/video/Makefile | 2 +- 2 files changed, 8 insertions(+), 1 deletion(-) (limited to 'drivers/video') diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index 2069576958..6aab8af1b3 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -395,6 +395,13 @@ config VIDEO_IVYBRIDGE_IGD a special tool which configures the VGA ROM, but the graphics resolution can be selected in U-Boot. +config VIDEO_FSL_DCU_FB + bool "Enable Freescale Display Control Unit" + depends on VIDEO + help + This enables support for Freescale Display Control Unit (DCU4) + module found on Freescale Vybrid and QorIQ family of SoCs. + config VIDEO_ROCKCHIP bool "Enable Rockchip video support" depends on DM_VIDEO diff --git a/drivers/video/Makefile b/drivers/video/Makefile index db34904a9a..7cd6d28658 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -27,7 +27,7 @@ obj-$(CONFIG_ATMEL_HLCD) += atmel_hlcdfb.o obj-$(CONFIG_ATMEL_LCD) += atmel_lcdfb.o obj-$(CONFIG_CFB_CONSOLE) += cfb_console.o obj-$(CONFIG_FSL_DIU_FB) += fsl_diu_fb.o videomodes.o -obj-$(CONFIG_FSL_DCU_FB) += fsl_dcu_fb.o videomodes.o +obj-$(CONFIG_VIDEO_FSL_DCU_FB) += fsl_dcu_fb.o videomodes.o obj-$(CONFIG_L5F31188) += l5f31188.o obj-$(CONFIG_MPC8XX_LCD) += mpc8xx_lcd.o obj-$(CONFIG_PXA_LCD) += pxa_lcd.o -- cgit From 77810e638efb5cdfed0c2f55149b59dca6f519d9 Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Tue, 11 Apr 2017 11:12:10 +0530 Subject: video: fsl_dcu_fb: fix framebuffer to the end of memory Fix the framebuffer location to the very end of the available memory. This allows to remove the area from available memory for the kernel, which in turn allows to display the splash screen through the Linux kernel boot process. Ideas has been taken from the sunxi display driver, e.g. 20779ec3a5 ("sunxi: video: Dynamically reserve framebuffer memory") Signed-off-by: Stefan Agner Signed-off-by: Sanchayan Maity --- drivers/video/Kconfig | 8 ++++++++ drivers/video/fsl_dcu_fb.c | 45 ++++++++++++++++++++++++++++++++++++++++++--- 2 files changed, 50 insertions(+), 3 deletions(-) (limited to 'drivers/video') diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index 6aab8af1b3..d1b017cfad 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -402,6 +402,14 @@ config VIDEO_FSL_DCU_FB This enables support for Freescale Display Control Unit (DCU4) module found on Freescale Vybrid and QorIQ family of SoCs. +config VIDEO_FSL_DCU_MAX_FB_SIZE_MB + int "Freescale DCU framebuffer size" + depends on VIDEO_FSL_DCU_FB + default 4194304 + help + Set maximum framebuffer size to be used for Freescale Display + Controller Unit (DCU4). + config VIDEO_ROCKCHIP bool "Enable Rockchip video support" depends on DM_VIDEO diff --git a/drivers/video/fsl_dcu_fb.c b/drivers/video/fsl_dcu_fb.c index d4cd382776..7f03290b74 100644 --- a/drivers/video/fsl_dcu_fb.c +++ b/drivers/video/fsl_dcu_fb.c @@ -8,6 +8,7 @@ #include #include +#include #include #include #include @@ -79,6 +80,8 @@ #define BPP_24_RGB888 5 #define BPP_32_ARGB8888 6 +DECLARE_GLOBAL_DATA_PTR; + /* * This setting is used for the TWR_LCD_RGB card */ @@ -254,11 +257,19 @@ int fsl_dcu_init(unsigned int xres, unsigned int yres, struct dcu_reg *regs = (struct dcu_reg *)CONFIG_SYS_DCU_ADDR; unsigned int div, mode; - /* Memory allocation for framebuffer */ info.screen_size = info.var.xres * info.var.yres * (info.var.bits_per_pixel / 8); - info.screen_base = (char *)memalign(ARCH_DMA_MINALIGN, - roundup(info.screen_size, ARCH_DMA_MINALIGN)); + + if (info.screen_size > CONFIG_VIDEO_FSL_DCU_MAX_FB_SIZE_MB) { + info.screen_size = 0; + return -ENOMEM; + } + + /* Reserve framebuffer at the end of memory */ + gd->fb_base = gd->bd->bi_dram[0].start + + gd->bd->bi_dram[0].size - info.screen_size; + info.screen_base = (char *)gd->fb_base; + memset(info.screen_base, 0, info.screen_size); reset_total_layers(); @@ -305,6 +316,11 @@ int fsl_dcu_init(unsigned int xres, unsigned int yres, return 0; } +ulong board_get_usable_ram_top(ulong total_size) +{ + return gd->ram_top - CONFIG_VIDEO_FSL_DCU_MAX_FB_SIZE_MB; +} + void *video_hw_init(void) { static GraphicDevice ctfb; @@ -363,3 +379,26 @@ void *video_hw_init(void) return &ctfb; } + +#if defined(CONFIG_OF_BOARD_SETUP) +int fsl_dcu_fixedfb_setup(void *blob) +{ + u64 start, size; + int ret; + + start = gd->bd->bi_dram[0].start; + size = gd->bd->bi_dram[0].size - info.screen_size; + + /* + * Align size on section size (1 MiB). + */ + size &= 0xfff00000; + ret = fdt_fixup_memory_banks(blob, &start, &size, 1); + if (ret) { + eprintf("Cannot setup fb: Error reserving memory\n"); + return ret; + } + + return 0; +} +#endif -- cgit From 32f26f56b3b918444ee2b3bf8f928bec506021b8 Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Tue, 11 Apr 2017 11:12:11 +0530 Subject: video: fsl_dcu_fb: Enable pixel clock after initialization When enabling the DCU and pixel clock, the test mode is activated since this is the reset configuration. The test mode immediately shows a red screen on a LCD. A moment later, the DCU gets initialized properly. This patch enables the pixel clock after initialization of the DCU control register. This avoids this initial flicker on LCD screens. While at it change the polarity of pixel clock to display samples data on the rising edge. Signed-off-by: Stefan Agner Signed-off-by: Sanchayan Maity Reviewed-by: Alison Wang --- drivers/video/fsl_dcu_fb.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) (limited to 'drivers/video') diff --git a/drivers/video/fsl_dcu_fb.c b/drivers/video/fsl_dcu_fb.c index 7f03290b74..c6ed3c40bc 100644 --- a/drivers/video/fsl_dcu_fb.c +++ b/drivers/video/fsl_dcu_fb.c @@ -41,7 +41,7 @@ #define DCU_VSYN_PARA_BP(x) ((x) << 22) #define DCU_VSYN_PARA_PW(x) ((x) << 11) #define DCU_VSYN_PARA_FP(x) (x) -#define DCU_SYN_POL_INV_PXCK_FALL (0 << 6) +#define DCU_SYN_POL_INV_PXCK_FALL (1 << 6) #define DCU_SYN_POL_NEG_REMAIN (0 << 5) #define DCU_SYN_POL_INV_VS_LOW (1 << 1) #define DCU_SYN_POL_INV_HS_LOW (1) @@ -191,8 +191,6 @@ static void reset_total_layers(void) dcu_write32(®s->ctrldescl[i][9], 0); dcu_write32(®s->ctrldescl[i][10], 0); } - - dcu_write32(®s->update_mode, DCU_UPDATE_MODE_READREG); } static int layer_ctrldesc_init(int index, u32 pixel_format) @@ -246,8 +244,6 @@ static int layer_ctrldesc_init(int index, u32 pixel_format) dcu_write32(®s->ctrldescl[index][7], DCU_CTRLDESCLN_8_FG_FCOLOR(0)); dcu_write32(®s->ctrldescl[index][8], DCU_CTRLDESCLN_9_BG_BCOLOR(0)); - dcu_write32(®s->update_mode, DCU_UPDATE_MODE_READREG); - return 0; } @@ -273,8 +269,6 @@ int fsl_dcu_init(unsigned int xres, unsigned int yres, memset(info.screen_base, 0, info.screen_size); reset_total_layers(); - div = dcu_set_pixel_clock(info.var.pixclock); - dcu_write32(®s->div_ratio, (div - 1)); dcu_write32(®s->disp_size, DCU_DISP_SIZE_DELTA_Y(info.var.yres) | @@ -313,6 +307,11 @@ int fsl_dcu_init(unsigned int xres, unsigned int yres, layer_ctrldesc_init(0, pixel_format); + div = dcu_set_pixel_clock(info.var.pixclock); + dcu_write32(®s->div_ratio, (div - 1)); + + dcu_write32(®s->update_mode, DCU_UPDATE_MODE_READREG); + return 0; } -- cgit From 7ce92a554a257d2f9ceee9ab855b878f01a5f88a Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Tue, 11 Apr 2017 11:12:12 +0530 Subject: video: fsl_dcu_fb: Fix DCU_MODE_BLEND_ITER setting DCU_LAYER_MAX_NUM is currently used for DCU_MODE_BLEND_ITER and it actually overflows the maximum value of BLEND_ITER for Vybrid and LS102XA. Fix this by using a default value of 2. Signed-off-by: Stefan Agner Signed-off-by: Sanchayan Maity --- drivers/video/fsl_dcu_fb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/video') diff --git a/drivers/video/fsl_dcu_fb.c b/drivers/video/fsl_dcu_fb.c index c6ed3c40bc..9fd9218c7b 100644 --- a/drivers/video/fsl_dcu_fb.c +++ b/drivers/video/fsl_dcu_fb.c @@ -294,7 +294,7 @@ int fsl_dcu_init(unsigned int xres, unsigned int yres, DCU_BGND_R(0) | DCU_BGND_G(0) | DCU_BGND_B(0)); dcu_write32(®s->mode, - DCU_MODE_BLEND_ITER(DCU_LAYER_MAX_NUM) | + DCU_MODE_BLEND_ITER(2) | DCU_MODE_RASTER_EN); dcu_write32(®s->threshold, -- cgit From 7a2d533eec571ae815455048e8ef4986725c9f87 Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Tue, 11 Apr 2017 11:12:13 +0530 Subject: video: fsl_dcu_fb: add additional modes for DCU Add common widescreen modes 800x480 and 1024x600. Signed-off-by: Stefan Agner Signed-off-by: Sanchayan Maity Reviewed-by: Alison Wang --- drivers/video/fsl_dcu_fb.c | 61 ++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 59 insertions(+), 2 deletions(-) (limited to 'drivers/video') diff --git a/drivers/video/fsl_dcu_fb.c b/drivers/video/fsl_dcu_fb.c index 9fd9218c7b..01e4a409b6 100644 --- a/drivers/video/fsl_dcu_fb.c +++ b/drivers/video/fsl_dcu_fb.c @@ -104,7 +104,7 @@ static struct fb_videomode fsl_dcu_mode_480_272 = { /* * This setting is used for Siliconimage SiI9022A HDMI */ -static struct fb_videomode fsl_dcu_mode_640_480 = { +static struct fb_videomode fsl_dcu_cea_mode_640_480 = { .name = "640x480-60", .refresh = 60, .xres = 640, @@ -120,6 +120,54 @@ static struct fb_videomode fsl_dcu_mode_640_480 = { .vmode = FB_VMODE_NONINTERLACED, }; +static struct fb_videomode fsl_dcu_mode_640_480 = { + .name = "640x480-60", + .refresh = 60, + .xres = 640, + .yres = 480, + .pixclock = 25175, + .left_margin = 40, + .right_margin = 24, + .upper_margin = 32, + .lower_margin = 11, + .hsync_len = 96, + .vsync_len = 2, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED, +}; + +static struct fb_videomode fsl_dcu_mode_800_480 = { + .name = "800x480-60", + .refresh = 60, + .xres = 800, + .yres = 480, + .pixclock = 33260, + .left_margin = 216, + .right_margin = 40, + .upper_margin = 35, + .lower_margin = 10, + .hsync_len = 128, + .vsync_len = 2, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED, +}; + +static struct fb_videomode fsl_dcu_mode_1024_600 = { + .name = "1024x600-60", + .refresh = 60, + .xres = 1024, + .yres = 600, + .pixclock = 48000, + .left_margin = 104, + .right_margin = 43, + .upper_margin = 24, + .lower_margin = 20, + .hsync_len = 5, + .vsync_len = 5, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED, +}; + /* * DCU register map */ @@ -342,7 +390,16 @@ void *video_hw_init(void) fsl_dcu_mode_db = &fsl_dcu_mode_480_272; break; case RESOLUTION(640, 480): - fsl_dcu_mode_db = &fsl_dcu_mode_640_480; + if (!strncmp(options, "monitor=hdmi", 12)) + fsl_dcu_mode_db = &fsl_dcu_cea_mode_640_480; + else + fsl_dcu_mode_db = &fsl_dcu_mode_640_480; + break; + case RESOLUTION(800, 480): + fsl_dcu_mode_db = &fsl_dcu_mode_800_480; + break; + case RESOLUTION(1024, 600): + fsl_dcu_mode_db = &fsl_dcu_mode_1024_600; break; default: printf("unsupported resolution %ux%u\n", -- cgit From 7927831e21a1ec2f44e0e0eb142ca24be807d202 Mon Sep 17 00:00:00 2001 From: Songjun Wu Date: Tue, 11 Apr 2017 16:33:30 +0800 Subject: at91: video: Support driver-model for the HLCD driver Add driver-model support to this driver. Signed-off-by: Songjun Wu --- drivers/video/Kconfig | 6 + drivers/video/atmel_hlcdfb.c | 482 ++++++++++++++++++++++++++++++++++++------- 2 files changed, 417 insertions(+), 71 deletions(-) (limited to 'drivers/video') diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index d1b017cfad..19e97452bd 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -371,6 +371,12 @@ config DISPLAY The devices provide a simple interface to start up the display, read display information and enable it. +config ATMEL_HLCD + bool "Enable ATMEL video support using HLCDC" + depends on DM_VIDEO + help + HLCDC supports video output to an attached LCD panel. + config VIDEO_BROADWELL_IGD bool "Enable Intel Broadwell integrated graphics device" depends on X86 diff --git a/drivers/video/atmel_hlcdfb.c b/drivers/video/atmel_hlcdfb.c index 960b474b76..59b9c45616 100644 --- a/drivers/video/atmel_hlcdfb.c +++ b/drivers/video/atmel_hlcdfb.c @@ -10,13 +10,22 @@ #include #include #include +#include +#include +#include #include +#include +#include #include #if defined(CONFIG_LCD_LOGO) #include #endif +DECLARE_GLOBAL_DATA_PTR; + +#ifndef CONFIG_DM_VIDEO + /* configurable parameters */ #define ATMEL_LCDC_CVAL_DEFAULT 0xc8 #define ATMEL_LCDC_DMA_BURST_LEN 8 @@ -26,19 +35,16 @@ #define ATMEL_LCDC_FIFO_SIZE 512 -#define lcdc_readl(reg) __raw_readl((reg)) -#define lcdc_writel(reg, val) __raw_writel((val), (reg)) - /* * the CLUT register map as following * RCLUT(24 ~ 16), GCLUT(15 ~ 8), BCLUT(7 ~ 0) */ void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue) { - lcdc_writel(((red << LCDC_BASECLUT_RCLUT_Pos) & LCDC_BASECLUT_RCLUT_Msk) - | ((green << LCDC_BASECLUT_GCLUT_Pos) & LCDC_BASECLUT_GCLUT_Msk) - | ((blue << LCDC_BASECLUT_BCLUT_Pos) & LCDC_BASECLUT_BCLUT_Msk), - panel_info.mmio + ATMEL_LCDC_LUT(regno)); + writel(panel_info.mmio + ATMEL_LCDC_LUT(regno), + ((red << LCDC_BASECLUT_RCLUT_Pos) & LCDC_BASECLUT_RCLUT_Msk) + | ((green << LCDC_BASECLUT_GCLUT_Pos) & LCDC_BASECLUT_GCLUT_Msk) + | ((blue << LCDC_BASECLUT_BCLUT_Pos) & LCDC_BASECLUT_BCLUT_Msk)); } ushort *configuration_get_cmap(void) @@ -55,6 +61,7 @@ void lcd_ctrl_init(void *lcdbase) unsigned long value; struct lcd_dma_desc *desc; struct atmel_hlcd_regs *regs; + int ret; if (!has_lcdc()) return; /* No lcdc */ @@ -62,21 +69,29 @@ void lcd_ctrl_init(void *lcdbase) regs = (struct atmel_hlcd_regs *)panel_info.mmio; /* Disable DISP signal */ - lcdc_writel(®s->lcdc_lcddis, LCDC_LCDDIS_DISPDIS); - while ((lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_DISPSTS)) - udelay(1); + writel(LCDC_LCDDIS_DISPDIS, ®s->lcdc_lcddis); + ret = wait_for_bit(__func__, ®s->lcdc_lcdsr, LCDC_LCDSR_DISPSTS, + false, 1000, false); + if (ret) + printf("%s: %d: Timeout!\n", __func__, __LINE__); /* Disable synchronization */ - lcdc_writel(®s->lcdc_lcddis, LCDC_LCDDIS_SYNCDIS); - while ((lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_LCDSTS)) - udelay(1); + writel(LCDC_LCDDIS_SYNCDIS, ®s->lcdc_lcddis); + ret = wait_for_bit(__func__, ®s->lcdc_lcdsr, LCDC_LCDSR_LCDSTS, + false, 1000, false); + if (ret) + printf("%s: %d: Timeout!\n", __func__, __LINE__); /* Disable pixel clock */ - lcdc_writel(®s->lcdc_lcddis, LCDC_LCDDIS_CLKDIS); - while ((lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_CLKSTS)) - udelay(1); + writel(LCDC_LCDDIS_CLKDIS, ®s->lcdc_lcddis); + ret = wait_for_bit(__func__, ®s->lcdc_lcdsr, LCDC_LCDSR_CLKSTS, + false, 1000, false); + if (ret) + printf("%s: %d: Timeout!\n", __func__, __LINE__); /* Disable PWM */ - lcdc_writel(®s->lcdc_lcddis, LCDC_LCDDIS_PWMDIS); - while ((lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_PWMSTS)) - udelay(1); + writel(LCDC_LCDDIS_PWMDIS, ®s->lcdc_lcddis); + ret = wait_for_bit(__func__, ®s->lcdc_lcdsr, LCDC_LCDSR_PWMSTS, + false, 1000, false); + if (ret) + printf("%s: %d: Timeout!\n", __func__, __LINE__); /* Set pixel clock */ value = get_lcdc_clk_rate(0) / panel_info.vl_clk; @@ -85,23 +100,23 @@ void lcd_ctrl_init(void *lcdbase) if (value < 1) { /* Using system clock as pixel clock */ - lcdc_writel(®s->lcdc_lcdcfg0, - LCDC_LCDCFG0_CLKDIV(0) - | LCDC_LCDCFG0_CGDISHCR - | LCDC_LCDCFG0_CGDISHEO - | LCDC_LCDCFG0_CGDISOVR1 - | LCDC_LCDCFG0_CGDISBASE - | panel_info.vl_clk_pol - | LCDC_LCDCFG0_CLKSEL); + writel(LCDC_LCDCFG0_CLKDIV(0) + | LCDC_LCDCFG0_CGDISHCR + | LCDC_LCDCFG0_CGDISHEO + | LCDC_LCDCFG0_CGDISOVR1 + | LCDC_LCDCFG0_CGDISBASE + | panel_info.vl_clk_pol + | LCDC_LCDCFG0_CLKSEL, + ®s->lcdc_lcdcfg0); } else { - lcdc_writel(®s->lcdc_lcdcfg0, - LCDC_LCDCFG0_CLKDIV(value - 2) - | LCDC_LCDCFG0_CGDISHCR - | LCDC_LCDCFG0_CGDISHEO - | LCDC_LCDCFG0_CGDISOVR1 - | LCDC_LCDCFG0_CGDISBASE - | panel_info.vl_clk_pol); + writel(LCDC_LCDCFG0_CLKDIV(value - 2) + | LCDC_LCDCFG0_CGDISHCR + | LCDC_LCDCFG0_CGDISHEO + | LCDC_LCDCFG0_CGDISOVR1 + | LCDC_LCDCFG0_CGDISBASE + | panel_info.vl_clk_pol, + ®s->lcdc_lcdcfg0); } /* Initialize control register 5 */ @@ -134,50 +149,50 @@ void lcd_ctrl_init(void *lcdbase) value |= LCDC_LCDCFG5_GUARDTIME(ATMEL_LCDC_GUARD_TIME); value |= (LCDC_LCDCFG5_DISPDLY | LCDC_LCDCFG5_VSPDLYS); - lcdc_writel(®s->lcdc_lcdcfg5, value); + writel(value, ®s->lcdc_lcdcfg5); /* Vertical & Horizontal Timing */ value = LCDC_LCDCFG1_VSPW(panel_info.vl_vsync_len - 1); value |= LCDC_LCDCFG1_HSPW(panel_info.vl_hsync_len - 1); - lcdc_writel(®s->lcdc_lcdcfg1, value); + writel(value, ®s->lcdc_lcdcfg1); value = LCDC_LCDCFG2_VBPW(panel_info.vl_upper_margin); value |= LCDC_LCDCFG2_VFPW(panel_info.vl_lower_margin - 1); - lcdc_writel(®s->lcdc_lcdcfg2, value); + writel(value, ®s->lcdc_lcdcfg2); value = LCDC_LCDCFG3_HBPW(panel_info.vl_left_margin - 1); value |= LCDC_LCDCFG3_HFPW(panel_info.vl_right_margin - 1); - lcdc_writel(®s->lcdc_lcdcfg3, value); + writel(value, ®s->lcdc_lcdcfg3); /* Display size */ value = LCDC_LCDCFG4_RPF(panel_info.vl_row - 1); value |= LCDC_LCDCFG4_PPL(panel_info.vl_col - 1); - lcdc_writel(®s->lcdc_lcdcfg4, value); + writel(value, ®s->lcdc_lcdcfg4); - lcdc_writel(®s->lcdc_basecfg0, - LCDC_BASECFG0_BLEN_AHB_INCR4 | LCDC_BASECFG0_DLBO); + writel(LCDC_BASECFG0_BLEN_AHB_INCR4 | LCDC_BASECFG0_DLBO, + ®s->lcdc_basecfg0); switch (NBITS(panel_info.vl_bpix)) { case 16: - lcdc_writel(®s->lcdc_basecfg1, - LCDC_BASECFG1_RGBMODE_16BPP_RGB_565); + writel(LCDC_BASECFG1_RGBMODE_16BPP_RGB_565, + ®s->lcdc_basecfg1); break; case 32: - lcdc_writel(®s->lcdc_basecfg1, - LCDC_BASECFG1_RGBMODE_24BPP_RGB_888); + writel(LCDC_BASECFG1_RGBMODE_24BPP_RGB_888, + ®s->lcdc_basecfg1); break; default: BUG(); break; } - lcdc_writel(®s->lcdc_basecfg2, LCDC_BASECFG2_XSTRIDE(0)); - lcdc_writel(®s->lcdc_basecfg3, 0); - lcdc_writel(®s->lcdc_basecfg4, LCDC_BASECFG4_DMA); + writel(LCDC_BASECFG2_XSTRIDE(0), ®s->lcdc_basecfg2); + writel(0, ®s->lcdc_basecfg3); + writel(LCDC_BASECFG4_DMA, ®s->lcdc_basecfg4); /* Disable all interrupts */ - lcdc_writel(®s->lcdc_lcdidr, ~0UL); - lcdc_writel(®s->lcdc_baseidr, ~0UL); + writel(~0UL, ®s->lcdc_lcdidr); + writel(~0UL, ®s->lcdc_baseidr); /* Setup the DMA descriptor, this descriptor will loop to itself */ desc = (struct lcd_dma_desc *)(lcdbase - 16); @@ -191,30 +206,355 @@ void lcd_ctrl_init(void *lcdbase) /* Flush the DMA descriptor if we enabled dcache */ flush_dcache_range((u32)desc, (u32)desc + sizeof(*desc)); - lcdc_writel(®s->lcdc_baseaddr, desc->address); - lcdc_writel(®s->lcdc_basectrl, desc->control); - lcdc_writel(®s->lcdc_basenext, desc->next); - lcdc_writel(®s->lcdc_basecher, LCDC_BASECHER_CHEN | - LCDC_BASECHER_UPDATEEN); + writel(desc->address, ®s->lcdc_baseaddr); + writel(desc->control, ®s->lcdc_basectrl); + writel(desc->next, ®s->lcdc_basenext); + writel(LCDC_BASECHER_CHEN | LCDC_BASECHER_UPDATEEN, + ®s->lcdc_basecher); /* Enable LCD */ - value = lcdc_readl(®s->lcdc_lcden); - lcdc_writel(®s->lcdc_lcden, value | LCDC_LCDEN_CLKEN); - while (!(lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_CLKSTS)) - udelay(1); - value = lcdc_readl(®s->lcdc_lcden); - lcdc_writel(®s->lcdc_lcden, value | LCDC_LCDEN_SYNCEN); - while (!(lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_LCDSTS)) - udelay(1); - value = lcdc_readl(®s->lcdc_lcden); - lcdc_writel(®s->lcdc_lcden, value | LCDC_LCDEN_DISPEN); - while (!(lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_DISPSTS)) - udelay(1); - value = lcdc_readl(®s->lcdc_lcden); - lcdc_writel(®s->lcdc_lcden, value | LCDC_LCDEN_PWMEN); - while (!(lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_PWMSTS)) - udelay(1); + value = readl(®s->lcdc_lcden); + writel(value | LCDC_LCDEN_CLKEN, ®s->lcdc_lcden); + ret = wait_for_bit(__func__, ®s->lcdc_lcdsr, LCDC_LCDSR_CLKSTS, + true, 1000, false); + if (ret) + printf("%s: %d: Timeout!\n", __func__, __LINE__); + value = readl(®s->lcdc_lcden); + writel(value | LCDC_LCDEN_SYNCEN, ®s->lcdc_lcden); + ret = wait_for_bit(__func__, ®s->lcdc_lcdsr, LCDC_LCDSR_LCDSTS, + true, 1000, false); + if (ret) + printf("%s: %d: Timeout!\n", __func__, __LINE__); + value = readl(®s->lcdc_lcden); + writel(value | LCDC_LCDEN_DISPEN, ®s->lcdc_lcden); + ret = wait_for_bit(__func__, ®s->lcdc_lcdsr, LCDC_LCDSR_DISPSTS, + true, 1000, false); + if (ret) + printf("%s: %d: Timeout!\n", __func__, __LINE__); + value = readl(®s->lcdc_lcden); + writel(value | LCDC_LCDEN_PWMEN, ®s->lcdc_lcden); + ret = wait_for_bit(__func__, ®s->lcdc_lcdsr, LCDC_LCDSR_PWMSTS, + true, 1000, false); + if (ret) + printf("%s: %d: Timeout!\n", __func__, __LINE__); /* Enable flushing if we enabled dcache */ lcd_set_flush_dcache(1); } + +#else + +enum { + LCD_MAX_WIDTH = 1024, + LCD_MAX_HEIGHT = 768, + LCD_MAX_LOG2_BPP = VIDEO_BPP16, +}; + +struct atmel_hlcdc_priv { + struct atmel_hlcd_regs *regs; + struct display_timing timing; + unsigned int vl_bpix; + unsigned int output_mode; + unsigned int guard_time; + ulong clk_rate; +}; + +static int at91_hlcdc_enable_clk(struct udevice *dev) +{ + struct atmel_hlcdc_priv *priv = dev_get_priv(dev); + struct clk clk; + ulong clk_rate; + int ret; + + ret = clk_get_by_index(dev, 0, &clk); + if (ret) + return -EINVAL; + + ret = clk_enable(&clk); + if (ret) + return ret; + + clk_rate = clk_get_rate(&clk); + if (!clk_rate) { + clk_disable(&clk); + return -ENODEV; + } + + priv->clk_rate = clk_rate; + + clk_free(&clk); + + return 0; +} + +static void atmel_hlcdc_init(struct udevice *dev) +{ + struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev); + struct atmel_hlcdc_priv *priv = dev_get_priv(dev); + struct atmel_hlcd_regs *regs = priv->regs; + struct display_timing *timing = &priv->timing; + struct lcd_dma_desc *desc; + unsigned long value, vl_clk_pol; + int ret; + + /* Disable DISP signal */ + writel(LCDC_LCDDIS_DISPDIS, ®s->lcdc_lcddis); + ret = wait_for_bit(__func__, ®s->lcdc_lcdsr, LCDC_LCDSR_DISPSTS, + false, 1000, false); + if (ret) + printf("%s: %d: Timeout!\n", __func__, __LINE__); + /* Disable synchronization */ + writel(LCDC_LCDDIS_SYNCDIS, ®s->lcdc_lcddis); + ret = wait_for_bit(__func__, ®s->lcdc_lcdsr, LCDC_LCDSR_LCDSTS, + false, 1000, false); + if (ret) + printf("%s: %d: Timeout!\n", __func__, __LINE__); + /* Disable pixel clock */ + writel(LCDC_LCDDIS_CLKDIS, ®s->lcdc_lcddis); + ret = wait_for_bit(__func__, ®s->lcdc_lcdsr, LCDC_LCDSR_CLKSTS, + false, 1000, false); + if (ret) + printf("%s: %d: Timeout!\n", __func__, __LINE__); + /* Disable PWM */ + writel(LCDC_LCDDIS_PWMDIS, ®s->lcdc_lcddis); + ret = wait_for_bit(__func__, ®s->lcdc_lcdsr, LCDC_LCDSR_PWMSTS, + false, 1000, false); + if (ret) + printf("%s: %d: Timeout!\n", __func__, __LINE__); + + /* Set pixel clock */ + value = priv->clk_rate / timing->pixelclock.typ; + if (priv->clk_rate % timing->pixelclock.typ) + value++; + + vl_clk_pol = 0; + if (timing->flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE) + vl_clk_pol = LCDC_LCDCFG0_CLKPOL; + + if (value < 1) { + /* Using system clock as pixel clock */ + writel(LCDC_LCDCFG0_CLKDIV(0) + | LCDC_LCDCFG0_CGDISHCR + | LCDC_LCDCFG0_CGDISHEO + | LCDC_LCDCFG0_CGDISOVR1 + | LCDC_LCDCFG0_CGDISBASE + | vl_clk_pol + | LCDC_LCDCFG0_CLKSEL, + ®s->lcdc_lcdcfg0); + + } else { + writel(LCDC_LCDCFG0_CLKDIV(value - 2) + | LCDC_LCDCFG0_CGDISHCR + | LCDC_LCDCFG0_CGDISHEO + | LCDC_LCDCFG0_CGDISOVR1 + | LCDC_LCDCFG0_CGDISBASE + | vl_clk_pol, + ®s->lcdc_lcdcfg0); + } + + /* Initialize control register 5 */ + value = 0; + + if (!(timing->flags & DISPLAY_FLAGS_HSYNC_HIGH)) + value |= LCDC_LCDCFG5_HSPOL; + if (!(timing->flags & DISPLAY_FLAGS_VSYNC_HIGH)) + value |= LCDC_LCDCFG5_VSPOL; + + switch (priv->output_mode) { + case 12: + value |= LCDC_LCDCFG5_MODE_OUTPUT_12BPP; + break; + case 16: + value |= LCDC_LCDCFG5_MODE_OUTPUT_16BPP; + break; + case 18: + value |= LCDC_LCDCFG5_MODE_OUTPUT_18BPP; + break; + case 24: + value |= LCDC_LCDCFG5_MODE_OUTPUT_24BPP; + break; + default: + BUG(); + break; + } + + value |= LCDC_LCDCFG5_GUARDTIME(priv->guard_time); + value |= (LCDC_LCDCFG5_DISPDLY | LCDC_LCDCFG5_VSPDLYS); + writel(value, ®s->lcdc_lcdcfg5); + + /* Vertical & Horizontal Timing */ + value = LCDC_LCDCFG1_VSPW(timing->vsync_len.typ - 1); + value |= LCDC_LCDCFG1_HSPW(timing->hsync_len.typ - 1); + writel(value, ®s->lcdc_lcdcfg1); + + value = LCDC_LCDCFG2_VBPW(timing->vback_porch.typ); + value |= LCDC_LCDCFG2_VFPW(timing->vfront_porch.typ - 1); + writel(value, ®s->lcdc_lcdcfg2); + + value = LCDC_LCDCFG3_HBPW(timing->hback_porch.typ - 1); + value |= LCDC_LCDCFG3_HFPW(timing->hfront_porch.typ - 1); + writel(value, ®s->lcdc_lcdcfg3); + + /* Display size */ + value = LCDC_LCDCFG4_RPF(timing->vactive.typ - 1); + value |= LCDC_LCDCFG4_PPL(timing->hactive.typ - 1); + writel(value, ®s->lcdc_lcdcfg4); + + writel(LCDC_BASECFG0_BLEN_AHB_INCR4 | LCDC_BASECFG0_DLBO, + ®s->lcdc_basecfg0); + + switch (VNBITS(priv->vl_bpix)) { + case 16: + writel(LCDC_BASECFG1_RGBMODE_16BPP_RGB_565, + ®s->lcdc_basecfg1); + break; + case 32: + writel(LCDC_BASECFG1_RGBMODE_24BPP_RGB_888, + ®s->lcdc_basecfg1); + break; + default: + BUG(); + break; + } + + writel(LCDC_BASECFG2_XSTRIDE(0), ®s->lcdc_basecfg2); + writel(0, ®s->lcdc_basecfg3); + writel(LCDC_BASECFG4_DMA, ®s->lcdc_basecfg4); + + /* Disable all interrupts */ + writel(~0UL, ®s->lcdc_lcdidr); + writel(~0UL, ®s->lcdc_baseidr); + + /* Setup the DMA descriptor, this descriptor will loop to itself */ + desc = (struct lcd_dma_desc *)(uc_plat->base - 16); + + desc->address = (u32)uc_plat->base; + + /* Disable DMA transfer interrupt & descriptor loaded interrupt. */ + desc->control = LCDC_BASECTRL_ADDIEN | LCDC_BASECTRL_DSCRIEN + | LCDC_BASECTRL_DMAIEN | LCDC_BASECTRL_DFETCH; + desc->next = (u32)desc; + + /* Flush the DMA descriptor if we enabled dcache */ + flush_dcache_range((u32)desc, (u32)desc + sizeof(*desc)); + + writel(desc->address, ®s->lcdc_baseaddr); + writel(desc->control, ®s->lcdc_basectrl); + writel(desc->next, ®s->lcdc_basenext); + writel(LCDC_BASECHER_CHEN | LCDC_BASECHER_UPDATEEN, + ®s->lcdc_basecher); + + /* Enable LCD */ + value = readl(®s->lcdc_lcden); + writel(value | LCDC_LCDEN_CLKEN, ®s->lcdc_lcden); + ret = wait_for_bit(__func__, ®s->lcdc_lcdsr, LCDC_LCDSR_CLKSTS, + true, 1000, false); + if (ret) + printf("%s: %d: Timeout!\n", __func__, __LINE__); + value = readl(®s->lcdc_lcden); + writel(value | LCDC_LCDEN_SYNCEN, ®s->lcdc_lcden); + ret = wait_for_bit(__func__, ®s->lcdc_lcdsr, LCDC_LCDSR_LCDSTS, + true, 1000, false); + if (ret) + printf("%s: %d: Timeout!\n", __func__, __LINE__); + value = readl(®s->lcdc_lcden); + writel(value | LCDC_LCDEN_DISPEN, ®s->lcdc_lcden); + ret = wait_for_bit(__func__, ®s->lcdc_lcdsr, LCDC_LCDSR_DISPSTS, + true, 1000, false); + if (ret) + printf("%s: %d: Timeout!\n", __func__, __LINE__); + value = readl(®s->lcdc_lcden); + writel(value | LCDC_LCDEN_PWMEN, ®s->lcdc_lcden); + ret = wait_for_bit(__func__, ®s->lcdc_lcdsr, LCDC_LCDSR_PWMSTS, + true, 1000, false); + if (ret) + printf("%s: %d: Timeout!\n", __func__, __LINE__); +} + +static int atmel_hlcdc_probe(struct udevice *dev) +{ + struct video_priv *uc_priv = dev_get_uclass_priv(dev); + struct atmel_hlcdc_priv *priv = dev_get_priv(dev); + int ret; + + ret = at91_hlcdc_enable_clk(dev); + if (ret) + return ret; + + atmel_hlcdc_init(dev); + + uc_priv->xsize = priv->timing.hactive.typ; + uc_priv->ysize = priv->timing.vactive.typ; + uc_priv->bpix = priv->vl_bpix; + + /* Enable flushing if we enabled dcache */ + video_set_flush_dcache(dev, true); + + return 0; +} + +static int atmel_hlcdc_ofdata_to_platdata(struct udevice *dev) +{ + struct atmel_hlcdc_priv *priv = dev_get_priv(dev); + const void *blob = gd->fdt_blob; + int node = dev->of_offset; + + priv->regs = (struct atmel_hlcd_regs *)dev_get_addr(dev); + if (!priv->regs) { + debug("%s: No display controller address\n", __func__); + return -EINVAL; + } + + if (fdtdec_decode_display_timing(blob, dev->of_offset, + 0, &priv->timing)) { + debug("%s: Failed to decode display timing\n", __func__); + return -EINVAL; + } + + if (priv->timing.hactive.typ > LCD_MAX_WIDTH) + priv->timing.hactive.typ = LCD_MAX_WIDTH; + + if (priv->timing.vactive.typ > LCD_MAX_HEIGHT) + priv->timing.vactive.typ = LCD_MAX_HEIGHT; + + priv->vl_bpix = fdtdec_get_int(blob, node, "atmel,vl-bpix", 0); + if (!priv->vl_bpix) { + debug("%s: Failed to get bits per pixel\n", __func__); + return -EINVAL; + } + + priv->output_mode = fdtdec_get_int(blob, node, "atmel,output-mode", 24); + priv->guard_time = fdtdec_get_int(blob, node, "atmel,guard-time", 1); + + return 0; +} + +static int atmel_hlcdc_bind(struct udevice *dev) +{ + struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev); + + uc_plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT * + (1 << LCD_MAX_LOG2_BPP) / 8; + + debug("%s: Frame buffer size %x\n", __func__, uc_plat->size); + + return 0; +} + +static const struct udevice_id atmel_hlcdc_ids[] = { + { .compatible = "atmel,sama5d2-hlcdc" }, + { .compatible = "atmel,at91sam9x5-hlcdc" }, + { } +}; + +U_BOOT_DRIVER(atmel_hlcdfb) = { + .name = "atmel_hlcdfb", + .id = UCLASS_VIDEO, + .of_match = atmel_hlcdc_ids, + .bind = atmel_hlcdc_bind, + .probe = atmel_hlcdc_probe, + .ofdata_to_platdata = atmel_hlcdc_ofdata_to_platdata, + .priv_auto_alloc_size = sizeof(struct atmel_hlcdc_priv), +}; + +#endif -- cgit From 7682736c891d2b6f0cce167f4ecd55d2df0f562f Mon Sep 17 00:00:00 2001 From: "eric.gao@rock-chips.com" Date: Mon, 10 Apr 2017 10:02:20 +0800 Subject: video: Fix crash when scroll screen After enabling log printing to lcd, when the screen starts scrolling, system crashes. Log is shown as bellow: "Synchronous Abort" handler, esr 0x96000045 "Synchronous Abort" handler, esr 0x96000045 Checking the source code, we found that the variable "pixels" gets a wrong value: int pixels = VIDEO_FONT_HEIGHT * vid_priv->line_length; "pixels" here means the value of pixels for a character, rather than the bytes for a character. So the variable "pixels" is 4 times bigger than it's exact value, which will cause the memory overflow when the cpu runs the following code: for (i = 0; i < pixels; i++) *dst++ = clr; <<---- Signed-off-by: Eric Gao --- drivers/video/console_normal.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/video') diff --git a/drivers/video/console_normal.c b/drivers/video/console_normal.c index 89a55dd11d..b627d48df6 100644 --- a/drivers/video/console_normal.c +++ b/drivers/video/console_normal.c @@ -18,7 +18,7 @@ static int console_normal_set_row(struct udevice *dev, uint row, int clr) { struct video_priv *vid_priv = dev_get_uclass_priv(dev->parent); void *line; - int pixels = VIDEO_FONT_HEIGHT * vid_priv->line_length; + int pixels = VIDEO_FONT_HEIGHT * vid_priv->xsize; int i; line = vid_priv->fb + row * VIDEO_FONT_HEIGHT * vid_priv->line_length; -- cgit