From 6e1385d5f8d137e741dfef02465d7dc328040ad7 Mon Sep 17 00:00:00 2001 From: Mingkai Hu Date: Fri, 11 Sep 2009 10:53:08 +0800 Subject: NAND boot: change NAND loader's relocate SP to CONFIG param So that we can set the NAND loader's relocate stack pointer to the value other than the relocate address + 0x10000. Signed-off-by: Mingkai Hu Acked-by: Kim Phillips Acked-by: Scott Wood Signed-off-by: Kumar Gala --- include/configs/SIMPC8313.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include/configs/SIMPC8313.h') diff --git a/include/configs/SIMPC8313.h b/include/configs/SIMPC8313.h index b847ce85db..866ff179e6 100644 --- a/include/configs/SIMPC8313.h +++ b/include/configs/SIMPC8313.h @@ -136,6 +136,7 @@ #define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000 #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000 +#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000) #define CONFIG_SYS_NAND_BR_PRELIM ( CONFIG_SYS_NAND_BASE \ | (2< Date: Fri, 25 Sep 2009 18:19:44 -0500 Subject: mpc83xx: retain POR values of non-configured ACR, SPCR, SCCR, and LCRR bitfields some LCRR bits are not documented throughout the 83xx family RMs. New board porters copying similar board configurations might omit setting e.g., DBYP since it was not documented in their SoC's RM. Prevent them bricking their board by retaining power on reset values in bit fields that the board porter doesn't explicitly configure via CONFIG_SYS__ assignments in the board config file. also move LCRR assignment to cpu_init_r[am] to help ensure no transactions are being executed via the local bus while CLKDIV is being modified. also start to use i/o accessors. Signed-off-by: Kim Phillips --- include/configs/SIMPC8313.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'include/configs/SIMPC8313.h') diff --git a/include/configs/SIMPC8313.h b/include/configs/SIMPC8313.h index 866ff179e6..f68d834170 100644 --- a/include/configs/SIMPC8313.h +++ b/include/configs/SIMPC8313.h @@ -111,7 +111,9 @@ /* * Local Bus LCRR and LBCR regs */ -#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_EADC_1 | LCRR_CLKDIV_2) +#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP +#define CONFIG_SYS_LCRR_EADC LCRR_EADC_1 +#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 #define CONFIG_SYS_LBC_LBCR (0x00040000 /* TODO */ \ | (0xFF << LBCR_BMT_SHIFT) \ | 0xF ) /* 0x0004ff0f */ -- cgit