From 85f737376d5ff3d5f0d45a8b657686326d175307 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 15 Jun 2007 07:39:43 +0200 Subject: [ppc4xx] Extend 44x GPIO setup with default output state The board config array CFG_440_GPIO_TABLE for the ppc440 GPIO setup is extended with the default GPIO output state (level). Signed-off-by: Stefan Roese --- include/configs/pcs440ep.h | 130 ++++++++++++++++++++++----------------------- 1 file changed, 65 insertions(+), 65 deletions(-) (limited to 'include/configs/pcs440ep.h') diff --git a/include/configs/pcs440ep.h b/include/configs/pcs440ep.h index 23bdfc8dfb..9e41773f57 100644 --- a/include/configs/pcs440ep.h +++ b/include/configs/pcs440ep.h @@ -315,76 +315,76 @@ /*----------------------------------------------------------------------- * PPC440 GPIO Configuration */ -#define CFG_440_GPIO_TABLE { /* GPIO Alternate1 Alternate2 Alternate3 */ \ +#define CFG_440_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \ { \ /* GPIO Core 0 */ \ -{ GPIO0_BASE, GPIO_OUT, GPIO_SEL }, /* GPIO0 EBC_ADDR(7) DMA_REQ(2) */ \ -{ GPIO0_BASE, GPIO_OUT, GPIO_SEL }, /* GPIO1 EBC_ADDR(6) DMA_ACK(2) */ \ -{ GPIO0_BASE, GPIO_OUT, GPIO_SEL }, /* GPIO2 EBC_ADDR(5) DMA_EOT/TC(2) */ \ -{ GPIO0_BASE, GPIO_OUT, GPIO_SEL }, /* GPIO3 EBC_ADDR(4) DMA_REQ(3) */ \ -{ GPIO0_BASE, GPIO_OUT, GPIO_SEL }, /* GPIO4 EBC_ADDR(3) DMA_ACK(3) */ \ -{ GPIO0_BASE, GPIO_OUT, GPIO_SEL }, /* GPIO5 EBC_ADDR(2) DMA_EOT/TC(3) */ \ -{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO6 EBC_CS_N(1) */ \ -{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO7 EBC_CS_N(2) */ \ -{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO8 EBC_CS_N(3) */ \ -{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO9 EBC_CS_N(4) */ \ -{ GPIO0_BASE, GPIO_OUT, GPIO_SEL }, /* GPIO10 EBC_CS_N(5) */ \ -{ GPIO0_BASE, GPIO_OUT, GPIO_SEL }, /* GPIO11 EBC_BUS_ERR */ \ -{ GPIO0_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO12 ZII_p0Rxd(0) */ \ -{ GPIO0_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO13 ZII_p0Rxd(1) */ \ -{ GPIO0_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO14 ZII_p0Rxd(2) */ \ -{ GPIO0_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO15 ZII_p0Rxd(3) */ \ -{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO16 ZII_p0Txd(0) */ \ -{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO17 ZII_p0Txd(1) */ \ -{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO18 ZII_p0Txd(2) */ \ -{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO19 ZII_p0Txd(3) */ \ -{ GPIO0_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO20 ZII_p0Rx_er */ \ -{ GPIO0_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO21 ZII_p0Rx_dv */ \ -{ GPIO0_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO22 ZII_p0RxCrs */ \ -{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO23 ZII_p0Tx_er */ \ -{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO24 ZII_p0Tx_en */ \ -{ GPIO0_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO25 ZII_p0Col */ \ -{ GPIO0_BASE, GPIO_IN, GPIO_SEL }, /* GPIO26 USB2D_RXVALID */ \ -{ GPIO0_BASE, GPIO_IN, GPIO_SEL }, /* GPIO27 EXT_EBC_REQ USB2D_RXERROR */ \ -{ GPIO0_BASE, GPIO_IN, GPIO_SEL }, /* GPIO28 USB2D_TXVALID */ \ -{ GPIO0_BASE, GPIO_IN, GPIO_SEL }, /* GPIO29 EBC_EXT_HDLA USB2D_PAD_SUSPNDM */ \ -{ GPIO0_BASE, GPIO_IN, GPIO_SEL }, /* GPIO30 EBC_EXT_ACK USB2D_XCVRSELECT*/ \ -{ GPIO0_BASE, GPIO_IN, GPIO_SEL }, /* GPIO31 EBC_EXR_BUSREQ USB2D_TERMSELECT*/ \ +{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO0 EBC_ADDR(7) DMA_REQ(2) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO1 EBC_ADDR(6) DMA_ACK(2) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO2 EBC_ADDR(5) DMA_EOT/TC(2) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO3 EBC_ADDR(4) DMA_REQ(3) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO4 EBC_ADDR(3) DMA_ACK(3) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO5 EBC_ADDR(2) DMA_EOT/TC(3) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO6 EBC_CS_N(1) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO7 EBC_CS_N(2) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO8 EBC_CS_N(3) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO9 EBC_CS_N(4) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO10 EBC_CS_N(5) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO11 EBC_BUS_ERR */ \ +{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO12 ZII_p0Rxd(0) */ \ +{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO13 ZII_p0Rxd(1) */ \ +{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO14 ZII_p0Rxd(2) */ \ +{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO15 ZII_p0Rxd(3) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO16 ZII_p0Txd(0) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO17 ZII_p0Txd(1) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO18 ZII_p0Txd(2) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO19 ZII_p0Txd(3) */ \ +{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO20 ZII_p0Rx_er */ \ +{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO21 ZII_p0Rx_dv */ \ +{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO22 ZII_p0RxCrs */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO23 ZII_p0Tx_er */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO24 ZII_p0Tx_en */ \ +{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO25 ZII_p0Col */ \ +{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO26 USB2D_RXVALID */ \ +{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO27 EXT_EBC_REQ USB2D_RXERROR */ \ +{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO28 USB2D_TXVALID */ \ +{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO29 EBC_EXT_HDLA USB2D_PAD_SUSPNDM */ \ +{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO30 EBC_EXT_ACK USB2D_XCVRSELECT*/ \ +{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO31 EBC_EXR_BUSREQ USB2D_TERMSELECT*/ \ }, \ { \ /* GPIO Core 1 */ \ -{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO32 USB2D_OPMODE0 */ \ -{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO33 USB2D_OPMODE1 */ \ -{ GPIO1_BASE, GPIO_OUT, GPIO_ALT3 }, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \ -{ GPIO1_BASE, GPIO_IN, GPIO_ALT3 }, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \ -{ GPIO1_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO36 UART0_8PIN_CTS_N UART3_SIN*/ \ -{ GPIO1_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO37 UART0_RTS_N */ \ -{ GPIO1_BASE, GPIO_OUT, GPIO_ALT2 }, /* GPIO38 UART0_DTR_N UART1_SOUT */ \ -{ GPIO1_BASE, GPIO_IN, GPIO_ALT2 }, /* GPIO39 UART0_RI_N UART1_SIN */ \ -{ GPIO1_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO40 UIC_IRQ(0) */ \ -{ GPIO1_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO41 UIC_IRQ(1) */ \ -{ GPIO1_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO42 UIC_IRQ(2) */ \ -{ GPIO1_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO43 UIC_IRQ(3) */ \ -{ GPIO1_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO44 UIC_IRQ(4) DMA_ACK(1) */ \ -{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO45 UIC_IRQ(6) DMA_EOT/TC(1) */ \ -{ GPIO1_BASE, GPIO_BI, GPIO_SEL }, /* GPIO46 UIC_IRQ(7) DMA_REQ(0) */ \ -{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO47 UIC_IRQ(8) DMA_ACK(0) */ \ -{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO48 UIC_IRQ(9) DMA_EOT/TC(0) */ \ -{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO49 Unselect via TraceSelect Bit */ \ -{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO50 Unselect via TraceSelect Bit */ \ -{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO51 Unselect via TraceSelect Bit */ \ -{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO52 Unselect via TraceSelect Bit */ \ -{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO53 Unselect via TraceSelect Bit */ \ -{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO54 Unselect via TraceSelect Bit */ \ -{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO55 Unselect via TraceSelect Bit */ \ -{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO56 Unselect via TraceSelect Bit */ \ -{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO57 Unselect via TraceSelect Bit */ \ -{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO58 Unselect via TraceSelect Bit */ \ -{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO59 Unselect via TraceSelect Bit */ \ -{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO60 Unselect via TraceSelect Bit */ \ -{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO61 Unselect via TraceSelect Bit */ \ -{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO62 Unselect via TraceSelect Bit */ \ -{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO63 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO32 USB2D_OPMODE0 */ \ +{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO33 USB2D_OPMODE1 */ \ +{GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_NO_CHG}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \ +{GPIO1_BASE, GPIO_IN, GPIO_ALT3, GPIO_OUT_NO_CHG}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \ +{GPIO1_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO36 UART0_8PIN_CTS_N UART3_SIN*/ \ +{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO37 UART0_RTS_N */ \ +{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_NO_CHG}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \ +{GPIO1_BASE, GPIO_IN, GPIO_ALT2, GPIO_OUT_NO_CHG}, /* GPIO39 UART0_RI_N UART1_SIN */ \ +{GPIO1_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO40 UIC_IRQ(0) */ \ +{GPIO1_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO41 UIC_IRQ(1) */ \ +{GPIO1_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO42 UIC_IRQ(2) */ \ +{GPIO1_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO43 UIC_IRQ(3) */ \ +{GPIO1_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO44 UIC_IRQ(4) DMA_ACK(1) */ \ +{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO45 UIC_IRQ(6) DMA_EOT/TC(1) */ \ +{GPIO1_BASE, GPIO_BI, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO46 UIC_IRQ(7) DMA_REQ(0) */ \ +{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO47 UIC_IRQ(8) DMA_ACK(0) */ \ +{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO48 UIC_IRQ(9) DMA_EOT/TC(0) */ \ +{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO49 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO50 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO51 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO52 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO53 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO54 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO55 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO56 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO57 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO58 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO59 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO60 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO61 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO62 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO63 Unselect via TraceSelect Bit */ \ } \ } -- cgit From efa35cf12d914d4caba942acd5a6c45f217de302 Mon Sep 17 00:00:00 2001 From: Grzegorz Bernacki Date: Fri, 15 Jun 2007 11:19:28 +0200 Subject: ppc4xx: Clean up 440 exceptions handling - Introduced dedicated switches for building 440 and 405 images required for 440-specific machine instructions like 'rfmci' etc. - Exception vectors moved to the proper location (_start moved away from the critical exception handler space, which it occupied) - CriticalInput now serviced (with default handler) - MachineCheck properly serviced (added a dedicated handler and return subroutine) - Overall cleanup of exceptions declared with STD_EXCEPTION macro (unused, unhandled and those not relevant for 4xx were eliminated) - Eliminated Linux leftovers, removed dead code Signed-off-by: Grzegorz Bernacki Signed-off-by: Rafal Jaworowski Signed-off-by: Stefan Roese --- include/configs/pcs440ep.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include/configs/pcs440ep.h') diff --git a/include/configs/pcs440ep.h b/include/configs/pcs440ep.h index 23bdfc8dfb..638031f48f 100644 --- a/include/configs/pcs440ep.h +++ b/include/configs/pcs440ep.h @@ -32,6 +32,7 @@ *----------------------------------------------------------------------*/ #define CONFIG_PCS440EP 1 /* Board is PCS440EP */ #define CONFIG_440EP 1 /* Specific PPC440EP support */ +#define CONFIG_440 1 /* ... PPC440 family */ #define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ -- cgit From 566a494f592ae3b3c0785d90d4e1ba45574880c4 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Fri, 22 Jun 2007 19:11:54 +0200 Subject: [PCS440EP] upgrade the PCS440EP board: - Show on the Status LEDs, some States of the board. - Get the MAC addresses from the EEProm - use PREBOOT - use the CF on the board. - check the U-Boot image in the Flash with a SHA1 checksum. - use dynamic TLB entries generation for the SDRAM Signed-off-by: Heiko Schocher --- include/configs/pcs440ep.h | 83 ++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 80 insertions(+), 3 deletions(-) (limited to 'include/configs/pcs440ep.h') diff --git a/include/configs/pcs440ep.h b/include/configs/pcs440ep.h index 23bdfc8dfb..d471808821 100644 --- a/include/configs/pcs440ep.h +++ b/include/configs/pcs440ep.h @@ -105,19 +105,27 @@ #ifdef CFG_ENV_IS_IN_FLASH #define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ #define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) -#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ +#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ + +#define CONFIG_ENV_OVERWRITE 1 /* Address and size of Redundant Environment Sector */ #define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) #endif /* CFG_ENV_IS_IN_FLASH */ +#define ENV_NAME_REVLEV "revision_level" +#define ENV_NAME_SOLDER "solder_switch" +#define ENV_NAME_DIP "dip" + /*----------------------------------------------------------------------- * DDR SDRAM *----------------------------------------------------------------------*/ #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */ #undef CONFIG_DDR_ECC /* don't use ECC */ #define SPD_EEPROM_ADDRESS {0x50} +#define CONFIG_PROG_SDRAM_TLB 1 +#define CONFIG_PPC4xx_USE_SPD_DDR_INIT_HANG 1 /*----------------------------------------------------------------------- * I2C @@ -142,6 +150,8 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "hostname=pcs440ep\0" \ + "use_eeprom_ethaddr=default\0" \ + "cs_test=off\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ "nfsroot=${serverip}:${rootpath}\0" \ "ramargs=setenv bootargs root=/dev/ram rw\0" \ @@ -172,6 +182,36 @@ #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ #endif +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +/* check U-Boot image with SHA1 sum */ +#define CONFIG_SHA1_CHECK_UB_IMG 1 +#define CONFIG_SHA1_START CFG_MONITOR_BASE +#define CONFIG_SHA1_LEN CFG_MONITOR_LEN + +/*----------------------------------------------------------------------- + * Definitions for status LED + */ +#define CONFIG_STATUS_LED 1 /* Status LED enabled */ +#define CONFIG_BOARD_SPECIFIC_LED 1 + +#define STATUS_LED_BIT 0x08 /* LED 1 is on GPIO_PPC_1 */ +#define STATUS_LED_PERIOD ((CFG_HZ / 2) / 5) /* blink at 5 Hz */ +#define STATUS_LED_STATE STATUS_LED_OFF +#define STATUS_LED_BIT1 0x04 /* LED 2 is on GPIO_PPC_2 */ +#define STATUS_LED_PERIOD1 ((CFG_HZ / 2) / 5) /* blink at 5 Hz */ +#define STATUS_LED_STATE1 STATUS_LED_ON +#define STATUS_LED_BIT2 0x02 /* LED 3 is on GPIO_PPC_3 */ +#define STATUS_LED_PERIOD2 ((CFG_HZ / 2) / 5) /* blink at 5 Hz */ +#define STATUS_LED_STATE2 STATUS_LED_OFF +#define STATUS_LED_BIT3 0x01 /* LED 4 is on GPIO_PPC_4 */ +#define STATUS_LED_PERIOD3 ((CFG_HZ / 2) / 5) /* blink at 5 Hz */ +#define STATUS_LED_STATE3 STATUS_LED_OFF + +#define CONFIG_SHOW_BOOT_PROGRESS 1 + #define CONFIG_BAUDRATE 115200 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ @@ -213,7 +253,10 @@ CFG_CMD_DIAG | \ CFG_CMD_EEPROM | \ CFG_CMD_ELF | \ + CFG_CMD_EXT2 | \ + CFG_CMD_FAT | \ CFG_CMD_I2C | \ + CFG_CMD_IDE | \ CFG_CMD_IRQ | \ CFG_CMD_MII | \ CFG_CMD_NET | \ @@ -221,9 +264,8 @@ CFG_CMD_PCI | \ CFG_CMD_PING | \ CFG_CMD_REGINFO | \ + CFG_CMD_REISER | \ CFG_CMD_SDRAM | \ - CFG_CMD_EXT2 | \ - CFG_CMD_FAT | \ CFG_CMD_USB ) @@ -410,4 +452,39 @@ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif +/*----------------------------------------------------------------------- + * IDE/ATA stuff Supports IDE harddisk + *----------------------------------------------------------------------- + */ + +#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ + +#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ +#undef CONFIG_IDE_LED /* LED for ide not supported */ + +#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ +#define CFG_IDE_MAXDEVICE 1 /* max. 2 drives per IDE bus */ + +#define CONFIG_IDE_PREINIT 1 +#define CONFIG_IDE_RESET 1 + +#define CFG_ATA_IDE0_OFFSET 0x0000 + +#define CFG_ATA_BASE_ADDR CFG_CF1 + +/* Offset for data I/O */ +#define CFG_ATA_DATA_OFFSET 0 + +/* Offset for normal register accesses */ +#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET) + +/* Offset for alternate registers */ +#define CFG_ATA_ALT_OFFSET (0x0000) + +/* This addresses need to be shifted one place to the left + * ( bus per_addr 20 -30 is connectsd on CF bus A10-A0) + * This values are shifted + */ +#define CFG_ATA_PORT_ADDR(port) ((port) << 1) + #endif /* __CONFIG_H */ -- cgit From 1636d1c8529c006d106287cfbc20cd0a246fe1cb Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Fri, 22 Jun 2007 23:59:00 +0200 Subject: Coding stylke cleanup; rebuild CHANGELOG --- include/configs/pcs440ep.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include/configs/pcs440ep.h') diff --git a/include/configs/pcs440ep.h b/include/configs/pcs440ep.h index 040e589597..333b4a2b7f 100644 --- a/include/configs/pcs440ep.h +++ b/include/configs/pcs440ep.h @@ -104,7 +104,7 @@ #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ #ifdef CFG_ENV_IS_IN_FLASH -#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ +#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ #define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) #define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ -- cgit From 466fff1a7bb5fe764a06450626f6098219f446b8 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 25 Jun 2007 15:57:39 +0200 Subject: ppc4xx: Add pci_pre_init() for 405 boards This patch removes the CFG_PCI_PRE_INIT option completely, since it's not needed anymore with the patch from Matthias Fuchs with the "weak" pci_pre_init() implementation. Signed-off-by: Stefan Roese --- include/configs/pcs440ep.h | 1 - 1 file changed, 1 deletion(-) (limited to 'include/configs/pcs440ep.h') diff --git a/include/configs/pcs440ep.h b/include/configs/pcs440ep.h index 040e589597..5c73658951 100644 --- a/include/configs/pcs440ep.h +++ b/include/configs/pcs440ep.h @@ -267,7 +267,6 @@ #define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/ /* Board-specific PCI */ -#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ #define CFG_PCI_TARGET_INIT #define CFG_PCI_MASTER_INIT -- cgit From a5d71e290f3673269be8eefb4ec44f53412f9461 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Mon, 25 Jun 2007 19:11:37 +0200 Subject: [PCS440EP] get rid of CONFIG_PPC4xx_USE_SPD_DDR_INIT_HANG Signed-off-by: Heiko Schocher --- include/configs/pcs440ep.h | 1 - 1 file changed, 1 deletion(-) (limited to 'include/configs/pcs440ep.h') diff --git a/include/configs/pcs440ep.h b/include/configs/pcs440ep.h index d471808821..c2b5cb8f9f 100644 --- a/include/configs/pcs440ep.h +++ b/include/configs/pcs440ep.h @@ -125,7 +125,6 @@ #undef CONFIG_DDR_ECC /* don't use ECC */ #define SPD_EEPROM_ADDRESS {0x50} #define CONFIG_PROG_SDRAM_TLB 1 -#define CONFIG_PPC4xx_USE_SPD_DDR_INIT_HANG 1 /*----------------------------------------------------------------------- * I2C -- cgit From 26a34560d56a9df5bc2ae23525d9229736134757 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Wed, 4 Jul 2007 22:33:17 -0500 Subject: include/configs: Use new CONFIG_CMD_* in various p* named board config files. Signed-off-by: Jon Loeliger --- include/configs/pcs440ep.h | 49 +++++++++++++++++++++++----------------------- 1 file changed, 25 insertions(+), 24 deletions(-) (limited to 'include/configs/pcs440ep.h') diff --git a/include/configs/pcs440ep.h b/include/configs/pcs440ep.h index 751b51277c..f0cd8d3c02 100644 --- a/include/configs/pcs440ep.h +++ b/include/configs/pcs440ep.h @@ -208,37 +208,38 @@ #define CONFIG_HW_WATCHDOG /* watchdog */ #endif -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DHCP | \ - CFG_CMD_DIAG | \ - CFG_CMD_EEPROM | \ - CFG_CMD_ELF | \ - CFG_CMD_I2C | \ - CFG_CMD_IRQ | \ - CFG_CMD_MII | \ - CFG_CMD_NET | \ - CFG_CMD_NFS | \ - CFG_CMD_PCI | \ - CFG_CMD_PING | \ - CFG_CMD_REGINFO | \ - CFG_CMD_SDRAM | \ - CFG_CMD_EXT2 | \ - CFG_CMD_FAT | \ - CFG_CMD_USB ) +/* + * Command line configuration. + */ +#include +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_DIAG +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_ELF +#define CONFIG_CMD_I2C +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_CMD_NFS +#define CONFIG_CMD_PCI +#define CONFIG_CMD_PING +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_SDRAM +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_USB -#define CONFIG_SUPPORT_VFAT -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +#define CONFIG_SUPPORT_VFAT /* * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -393,7 +394,7 @@ */ #define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */ #define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif @@ -405,7 +406,7 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif -- cgit From 4ef218f6fdf8d747f4589da5252b004e7d2c2876 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Tue, 10 Jul 2007 00:01:28 +0200 Subject: Coding style cleanup; update CHANGELOG. Signed-off-by: Wolfgang Denk --- include/configs/pcs440ep.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'include/configs/pcs440ep.h') diff --git a/include/configs/pcs440ep.h b/include/configs/pcs440ep.h index 0e83e4881a..69d97d66ea 100644 --- a/include/configs/pcs440ep.h +++ b/include/configs/pcs440ep.h @@ -480,9 +480,9 @@ /* Offset for alternate registers */ #define CFG_ATA_ALT_OFFSET (0x0000) -/* This addresses need to be shifted one place to the left +/* These addresses need to be shifted one place to the left * ( bus per_addr 20 -30 is connectsd on CF bus A10-A0) - * This values are shifted + * These values are shifted */ #define CFG_ATA_PORT_ADDR(port) ((port) << 1) -- cgit From 079a136c3588814784561d6e4856970ee82d6e2a Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Tue, 10 Jul 2007 10:12:10 -0500 Subject: include/configs/[p-z]* + misc: Cleanup BOOTP and lingering CFG_CMD_*. Explicitly add in default CONFIG_BOOTP_* options where cmd_confdefs.h used to be included but CONFIG_BOOTP_MASK was not defined. Remove lingering references to CFG_CMD_* symbols. Signed-off-by: Jon Loeliger --- include/configs/pcs440ep.h | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'include/configs/pcs440ep.h') diff --git a/include/configs/pcs440ep.h b/include/configs/pcs440ep.h index f0cd8d3c02..aa66c30f0e 100644 --- a/include/configs/pcs440ep.h +++ b/include/configs/pcs440ep.h @@ -209,6 +209,15 @@ #endif +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ -- cgit From 96e1d75be8193ca79e4215a368bf9d7f2362450f Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Wed, 11 Jul 2007 18:39:11 +0200 Subject: [PCS440EP] - Show on the DIAG LEDs, if the SHA1 check failed - now the Flash ST M29W040B is supported (not tested) - fix the "led" command - fix compile error, if BUILD_DIR is used Signed-off-by: Heiko Schocher --- include/configs/pcs440ep.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'include/configs/pcs440ep.h') diff --git a/include/configs/pcs440ep.h b/include/configs/pcs440ep.h index 69d97d66ea..5ee97c1279 100644 --- a/include/configs/pcs440ep.h +++ b/include/configs/pcs440ep.h @@ -197,16 +197,16 @@ #define CONFIG_STATUS_LED 1 /* Status LED enabled */ #define CONFIG_BOARD_SPECIFIC_LED 1 -#define STATUS_LED_BIT 0x08 /* LED 1 is on GPIO_PPC_1 */ +#define STATUS_LED_BIT 0x08 /* DIAG1 is on GPIO_PPC_1 */ #define STATUS_LED_PERIOD ((CFG_HZ / 2) / 5) /* blink at 5 Hz */ #define STATUS_LED_STATE STATUS_LED_OFF -#define STATUS_LED_BIT1 0x04 /* LED 2 is on GPIO_PPC_2 */ +#define STATUS_LED_BIT1 0x04 /* DIAG2 is on GPIO_PPC_2 */ #define STATUS_LED_PERIOD1 ((CFG_HZ / 2) / 5) /* blink at 5 Hz */ #define STATUS_LED_STATE1 STATUS_LED_ON -#define STATUS_LED_BIT2 0x02 /* LED 3 is on GPIO_PPC_3 */ +#define STATUS_LED_BIT2 0x02 /* DIAG3 is on GPIO_PPC_3 */ #define STATUS_LED_PERIOD2 ((CFG_HZ / 2) / 5) /* blink at 5 Hz */ #define STATUS_LED_STATE2 STATUS_LED_OFF -#define STATUS_LED_BIT3 0x01 /* LED 4 is on GPIO_PPC_4 */ +#define STATUS_LED_BIT3 0x01 /* DIAG4 is on GPIO_PPC_4 */ #define STATUS_LED_PERIOD3 ((CFG_HZ / 2) / 5) /* blink at 5 Hz */ #define STATUS_LED_STATE3 STATUS_LED_OFF -- cgit