From 99744b7e342014082609572af01bb6964e0f5a5a Mon Sep 17 00:00:00 2001 From: Phil Edworthy Date: Tue, 15 May 2012 22:15:51 +0000 Subject: sh: Add SH7269 device and RSK2+SH7269 board This is an sh2a device (max 266MHz) with FPU, video display controller (VDC), 8 serial ports, 4 I2C channels, 3 CAN ports, SD and on-chip USB. The RSK2+SH7269 board uses the SH7269 processor. It is often referred to as just rsk7269. Signed-off-by: Phil Edworthy Signed-off-by: Nobuhiro Iwamatsu --- include/configs/rsk7269.h | 76 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 76 insertions(+) create mode 100644 include/configs/rsk7269.h (limited to 'include/configs/rsk7269.h') diff --git a/include/configs/rsk7269.h b/include/configs/rsk7269.h new file mode 100644 index 0000000000..26c1764212 --- /dev/null +++ b/include/configs/rsk7269.h @@ -0,0 +1,76 @@ +/* + * Configuation settings for the Renesas RSK2+SH7269 board + * + * Copyright (C) 2012 Renesas Electronics Europe Ltd. + * Copyright (C) 2012 Phil Edworthy + * + * This file is released under the terms of GPL v2 and any later version. + * See the file COPYING in the root directory of the source tree for details. + */ + +#ifndef __RSK7269_H +#define __RSK7269_H + +#undef DEBUG +#define CONFIG_SH 1 +#define CONFIG_SH2 1 +#define CONFIG_SH2A 1 +#define CONFIG_CPU_SH7269 1 +#define CONFIG_RSK7269 1 + +#ifndef _CONFIG_CMD_DEFAULT_H +# include +#endif + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_BOOTARGS "console=ttySC7,115200" +#define CONFIG_BOOTDELAY 3 +#define CONFIG_SYS_BAUDRATE_TABLE { CONFIG_BAUDRATE } + +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 256 /* Boot Argument Buffer Size */ +#define CONFIG_SYS_PBSIZE 256 /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ + +/* Serial */ +#define CONFIG_SCIF_CONSOLE +#define CONFIG_CONS_SCIF7 + +/* Memory */ +/* u-boot relocated to top 256KB of ram */ +#define CONFIG_SYS_TEXT_BASE 0x0DFC0000 +#define CONFIG_SYS_SDRAM_BASE 0x0C000000 +#define CONFIG_SYS_SDRAM_SIZE (32 * 1024 * 1024) + +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - 0x100000) +#define CONFIG_SYS_MALLOC_LEN (256 * 1024) +#define CONFIG_SYS_MONITOR_LEN (128 * 1024) +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4*1024*1024) + +/* NOR Flash */ +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT +#define CONFIG_SYS_FLASH_BASE 0x20000000 /* Non-cached */ +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 512 + +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_OFFSET (128 * 1024) +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) +#define CONFIG_ENV_SECT_SIZE (64 * 1024) +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE + +/* Board Clock */ +#define CONFIG_SYS_CLK_FREQ 66125000 +#define CMT_CLK_DIVIDER 32 /* 8 (default), 32, 128 or 512 */ +#define CONFIG_SYS_HZ (CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER) + +/* Network interface */ +#define CONFIG_SMC911X +#define CONFIG_SMC911X_16_BIT +#define CONFIG_SMC911X_BASE 0x24000000 + +#endif /* __RSK7269_H */ -- cgit