From e90fb6afab2c0c074dfb67bacb4de179eb188a24 Mon Sep 17 00:00:00 2001 From: Yuri Tikhonov Date: Thu, 4 Sep 2008 11:19:05 +0200 Subject: USB EHCI: reset root hub Some of multi-function USB controllers (e.g. ISP1562) allow root hub resetting only via EHCI registers. So, this patch adds the corresponding kind of reset to OHCI's hc_reset() if the newly introduced CONFIG_PCI_EHCI_DEVNO option is set (e.g. for Socrates board). Signed-off-by: Yuri Tikhonov Acked-by: Markus Klotzbuecher --- include/configs/socrates.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include/configs/socrates.h') diff --git a/include/configs/socrates.h b/include/configs/socrates.h index 15abec199d..5cc4213deb 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -410,6 +410,7 @@ #define CONFIG_USB_OHCI_NEW 1 #define CONFIG_PCI_OHCI 1 #define CONFIG_PCI_OHCI_DEVNO 3 /* Number in PCI list */ +#define CONFIG_PCI_EHCI_DEVNO (CONFIG_PCI_OHCI_DEVNO / 2) #define CFG_USB_OHCI_MAX_ROOT_PORTS 15 #define CFG_USB_OHCI_SLOT_NAME "ohci_pci" #define CFG_OHCI_SWAP_REG_ACCESS 1 -- cgit From 3e79b588b5199f35016f178fc0d5d1266382097f Mon Sep 17 00:00:00 2001 From: Detlev Zundel Date: Fri, 15 Aug 2008 15:42:12 +0200 Subject: 85xx: Socrates: Major code update. - Update the local bus ranges in the FDT for Linux for the various devices connected to the local bus via chip-select. - Set the LCRR_DBYP bit in the LCRR for local bus frequencies lower than 66 MHz and uses I/O accessor functions consequently. - UPM data update. - Update of default environment and configuration. Use I2C multibus as we do have two I2C buses. Also enable sdram and ext2 commands. Signed-off-by: Wolfgang Grandegger Signed-off-by: Sergei Poselenov Signed-off-by: Detlev Zundel --- include/configs/socrates.h | 110 +++++++++++++++++++++++++++------------------ 1 file changed, 67 insertions(+), 43 deletions(-) (limited to 'include/configs/socrates.h') diff --git a/include/configs/socrates.h b/include/configs/socrates.h index 5cc4213deb..197ed78d5d 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -45,6 +45,7 @@ #define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ +#define CONFIG_BOARD_EARLY_INIT_R 1 /* Call board_early_init_r */ #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ @@ -141,13 +142,12 @@ #define CFG_FLASH_BASE CFG_LBC_FLASH_BASE /* start of FLASH */ #define CFG_BR0_PRELIM 0xfe001001 /* port size 16bit */ -#define CFG_OR0_PRELIM 0xfe000ff7 /* 32MB Flash */ +#define CFG_OR0_PRELIM 0xfe000030 /* 32MB Flash */ #define CFG_BR1_PRELIM 0xfc001001 /* port size 16bit */ -#define CFG_OR1_PRELIM 0xfe000ff7 /* 32MB Flash */ +#define CFG_OR1_PRELIM 0xfe000030 /* 32MB Flash */ #define CFG_FLASH_CFI /* flash is CFI compat. */ #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver*/ -#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector */ #define CFG_MAX_FLASH_BANKS 2 /* number of banks */ #define CFG_MAX_FLASH_SECT 256 /* sectors per device */ @@ -157,7 +157,7 @@ #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ -#define CFG_LBC_LCRR 0x00030008 /* LB clock ratio reg */ +#define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */ #define CFG_LBC_LBCR 0x00000000 /* LB config reg */ #define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ #define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer presc.*/ @@ -171,8 +171,20 @@ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256kB for Mon*/ -#define CFG_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256kB for Mon */ +#define CFG_MALLOC_LEN (4 << 20) /* Reserve 4 MB for malloc */ + +/* FPGA and NAND */ +#define CFG_FPGA_BASE 0xc0000000 +#define CFG_FPGA_SIZE 0x00100000 /* 1 MB */ +#define CFG_HMI_BASE 0xc0010000 +#define CFG_BR3_PRELIM 0xc0001881 /* UPMA, 32-bit */ +#define CFG_OR3_PRELIM 0xfff00000 /* 1 MB */ + +#define CFG_NAND_BASE (CFG_FPGA_BASE + 0x70) +#define CFG_MAX_NAND_DEVICE 1 +#define NAND_MAX_CHIPS 1 +#define CONFIG_CMD_NAND /* Serial Port */ @@ -204,11 +216,14 @@ #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ #define CONFIG_HARD_I2C /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SPEED 102124 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F -#define CFG_I2C_NOPROBES {0x48} /* Don't probe these addrs */ #define CFG_I2C_OFFSET 0x3000 +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_I2C_CMD_TREE +#define CFG_I2C2_OFFSET 0x3100 + /* I2C RTC */ #define CONFIG_RTC_RX8025 /* Use Epson rx8025 rtc via i2c */ #define CFG_I2C_RTC_ADDR 0x32 /* at address 0x32 */ @@ -302,18 +317,18 @@ #define CONFIG_CMD_DTT #undef CONFIG_CMD_EEPROM #define CONFIG_CMD_I2C +#define CONFIG_CMD_SDRAM #define CONFIG_CMD_MII #define CONFIG_CMD_NFS #define CONFIG_CMD_PING #define CONFIG_CMD_SNTP #define CONFIG_CMD_USB - +#define CONFIG_CMD_EXT2 /* EXT2 Support */ #if defined(CONFIG_PCI) #define CONFIG_CMD_PCI #endif - #undef CONFIG_WATCHDOG /* watchdog disabled */ /* @@ -357,50 +372,69 @@ #define CONFIG_LOADADDR 200000 /* default addr for tftp & bootm*/ -#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */ +#define CONFIG_BOOTDELAY 1 /* -1 disables auto-boot */ #define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ + "echo Welcome on the ABB Socrates Board;" \ "echo" #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ #define CONFIG_EXTRA_ENV_SETTINGS \ - "bootfile=$hostname/uImage\0" \ "netdev=eth0\0" \ "consdev=ttyS0\0" \ - "hostname=socrates\0" \ + "uboot_file=/home/tftp/syscon3/u-boot.bin\0" \ + "bootfile=/home/tftp/syscon3/uImage\0" \ + "fdt_file=/home/tftp/syscon3/socrates.dtb\0" \ + "initrd_file=/home/tftp/syscon3/uinitrd.gz\0" \ + "uboot_addr=FFFA0000\0" \ + "kernel_addr=FE000000\0" \ + "fdt_addr=FE1E0000\0" \ + "ramdisk_addr=FE200000\0" \ + "fdt_addr_r=B00000\0" \ + "kernel_addr_r=200000\0" \ + "ramdisk_addr_r=400000\0" \ + "rootpath=/opt/eldk/ppc_85xxDP\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ "nfsroot=$serverip:$rootpath\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addcons=setenv bootargs $bootargs " \ + "console=$consdev,$baudrate\0" \ "addip=setenv bootargs $bootargs " \ "ip=$ipaddr:$serverip:$gatewayip:$netmask" \ ":$hostname:$netdev:off panic=1\0" \ - "addcons=setenv bootargs $bootargs " \ - "console=$consdev,$baudrate\0" \ - "flash_self=run ramargs addip addcons;" \ + "boot_nor=run ramargs addcons;" \ "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ - "flash_nfs=run nfsargs addip addcons;" \ - "bootm ${kernel_addr} - ${fdt_addr}\0" \ "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ "tftp ${fdt_addr_r} ${fdt_file}; " \ "run nfsargs addip addcons;" \ "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ - "fdt_file=$hostname/socrates.dtb\0" \ - "fdt_addr_r=B00000\0" \ - "fdt_addr=FC1E0000\0" \ - "rootpath=/opt/eldk/ppc_85xxDP\0" \ - "kernel_addr=FC000000\0" \ - "kernel_addr_r=200000\0" \ - "ramdisk_addr=FC200000\0" \ - "ramdisk_addr_r=400000\0" \ - "load=tftp 100000 $hostname/u-boot.bin\0" \ - "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \ - "cp.b 100000 fffc0000 40000;" \ + "update_uboot=tftp 100000 ${uboot_file};" \ + "protect off fffa0000 ffffffff;" \ + "era fffa0000 ffffffff;" \ + "cp.b 100000 fffa0000 ${filesize};" \ + "setenv filesize;saveenv\0" \ + "update_kernel=tftp 100000 ${bootfile};" \ + "era fe000000 fe1dffff;" \ + "cp.b 100000 fe000000 ${filesize};" \ "setenv filesize;saveenv\0" \ - "upd=run load update\0" \ + "update_fdt=tftp 100000 ${fdt_file};" \ + "era fe1e0000 fe1fffff;" \ + "cp.b 100000 fe1e0000 ${filesize};" \ + "setenv filesize;saveenv\0" \ + "update_initrd=tftp 100000 ${initrd_file};" \ + "era fe200000 fe9fffff;" \ + "cp.b 100000 fe200000 ${filesize};" \ + "setenv filesize;saveenv\0" \ + "clean_data=era fea00000 fff5ffff\0" \ + "usbargs=setenv bootargs root=/dev/sda1 rw\0" \ + "load_usb=usb start;" \ + "ext2load usb 0:1 ${kernel_addr_r} /boot/uImage\0" \ + "boot_usb=run load_usb usbargs addcons;" \ + "bootm ${kernel_addr_r} - ${fdt_addr};" \ + "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ "" -#define CONFIG_BOOTCOMMAND "run flash_self" +#define CONFIG_BOOTCOMMAND "run boot_nor" /* pass open firmware flat tree */ #define CONFIG_OF_LIBFDT 1 @@ -417,14 +451,4 @@ #define CONFIG_DOS_PARTITION 1 #define CONFIG_USB_STORAGE 1 -/* FPGA and NAND */ -#define CFG_FPGA_BASE 0xc0000000 -#define CFG_BR3_PRELIM 0xc0001881 /* UPMA, 32-bit */ -#define CFG_OR3_PRELIM 0xfff00000 /* 1 MB */ - -#define CFG_NAND_BASE (CFG_FPGA_BASE + 0x70) -#define CFG_MAX_NAND_DEVICE 1 -#define NAND_MAX_CHIPS 1 -#define CONFIG_CMD_NAND - #endif /* __CONFIG_H */ -- cgit From e64987a892353f3d49eb242d997820ef8f538912 Mon Sep 17 00:00:00 2001 From: Anatolij Gustschin Date: Fri, 15 Aug 2008 15:42:13 +0200 Subject: 85xx: socrates: Enable Lime support. This patch adds Lime GDC support together with support for the PWM backlight control through the w83782d chip. The reset pin of the latter is attached to GPIO, so we need to reset it in early_board_init_r. Signed-off-by: Anatolij Gustschin --- include/configs/socrates.h | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) (limited to 'include/configs/socrates.h') diff --git a/include/configs/socrates.h b/include/configs/socrates.h index 197ed78d5d..a981a8fe95 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -186,6 +186,26 @@ #define NAND_MAX_CHIPS 1 #define CONFIG_CMD_NAND +/* LIME GDC */ +#define CFG_LIME_BASE 0xc8000000 +#define CFG_LIME_SIZE 0x04000000 /* 64 MB */ +#define CFG_BR2_PRELIM 0xc80018a1 /* UPMB, 32-bit */ +#define CFG_OR2_PRELIM 0xfc000000 /* 64 MB */ + +#define CONFIG_VIDEO +#define CONFIG_VIDEO_MB862xx +#define CONFIG_CFB_CONSOLE +#define CONFIG_VIDEO_LOGO +#define CONFIG_VIDEO_BMP_LOGO +#define CONFIG_CONSOLE_EXTRA_INFO +#define VIDEO_FB_16BPP_PIXEL_SWAP +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CFG_CONSOLE_IS_IN_ENV +#define CONFIG_VIDEO_SW_CURSOR +#define CONFIG_SPLASH_SCREEN +#define CONFIG_VIDEO_BMP_GZIP +#define CFG_VIDEO_LOGO_MAX_SIZE (2 << 20) /* decompressed img */ + /* Serial Port */ #define CONFIG_CONS_INDEX 1 @@ -228,6 +248,9 @@ #define CONFIG_RTC_RX8025 /* Use Epson rx8025 rtc via i2c */ #define CFG_I2C_RTC_ADDR 0x32 /* at address 0x32 */ +/* I2C W83782G HW-Monitoring IC */ +#define CFG_I2C_W83782G_ADDR 0x28 /* W83782G address */ + /* I2C temp sensor */ /* Socrates uses Maxim's DS75, which is compatible with LM75 */ #define CONFIG_DTT_LM75 1 @@ -324,6 +347,7 @@ #define CONFIG_CMD_SNTP #define CONFIG_CMD_USB #define CONFIG_CMD_EXT2 /* EXT2 Support */ +#define CONFIG_CMD_BMP #if defined(CONFIG_PCI) #define CONFIG_CMD_PCI -- cgit From 5a1aceb0689e2f731491838970884a673ef7e7d3 Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Wed, 10 Sep 2008 22:48:04 +0200 Subject: rename CFG_ENV_IS_IN_FLASH in CONFIG_ENV_IS_IN_FLASH Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- include/configs/socrates.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include/configs/socrates.h') diff --git a/include/configs/socrates.h b/include/configs/socrates.h index a981a8fe95..09e1c8cfc5 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -308,7 +308,7 @@ /* * Environment */ -#define CFG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_IS_IN_FLASH 1 #define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ #define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SECT_SIZE) #define CFG_ENV_SIZE 0x4000 -- cgit From 0e8d158664a913392cb01fb11a948d83f72e105e Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Wed, 10 Sep 2008 22:48:06 +0200 Subject: rename CFG_ENV macros to CONFIG_ENV Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- include/configs/socrates.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'include/configs/socrates.h') diff --git a/include/configs/socrates.h b/include/configs/socrates.h index 09e1c8cfc5..867eb3513c 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -309,11 +309,11 @@ * Environment */ #define CONFIG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ -#define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SECT_SIZE) -#define CFG_ENV_SIZE 0x4000 -#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) -#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ +#define CONFIG_ENV_ADDR (CFG_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE 0x4000 +#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ -- cgit From e99b607a5ec56ce66e0bcccb78480d5e16fb7bc5 Mon Sep 17 00:00:00 2001 From: "u-boot@bugs.denx.de" Date: Thu, 11 Sep 2008 15:40:01 +0200 Subject: 85xx: socrates: Add support for new image format. Signed-off-by: Detlev Zundel --- include/configs/socrates.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'include/configs/socrates.h') diff --git a/include/configs/socrates.h b/include/configs/socrates.h index 867eb3513c..0135ac8531 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -33,6 +33,11 @@ #ifndef __CONFIG_H #define __CONFIG_H +/* new uImage format support */ +#define CONFIG_FIT 1 +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */ + /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ -- cgit From 562788b0a303f3528b920d81f547f5ca77ba528e Mon Sep 17 00:00:00 2001 From: Anatolij Gustschin Date: Wed, 17 Sep 2008 11:45:51 +0200 Subject: socrates: fix SPD EEPROM address Commit be0bd8234b9777ecd63c4c686f72af070d886517 changed SPD EEPROM address to 0x51 and DDR SDRAM detection stopped working. Change this address back to 0x50. Signed-off-by: Anatolij Gustschin --- include/configs/socrates.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include/configs/socrates.h') diff --git a/include/configs/socrates.h b/include/configs/socrates.h index 0135ac8531..28e8fd2f9c 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -117,7 +117,7 @@ #define CONFIG_CHIP_SELECTS_PER_CTRL 2 /* I2C addresses of SPD EEPROMs */ -#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ +#define SPD_EEPROM_ADDRESS 0x50 /* CTLR 0 DIMM 0 */ #define CONFIG_DDR_DEFAULT_CL 30 /* CAS latency 3 */ -- cgit From 5c65ecf7cd94df250b295621f3b24135cbcfe579 Mon Sep 17 00:00:00 2001 From: Anatolij Gustschin Date: Wed, 17 Sep 2008 13:46:17 +0200 Subject: socrates: change default mtest address range Running mtest command on socrates without specifying an address range crashes the board. This patch changes default mtest address range to prevent this behavior. Signed-off-by: Anatolij Gustschin --- include/configs/socrates.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'include/configs/socrates.h') diff --git a/include/configs/socrates.h b/include/configs/socrates.h index 28e8fd2f9c..bbb9d18b5b 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -87,8 +87,8 @@ #define CFG_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */ #undef CFG_DRAM_TEST /* memory test, takes time */ -#define CFG_MEMTEST_START 0x00000000 -#define CFG_MEMTEST_END 0x10000000 +#define CFG_MEMTEST_START 0x00400000 +#define CFG_MEMTEST_END 0x00C00000 /* * Base addresses -- Note these are effective addresses where the -- cgit From abbb90666d5ef2f500ebbedbb80ff60adc56b043 Mon Sep 17 00:00:00 2001 From: Peter Tyser Date: Tue, 23 Sep 2008 12:39:40 -0500 Subject: Remove unused CFG_EEPROM_PAGE_WRITE_ENABLE references Signed-off-by: Peter Tyser --- include/configs/socrates.h | 1 - 1 file changed, 1 deletion(-) (limited to 'include/configs/socrates.h') diff --git a/include/configs/socrates.h b/include/configs/socrates.h index bbb9d18b5b..c4255f14e7 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -263,7 +263,6 @@ #define CFG_DTT_MAX_TEMP 125 #define CFG_DTT_LOW_TEMP -55 #define CFG_DTT_HYSTERESIS 3 -#define CFG_EEPROM_PAGE_WRITE_ENABLE /* necessary for the LM75 chip */ #define CFG_EEPROM_PAGE_WRITE_BITS 4 /* -- cgit From 6d0f6bcf337c5261c08fabe12982178c2c489d76 Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Thu, 16 Oct 2008 15:01:15 +0200 Subject: rename CFG_ macros to CONFIG_SYS Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- include/configs/socrates.h | 212 ++++++++++++++++++++++----------------------- 1 file changed, 106 insertions(+), 106 deletions(-) (limited to 'include/configs/socrates.h') diff --git a/include/configs/socrates.h b/include/configs/socrates.h index c4255f14e7..c67db8f25d 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -84,20 +84,20 @@ #define CONFIG_BTB /* toggle branch predition */ #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ -#define CFG_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */ +#define CONFIG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */ -#undef CFG_DRAM_TEST /* memory test, takes time */ -#define CFG_MEMTEST_START 0x00400000 -#define CFG_MEMTEST_END 0x00C00000 +#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ +#define CONFIG_SYS_MEMTEST_START 0x00400000 +#define CONFIG_SYS_MEMTEST_END 0x00C00000 /* * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) */ -#define CFG_CCSRBAR_DEFAULT 0xFF700000 /* CCSRBAR Default */ -#define CFG_CCSRBAR 0xE0000000 /* relocated CCSRBAR */ -#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ -#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xFF700000 /* CCSRBAR Default */ +#define CONFIG_SYS_CCSRBAR 0xE0000000 /* relocated CCSRBAR */ +#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ +#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ /* DDR Setup */ #define CONFIG_FSL_DDR2 @@ -108,8 +108,8 @@ #undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef -#define CFG_DDR_SDRAM_BASE 0x00000000 -#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_VERY_BIG_RAM #define CONFIG_NUM_DDR_CONTROLLERS 1 @@ -122,80 +122,80 @@ #define CONFIG_DDR_DEFAULT_CL 30 /* CAS latency 3 */ /* Hardcoded values, to use instead of SPD */ -#define CFG_DDR_CS0_BNDS 0x0000000f -#define CFG_DDR_CS0_CONFIG 0x80010102 -#define CFG_DDR_TIMING_0 0x00260802 -#define CFG_DDR_TIMING_1 0x3935D322 -#define CFG_DDR_TIMING_2 0x14904CC8 -#define CFG_DDR_MODE 0x00480432 -#define CFG_DDR_INTERVAL 0x030C0100 -#define CFG_DDR_CONFIG_2 0x04400000 -#define CFG_DDR_CONFIG 0xC3008000 -#define CFG_DDR_CLK_CONTROL 0x03800000 -#define CFG_SDRAM_SIZE 256 /* in Megs */ +#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f +#define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 +#define CONFIG_SYS_DDR_TIMING_0 0x00260802 +#define CONFIG_SYS_DDR_TIMING_1 0x3935D322 +#define CONFIG_SYS_DDR_TIMING_2 0x14904CC8 +#define CONFIG_SYS_DDR_MODE 0x00480432 +#define CONFIG_SYS_DDR_INTERVAL 0x030C0100 +#define CONFIG_SYS_DDR_CONFIG_2 0x04400000 +#define CONFIG_SYS_DDR_CONFIG 0xC3008000 +#define CONFIG_SYS_DDR_CLK_CONTROL 0x03800000 +#define CONFIG_SYS_SDRAM_SIZE 256 /* in Megs */ /* * Flash on the LocalBus */ -#define CFG_LBC_CACHE_BASE 0xf0000000 /* Localbus cacheable */ +#define CONFIG_SYS_LBC_CACHE_BASE 0xf0000000 /* Localbus cacheable */ -#define CFG_FLASH0 0xFE000000 -#define CFG_FLASH1 0xFC000000 -#define CFG_FLASH_BANKS_LIST { CFG_FLASH1, CFG_FLASH0 } +#define CONFIG_SYS_FLASH0 0xFE000000 +#define CONFIG_SYS_FLASH1 0xFC000000 +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 } -#define CFG_LBC_FLASH_BASE CFG_FLASH1 /* Localbus flash start */ -#define CFG_FLASH_BASE CFG_LBC_FLASH_BASE /* start of FLASH */ +#define CONFIG_SYS_LBC_FLASH_BASE CONFIG_SYS_FLASH1 /* Localbus flash start */ +#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_LBC_FLASH_BASE /* start of FLASH */ -#define CFG_BR0_PRELIM 0xfe001001 /* port size 16bit */ -#define CFG_OR0_PRELIM 0xfe000030 /* 32MB Flash */ -#define CFG_BR1_PRELIM 0xfc001001 /* port size 16bit */ -#define CFG_OR1_PRELIM 0xfe000030 /* 32MB Flash */ +#define CONFIG_SYS_BR0_PRELIM 0xfe001001 /* port size 16bit */ +#define CONFIG_SYS_OR0_PRELIM 0xfe000030 /* 32MB Flash */ +#define CONFIG_SYS_BR1_PRELIM 0xfc001001 /* port size 16bit */ +#define CONFIG_SYS_OR1_PRELIM 0xfe000030 /* 32MB Flash */ -#define CFG_FLASH_CFI /* flash is CFI compat. */ +#define CONFIG_SYS_FLASH_CFI /* flash is CFI compat. */ #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver*/ -#define CFG_MAX_FLASH_BANKS 2 /* number of banks */ -#define CFG_MAX_FLASH_SECT 256 /* sectors per device */ -#undef CFG_FLASH_CHECKSUM -#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per device */ +#undef CONFIG_SYS_FLASH_CHECKSUM +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ -#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ +#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ -#define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */ -#define CFG_LBC_LBCR 0x00000000 /* LB config reg */ -#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ -#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer presc.*/ +#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ +#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ +#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ +#define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer presc.*/ #define CONFIG_L1_INIT_RAM -#define CFG_INIT_RAM_LOCK 1 -#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ -#define CFG_INIT_RAM_END 0x4000 /* End used area in RAM */ +#define CONFIG_SYS_INIT_RAM_LOCK 1 +#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ +#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End used area in RAM */ -#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data*/ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data*/ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256kB for Mon */ -#define CFG_MALLOC_LEN (4 << 20) /* Reserve 4 MB for malloc */ +#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256kB for Mon */ +#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* Reserve 4 MB for malloc */ /* FPGA and NAND */ -#define CFG_FPGA_BASE 0xc0000000 -#define CFG_FPGA_SIZE 0x00100000 /* 1 MB */ -#define CFG_HMI_BASE 0xc0010000 -#define CFG_BR3_PRELIM 0xc0001881 /* UPMA, 32-bit */ -#define CFG_OR3_PRELIM 0xfff00000 /* 1 MB */ - -#define CFG_NAND_BASE (CFG_FPGA_BASE + 0x70) -#define CFG_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_FPGA_BASE 0xc0000000 +#define CONFIG_SYS_FPGA_SIZE 0x00100000 /* 1 MB */ +#define CONFIG_SYS_HMI_BASE 0xc0010000 +#define CONFIG_SYS_BR3_PRELIM 0xc0001881 /* UPMA, 32-bit */ +#define CONFIG_SYS_OR3_PRELIM 0xfff00000 /* 1 MB */ + +#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_FPGA_BASE + 0x70) +#define CONFIG_SYS_MAX_NAND_DEVICE 1 #define NAND_MAX_CHIPS 1 #define CONFIG_CMD_NAND /* LIME GDC */ -#define CFG_LIME_BASE 0xc8000000 -#define CFG_LIME_SIZE 0x04000000 /* 64 MB */ -#define CFG_BR2_PRELIM 0xc80018a1 /* UPMB, 32-bit */ -#define CFG_OR2_PRELIM 0xfc000000 /* 64 MB */ +#define CONFIG_SYS_LIME_BASE 0xc8000000 +#define CONFIG_SYS_LIME_SIZE 0x04000000 /* 64 MB */ +#define CONFIG_SYS_BR2_PRELIM 0xc80018a1 /* UPMB, 32-bit */ +#define CONFIG_SYS_OR2_PRELIM 0xfc000000 /* 64 MB */ #define CONFIG_VIDEO #define CONFIG_VIDEO_MB862xx @@ -205,33 +205,33 @@ #define CONFIG_CONSOLE_EXTRA_INFO #define VIDEO_FB_16BPP_PIXEL_SWAP #define CONFIG_VGA_AS_SINGLE_DEVICE -#define CFG_CONSOLE_IS_IN_ENV +#define CONFIG_SYS_CONSOLE_IS_IN_ENV #define CONFIG_VIDEO_SW_CURSOR #define CONFIG_SPLASH_SCREEN #define CONFIG_VIDEO_BMP_GZIP -#define CFG_VIDEO_LOGO_MAX_SIZE (2 << 20) /* decompressed img */ +#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) /* decompressed img */ /* Serial Port */ #define CONFIG_CONS_INDEX 1 #undef CONFIG_SERIAL_SOFTWARE_FIFO -#define CFG_NS16550 -#define CFG_NS16550_SERIAL -#define CFG_NS16550_REG_SIZE 1 -#define CFG_NS16550_CLK get_bus_freq(0) +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) -#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) -#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) #define CONFIG_BAUDRATE 115200 -#define CFG_BAUDRATE_TABLE \ +#define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ +#ifdef CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " #endif @@ -241,44 +241,44 @@ #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ #define CONFIG_HARD_I2C /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CFG_I2C_SPEED 102124 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F -#define CFG_I2C_OFFSET 0x3000 +#define CONFIG_SYS_I2C_SPEED 102124 /* I2C speed and slave address */ +#define CONFIG_SYS_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C_OFFSET 0x3000 #define CONFIG_I2C_MULTI_BUS #define CONFIG_I2C_CMD_TREE -#define CFG_I2C2_OFFSET 0x3100 +#define CONFIG_SYS_I2C2_OFFSET 0x3100 /* I2C RTC */ #define CONFIG_RTC_RX8025 /* Use Epson rx8025 rtc via i2c */ -#define CFG_I2C_RTC_ADDR 0x32 /* at address 0x32 */ +#define CONFIG_SYS_I2C_RTC_ADDR 0x32 /* at address 0x32 */ /* I2C W83782G HW-Monitoring IC */ -#define CFG_I2C_W83782G_ADDR 0x28 /* W83782G address */ +#define CONFIG_SYS_I2C_W83782G_ADDR 0x28 /* W83782G address */ /* I2C temp sensor */ /* Socrates uses Maxim's DS75, which is compatible with LM75 */ #define CONFIG_DTT_LM75 1 #define CONFIG_DTT_SENSORS {4} /* Sensor addresses */ -#define CFG_DTT_MAX_TEMP 125 -#define CFG_DTT_LOW_TEMP -55 -#define CFG_DTT_HYSTERESIS 3 -#define CFG_EEPROM_PAGE_WRITE_BITS 4 +#define CONFIG_SYS_DTT_MAX_TEMP 125 +#define CONFIG_SYS_DTT_LOW_TEMP -55 +#define CONFIG_SYS_DTT_HYSTERESIS 3 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* * General PCI * Memory space is mapped 1-1. */ -#define CFG_PCI_PHYS 0x80000000 /* 1G PCI TLB */ +#define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */ /* PCI is clocked by the external source at 33 MHz */ #define CONFIG_PCI_CLK_FREQ 33000000 -#define CFG_PCI1_MEM_BASE 0x80000000 -#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE -#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI1_IO_BASE 0xE2000000 -#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE -#define CFG_PCI1_IO_SIZE 0x01000000 /* 16M */ +#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 +#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE +#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCI1_IO_BASE 0xE2000000 +#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE +#define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */ #if defined(CONFIG_PCI) #define CONFIG_PCI_PNP /* do pci plug-and-play */ @@ -314,13 +314,13 @@ */ #define CONFIG_ENV_IS_IN_FLASH 1 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ -#define CONFIG_ENV_ADDR (CFG_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) #define CONFIG_ENV_SIZE 0x4000 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE) #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ #define CONFIG_TIMESTAMP /* Print image info with ts */ @@ -362,27 +362,27 @@ /* * Miscellaneous configurable options */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_LOAD_ADDR 0x2000000 /* default load address */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) - #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ + #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #else - #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ + #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ #endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buf Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buf Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ /* * Internal Definitions @@ -473,9 +473,9 @@ #define CONFIG_PCI_OHCI 1 #define CONFIG_PCI_OHCI_DEVNO 3 /* Number in PCI list */ #define CONFIG_PCI_EHCI_DEVNO (CONFIG_PCI_OHCI_DEVNO / 2) -#define CFG_USB_OHCI_MAX_ROOT_PORTS 15 -#define CFG_USB_OHCI_SLOT_NAME "ohci_pci" -#define CFG_OHCI_SWAP_REG_ACCESS 1 +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci" +#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1 #define CONFIG_DOS_PARTITION 1 #define CONFIG_USB_STORAGE 1 -- cgit From 801a194616d95e6fc426a176d9615ccbf9876c7f Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Thu, 20 Nov 2008 12:01:02 -0600 Subject: Removed unused CONFIG_L1_INIT_RAM symbol. Prevent further viral propogation of the unused symbol CONFIG_L1_INIT_RAM by just removing it. Signed-off-by: Jon Loeliger --- include/configs/socrates.h | 1 - 1 file changed, 1 deletion(-) (limited to 'include/configs/socrates.h') diff --git a/include/configs/socrates.h b/include/configs/socrates.h index c67db8f25d..e89b5a3fb0 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -167,7 +167,6 @@ #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer presc.*/ -#define CONFIG_L1_INIT_RAM #define CONFIG_SYS_INIT_RAM_LOCK 1 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ #define CONFIG_SYS_INIT_RAM_END 0x4000 /* End used area in RAM */ -- cgit From ba490b7761c62b549c222a9723e532dc801a3899 Mon Sep 17 00:00:00 2001 From: Peter Tyser Date: Mon, 1 Dec 2008 16:22:45 -0600 Subject: Remove unused CONFIG_ADDR_STREAMING defines Signed-off-by: Peter Tyser --- include/configs/socrates.h | 1 - 1 file changed, 1 deletion(-) (limited to 'include/configs/socrates.h') diff --git a/include/configs/socrates.h b/include/configs/socrates.h index e89b5a3fb0..cbf04e3f2d 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -82,7 +82,6 @@ */ #define CONFIG_L2_CACHE /* toggle L2 cache */ #define CONFIG_BTB /* toggle branch predition */ -#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ #define CONFIG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */ -- cgit