From 57897c13de03ac0136d64641a3eab526c6810387 Mon Sep 17 00:00:00 2001 From: Vignesh R Date: Wed, 21 Dec 2016 10:42:32 +0530 Subject: spi: cadence_qspi_apb: Use 32 bit indirect write transaction when possible According to Section 11.15.4.9.2 Indirect Write Controller of K2G SoC TRM SPRUHY8D[1], the external master is only permitted to issue 32-bit data interface writes until the last word of an indirect transfer otherwise indirect writes is known to fails sometimes. So, make sure that QSPI indirect writes are 32 bit sized except for the last write. If the txbuf is unaligned then use bounce buffer to avoid data aborts. So, now that the driver uses bounce_buffer, enable CONFIG_BOUNCE_BUFFER for all boards that use Cadence QSPI driver. [1]www.ti.com/lit/ug/spruhy8d/spruhy8d.pdf Signed-off-by: Vignesh R Reviewed-by: Marek Vasut Reviewed-by: Jagan Teki --- include/configs/stv0991.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include/configs/stv0991.h') diff --git a/include/configs/stv0991.h b/include/configs/stv0991.h index bfd1bd7192..09a3064bd6 100644 --- a/include/configs/stv0991.h +++ b/include/configs/stv0991.h @@ -74,6 +74,7 @@ #ifdef CONFIG_OF_CONTROL /* QSPI is controlled via DT */ #define CONFIG_CQSPI_DECODER 0 #define CONFIG_CQSPI_REF_CLK ((30/4)/2)*1000*1000 +#define CONFIG_BOUNCE_BUFFER #endif -- cgit