From 16d88f415ab799287672ae6cd08bf3ce975de2b5 Mon Sep 17 00:00:00 2001 From: Suresh Gupta Date: Mon, 25 Mar 2013 07:40:13 +0000 Subject: Enable XAUI interface for B4860QDS - Added SERDES2 PRTCLs = 0x98, 0x9E - Default Phy Addresses for Teranetics PHY on XAUI card The PHY addresses of Teranetics PHY on XAUI riser card are assigned based on the slot it is in. Switches SW4[2:4] and SW6[2:4] on AMC2PEX-2S On B4860QDS, AMC2PEX card decide the PHY addresses on slot1 and slot2 - Configure MDIO for 10Gig Mac Signed-off-by: Suresh Gupta Signed-off-by: Andy Fleming --- include/configs/B4860QDS.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'include/configs') diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h index b09119a2f2..cfab1e8140 100644 --- a/include/configs/B4860QDS.h +++ b/include/configs/B4860QDS.h @@ -623,7 +623,11 @@ unsigned long get_board_ddr_clk(void); #ifdef CONFIG_FMAN_ENET #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x10 #define CONFIG_SYS_FM1_DTSEC6_PHY_ADDR 0x11 -#define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 4 + +/*B4860 QDS AMC2PEX-2S default PHY_ADDR */ +#define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0x7 /*SLOT 1*/ +#define CONFIG_SYS_FM1_10GEC2_PHY_ADDR 0x6 /*SLOT 2*/ + #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d -- cgit