From bbe0d4db53e30affae1194882075e1e0997c4c5c Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 5 Jun 2015 14:39:32 -0600 Subject: tegra: cros_ec: Add tegra support for Chrome OS EC This requires a change to stdin to include the 'cros-ec-keyb' input device. Put this in the common file, enabled by the relevant CONFIG. Signed-off-by: Simon Glass Signed-off-by: Tom Warren --- include/configs/tegra-common-post.h | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'include/configs') diff --git a/include/configs/tegra-common-post.h b/include/configs/tegra-common-post.h index 0cea795de1..48c1a7a1b6 100644 --- a/include/configs/tegra-common-post.h +++ b/include/configs/tegra-common-post.h @@ -40,8 +40,14 @@ #define STDOUT_LCD "" #endif +#ifdef CONFIG_CROS_EC_KEYB +#define STDOUT_CROS_EC ",cros-ec-keyb" +#else +#define STDOUT_CROS_EC "" +#endif + #define TEGRA_DEVICE_SETTINGS \ - "stdin=serial" STDIN_KBD_KBC STDIN_KBD_USB "\0" \ + "stdin=serial" STDIN_KBD_KBC STDIN_KBD_USB STDOUT_CROS_EC "\0" \ "stdout=serial" STDOUT_LCD "\0" \ "stderr=serial" STDOUT_LCD "\0" \ "" -- cgit From b3b9d7ca324429319df1d1f246643d2ae928beb6 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 5 Jun 2015 14:39:34 -0600 Subject: dm: tegra: cros_ec: Enable Chrome OS EC on Nyan-big Enable the EC and keyboard, using the SPI bus. The EC driver requires a particular format and a deactivation delay. Also U-Boot does not support interrupts. For now, adjust the device tree to comply. At some point we should tidy this up to support interrupts and make tegra and exynos use the same setup. Signed-off-by: Simon Glass Signed-off-by: Tom Warren --- include/configs/nyan-big.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include/configs') diff --git a/include/configs/nyan-big.h b/include/configs/nyan-big.h index a92112f870..515704f2ed 100644 --- a/include/configs/nyan-big.h +++ b/include/configs/nyan-big.h @@ -79,6 +79,8 @@ #define CONFIG_FIT #define CONFIG_OF_LIBFDT +#define CONFIG_KEYBOARD + #include "tegra-common-usb-gadget.h" #include "tegra-common-post.h" -- cgit From 0859b49d127665e507300c56fb279183f13321e9 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 5 Jun 2015 14:39:40 -0600 Subject: tegra: Increase maximum arguments to 32 When setting up large environment variables we can exceed 16 arguemnts. Increase this to avoid problems. Signed-off-by: Simon Glass Signed-off-by: Tom Warren --- include/configs/tegra-common.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include/configs') diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h index 0bac9ad5c4..2d5842229f 100644 --- a/include/configs/tegra-common.h +++ b/include/configs/tegra-common.h @@ -104,7 +104,7 @@ /* Print Buffer Size */ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_MAXARGS 32 /* max number of command args */ /* Boot Argument Buffer Size */ #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) -- cgit From e379b03e6bde7b1e78fbec1adc22d69cd1c3063e Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 5 Jun 2015 14:39:44 -0600 Subject: tegra: config: Allow Chrome OS environment settings to be included Bring these in if they are provided by the board. Signed-off-by: Simon Glass Signed-off-by: Tom Warren --- include/configs/tegra-common-post.h | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'include/configs') diff --git a/include/configs/tegra-common-post.h b/include/configs/tegra-common-post.h index 48c1a7a1b6..483222fbcf 100644 --- a/include/configs/tegra-common-post.h +++ b/include/configs/tegra-common-post.h @@ -58,13 +58,18 @@ #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#ifndef CONFIG_CHROMEOS_EXTRA_ENV_SETTINGS +#define CONFIG_CHROMEOS_EXTRA_ENV_SETTINGS +#endif + #define CONFIG_EXTRA_ENV_SETTINGS \ TEGRA_DEVICE_SETTINGS \ MEM_LAYOUT_ENV_SETTINGS \ "fdt_high=ffffffff\0" \ "initrd_high=ffffffff\0" \ BOOTENV \ - BOARD_EXTRA_ENV_SETTINGS + BOARD_EXTRA_ENV_SETTINGS \ + CONFIG_CHROMEOS_EXTRA_ENV_SETTINGS #if defined(CONFIG_TEGRA20_SFLASH) || defined(CONFIG_TEGRA20_SLINK) || defined(CONFIG_TEGRA114_SPI) #define CONFIG_TEGRA_SPI -- cgit From b7160fabf11f423e879ee9cdcf8f7d0de7964509 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 5 Jun 2015 14:39:46 -0600 Subject: tegra: config: nyan-big: Add options required by Chrome OS boot We need to match the device tree in the FIT with the U-Boot model so we can automatically select the right device tree. Also adjust the load address so that the device tree is not in the way when a zImage kernel tries to extract itself. Signed-off-by: Simon Glass Signed-off-by: Tom Warren --- include/configs/nyan-big.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'include/configs') diff --git a/include/configs/nyan-big.h b/include/configs/nyan-big.h index 515704f2ed..b99d762761 100644 --- a/include/configs/nyan-big.h +++ b/include/configs/nyan-big.h @@ -47,6 +47,7 @@ #define CONFIG_AS3722_POWER #define LCD_BPP LCD_COLOR16 #define CONFIG_SYS_WHITE_ON_BLACK +#define CONFIG_CMD_BMP /* Align LCD to 1MB boundary */ #define CONFIG_LCD_ALIGNMENT MMU_SECTION_SIZE @@ -77,10 +78,14 @@ #define CONFIG_CMD_DHCP #define CONFIG_FIT +#define CONFIG_FIT_BEST_MATCH #define CONFIG_OF_LIBFDT #define CONFIG_KEYBOARD +#undef CONFIG_LOADADDR +#define CONFIG_LOADADDR 0x82408000 + #include "tegra-common-usb-gadget.h" #include "tegra-common-post.h" -- cgit From fb1e3eb9eae5eda7fe9ea0efce60ae95a62d0006 Mon Sep 17 00:00:00 2001 From: Andreas Bießmann Date: Sat, 23 May 2015 23:09:15 +0200 Subject: atngw100: convert to generic board MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Andreas Bießmann --- include/configs/atngw100.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'include/configs') diff --git a/include/configs/atngw100.h b/include/configs/atngw100.h index 1202ec2494..56bd7f87d1 100644 --- a/include/configs/atngw100.h +++ b/include/configs/atngw100.h @@ -14,6 +14,10 @@ #define CONFIG_AT32AP7000 #define CONFIG_ATNGW100 +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_EARLY_INIT_R + /* * Set up the PLL to run at 140 MHz, the CPU to run at the PLL * frequency, the HSB and PBB busses to run at 1/2 the PLL frequency -- cgit From 9eb45aabe0780eb837baefe706482fe7bf68d9fc Mon Sep 17 00:00:00 2001 From: Andreas Bießmann Date: Mon, 11 May 2015 13:07:24 +0200 Subject: avr32: delete non generic board favr-32-ezkit MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Andreas Bießmann --- include/configs/favr-32-ezkit.h | 171 ---------------------------------------- 1 file changed, 171 deletions(-) delete mode 100644 include/configs/favr-32-ezkit.h (limited to 'include/configs') diff --git a/include/configs/favr-32-ezkit.h b/include/configs/favr-32-ezkit.h deleted file mode 100644 index 04f4124de8..0000000000 --- a/include/configs/favr-32-ezkit.h +++ /dev/null @@ -1,171 +0,0 @@ -/* - * Copyright (C) 2008 Atmel Corporation - * - * Configuration settings for the Favr-32 EarthLCD LCD kit. - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -#define CONFIG_AT32AP -#define CONFIG_AT32AP7000 -#define CONFIG_FAVR32_EZKIT - -#define CONFIG_FAVR32_EZKIT_EXT_FLASH - -/* - * Set up the PLL to run at 140 MHz, the CPU to run at the PLL - * frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the - * PLL frequency. - * (CONFIG_SYS_OSC0_HZ * CONFIG_SYS_PLL0_MUL) / CONFIG_SYS_PLL0_DIV = PLL MHz - */ -#define CONFIG_PLL -#define CONFIG_SYS_POWER_MANAGER -#define CONFIG_SYS_OSC0_HZ 20000000 -#define CONFIG_SYS_PLL0_DIV 1 -#define CONFIG_SYS_PLL0_MUL 7 -#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES 16 -/* - * Set the CPU running at: - * PLL / (2^CONFIG_SYS_CLKDIV_CPU) = CPU MHz - */ -#define CONFIG_SYS_CLKDIV_CPU 0 -/* - * Set the HSB running at: - * PLL / (2^CONFIG_SYS_CLKDIV_HSB) = HSB MHz - */ -#define CONFIG_SYS_CLKDIV_HSB 1 -/* - * Set the PBA running at: - * PLL / (2^CONFIG_SYS_CLKDIV_PBA) = PBA MHz - */ -#define CONFIG_SYS_CLKDIV_PBA 2 -/* - * Set the PBB running at: - * PLL / (2^CONFIG_SYS_CLKDIV_PBB) = PBB MHz - */ -#define CONFIG_SYS_CLKDIV_PBB 1 - -/* Reserve VM regions for SDRAM and NOR flash */ -#define CONFIG_SYS_NR_VM_REGIONS 2 - -/* - * The PLLOPT register controls the PLL like this: - * icp = PLLOPT<2> - * ivco = PLLOPT<1:0> - * - * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz). - */ -#define CONFIG_SYS_PLL0_OPT 0x04 - -#define CONFIG_USART_BASE ATMEL_BASE_USART3 -#define CONFIG_USART_ID 3 - -/* User serviceable stuff */ -#define CONFIG_DOS_PARTITION - -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - -#define CONFIG_STACKSIZE (2048) - -#define CONFIG_BAUDRATE 115200 -#define CONFIG_BOOTARGS \ - "root=/dev/mtdblock1 rootfstype=jffs fbmem=1800k" - -#define CONFIG_BOOTCOMMAND \ - "fsload; bootm $(fileaddr)" - -#define CONFIG_BOOTDELAY 1 - -/* - * After booting the board for the first time, new ethernet addresses - * should be generated and assigned to the environment variables - * "ethaddr" and "eth1addr". This is normally done during production. - */ -#define CONFIG_OVERWRITE_ETHADDR_ONCE - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_MMC - -#undef CONFIG_CMD_FPGA -#undef CONFIG_CMD_SETGETDCR -#undef CONFIG_CMD_SOURCE -#undef CONFIG_CMD_XIMG - -#define CONFIG_ATMEL_USART -#define CONFIG_MACB -#define CONFIG_PORTMUX_PIO -#define CONFIG_SYS_NR_PIOS 5 -#define CONFIG_SYS_HSDRAMC -#define CONFIG_MMC -#define CONFIG_GENERIC_ATMEL_MCI -#define CONFIG_GENERIC_MMC - -#define CONFIG_SYS_DCACHE_LINESZ 32 -#define CONFIG_SYS_ICACHE_LINESZ 32 - -#define CONFIG_NR_DRAM_BANKS 1 - -/* External flash on Favr-32 */ -#if 0 -#define CONFIG_SYS_FLASH_CFI 1 -#define CONFIG_FLASH_CFI_DRIVER 1 -#endif - -#define CONFIG_SYS_FLASH_BASE 0x00000000 -#define CONFIG_SYS_FLASH_SIZE 0x800000 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 135 - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_TEXT_BASE 0x00000000 - -#define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE -#define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE -#define CONFIG_SYS_SDRAM_BASE EBI_SDRAM_BASE - -#define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_SIZE 65536 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE) - -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE) - -#define CONFIG_SYS_MALLOC_LEN (256*1024) - -/* Allow 4MB for the kernel run-time image */ -#define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000) -#define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024) - -/* Other configuration settings that shouldn't have to change all that often */ -#define CONFIG_SYS_PROMPT "U-Boot> " -#define CONFIG_SYS_CBSIZE 256 -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_LONGHELP - -#define CONFIG_SYS_MEMTEST_START EBI_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x700000) -#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 } - -#endif /* __CONFIG_H */ -- cgit From e36930764471711c12a7fac8dfb9535b96a284ca Mon Sep 17 00:00:00 2001 From: Andreas Bießmann Date: Mon, 11 May 2015 13:07:25 +0200 Subject: avr32: delete non generic board hammerhead MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Andreas Bießmann --- include/configs/hammerhead.h | 147 ------------------------------------------- 1 file changed, 147 deletions(-) delete mode 100644 include/configs/hammerhead.h (limited to 'include/configs') diff --git a/include/configs/hammerhead.h b/include/configs/hammerhead.h deleted file mode 100644 index 274f2a81b8..0000000000 --- a/include/configs/hammerhead.h +++ /dev/null @@ -1,147 +0,0 @@ -/* - * Copyright (C) 2008 Miromico AG - * - * Configuration settings for the Miromico Hammerhead AVR32 board - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_AT32AP -#define CONFIG_AT32AP7000 -#define CONFIG_HAMMERHEAD - -/* - * Set up the PLL to run at 125 MHz, the CPU to run at the PLL - * frequency, the HSB and PBB busses to run at 1/2 the PLL frequency - * and the PBA bus to run at 1/4 the PLL frequency. - */ -#define CONFIG_PLL -#define CONFIG_SYS_POWER_MANAGER -#define CONFIG_SYS_OSC0_HZ 25000000 -#define CONFIG_SYS_PLL0_DIV 1 -#define CONFIG_SYS_PLL0_MUL 5 -#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES 16 -#define CONFIG_SYS_CLKDIV_CPU 0 -#define CONFIG_SYS_CLKDIV_HSB 1 -#define CONFIG_SYS_CLKDIV_PBA 2 -#define CONFIG_SYS_CLKDIV_PBB 1 - -/* Reserve VM regions for SDRAM and NOR flash */ -#define CONFIG_SYS_NR_VM_REGIONS 2 - -/* - * The PLLOPT register controls the PLL like this: - * icp = PLLOPT<2> - * ivco = PLLOPT<1:0> - * - * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz). - */ -#define CONFIG_SYS_PLL0_OPT 0x04 - -#define CONFIG_USART_BASE ATMEL_BASE_USART1 -#define CONFIG_USART_ID 1 - -#define CONFIG_HOSTNAME hammerhead - -/* User serviceable stuff */ -#define CONFIG_DOS_PARTITION - -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - -#define CONFIG_STACKSIZE (2048) - -#define CONFIG_BAUDRATE 115200 -#define CONFIG_BOOTARGS \ - "console=ttyS0 root=mtd1 rootfstype=jffs2" -#define CONFIG_BOOTCOMMAND \ - "fsload; bootm" - -#define CONFIG_BOOTDELAY 1 - -/* - * After booting the board for the first time, new ethernet address - * should be generated and assigned to the environment variables - * "ethaddr". This is normally done during production. - */ -#define CONFIG_OVERWRITE_ETHADDR_ONCE - -/* - * BOOTP/DHCP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_MMC -#undef CONFIG_CMD_FPGA -#undef CONFIG_CMD_SETGETDCR - -#define CONFIG_ATMEL_USART -#define CONFIG_MACB -#define CONFIG_PORTMUX_PIO -#define CONFIG_SYS_NR_PIOS 5 -#define CONFIG_SYS_HSDRAMC -#define CONFIG_MMC -#define CONFIG_GENERIC_ATMEL_MCI -#define CONFIG_GENERIC_MMC - -#define CONFIG_SYS_DCACHE_LINESZ 32 -#define CONFIG_SYS_ICACHE_LINESZ 32 - -#define CONFIG_NR_DRAM_BANKS 1 - -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_FLASH_CFI_DRIVER - -#define CONFIG_SYS_FLASH_BASE 0x00000000 -#define CONFIG_SYS_FLASH_SIZE 0x800000 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 135 - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_TEXT_BASE 0x00000000 - -#define CONFIG_SYS_INTRAM_BASE 0x24000000 -#define CONFIG_SYS_INTRAM_SIZE 0x8000 - -#define CONFIG_SYS_SDRAM_BASE 0x10000000 - -#define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_SIZE 65536 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE) - -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE) - -#define CONFIG_SYS_MALLOC_LEN (256*1024) - - -/* Allow 4MB for the kernel run-time image */ -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x00400000) -#define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024) - -/* Other configuration settings that shouldn't have to change all that often */ -#define CONFIG_SYS_PROMPT "Hammerhead> " -#define CONFIG_SYS_CBSIZE 256 -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_LONGHELP - -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x1f00000) - -#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 } - -#endif /* __CONFIG_H */ -- cgit From c62d2f8fc5c682ad541d98e289434a0f76d5ad4b Mon Sep 17 00:00:00 2001 From: Andreas Bießmann Date: Mon, 11 May 2015 13:07:26 +0200 Subject: avr32: delete non generic board mimc200 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Andreas Bießmann --- include/configs/mimc200.h | 176 ---------------------------------------------- 1 file changed, 176 deletions(-) delete mode 100644 include/configs/mimc200.h (limited to 'include/configs') diff --git a/include/configs/mimc200.h b/include/configs/mimc200.h deleted file mode 100644 index e8e5ae73ec..0000000000 --- a/include/configs/mimc200.h +++ /dev/null @@ -1,176 +0,0 @@ -/* - * Copyright (C) 2006 Atmel Corporation - * - * Configuration settings for the AVR32 Network Gateway - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -#define CONFIG_AT32AP -#define CONFIG_AT32AP7000 -#define CONFIG_MIMC200 - -#define CONFIG_MIMC200_EXT_FLASH - -/* - * Set up the PLL to run at 140 MHz, the CPU to run at the PLL - * frequency, the HSB and PBB busses to run at 1/2 the PLL frequency - * and the PBA bus to run at 1/4 the PLL frequency. - */ -#define CONFIG_PLL -#define CONFIG_SYS_POWER_MANAGER -#define CONFIG_SYS_OSC0_HZ 10000000 -#define CONFIG_SYS_PLL0_DIV 1 -#define CONFIG_SYS_PLL0_MUL 15 -#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES 16 -#define CONFIG_SYS_CLKDIV_CPU 0 -#define CONFIG_SYS_CLKDIV_HSB 1 -#define CONFIG_SYS_CLKDIV_PBA 2 -#define CONFIG_SYS_CLKDIV_PBB 1 - -/* Reserve VM regions for SDRAM, NOR flash and FRAM */ -#define CONFIG_SYS_NR_VM_REGIONS 3 - -/* - * The PLLOPT register controls the PLL like this: - * icp = PLLOPT<2> - * ivco = PLLOPT<1:0> - * - * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz). - */ -#define CONFIG_SYS_PLL0_OPT 0x04 - -#define CONFIG_USART_BASE ATMEL_BASE_USART1 -#define CONFIG_USART_ID 1 - -#define CONFIG_MIMC200_DBGLINK 1 - -/* User serviceable stuff */ -#define CONFIG_DOS_PARTITION - -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - -#define CONFIG_STACKSIZE (2048) - -#define CONFIG_BAUDRATE 115200 -#define CONFIG_BOOTARGS \ - "root=/dev/mtdblock1 rootfstype=jffs2 fbmem=512k console=ttyS1" -#define CONFIG_BOOTCOMMAND \ - "fsload boot/uImage; bootm" - -#define CONFIG_SILENT_CONSOLE /* enable silent startup */ -#define CONFIG_DISABLE_CONSOLE /* disable console */ -#define CONFIG_SYS_DEVICE_NULLDEV /* include nulldev device */ - -#define CONFIG_LCD 1 - -/* - * Only interrupt autoboot if is pressed. Otherwise, garbage - * data on the serial line may interrupt the boot sequence. - */ -#define CONFIG_BOOTDELAY 0 -#define CONFIG_ZERO_BOOTDELAY_CHECK -#define CONFIG_AUTOBOOT - -/* - * After booting the board for the first time, new ethernet addresses - * should be generated and assigned to the environment variables - * "ethaddr" and "eth1addr". This is normally done during production. - */ -#define CONFIG_OVERWRITE_ETHADDR_ONCE - -/* - * BOOTP/DHCP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_MMC - -#define CONFIG_ATMEL_USART -#define CONFIG_MACB -#define CONFIG_PORTMUX_PIO -#define CONFIG_SYS_NR_PIOS 5 -#define CONFIG_SYS_HSDRAMC -#define CONFIG_MMC -#define CONFIG_GENERIC_ATMEL_MCI -#define CONFIG_GENERIC_MMC - -#if defined(CONFIG_LCD) -#define CONFIG_CMD_BMP -#define CONFIG_ATMEL_LCD 1 -#define LCD_BPP LCD_COLOR16 -#define CONFIG_BMP_16BPP 1 -#define CONFIG_FB_ADDR 0x10600000 -#define CONFIG_WHITE_ON_BLACK 1 -#define CONFIG_VIDEO_BMP_GZIP 1 -#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE 262144 -#define CONFIG_ATMEL_LCD_BGR555 1 -#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 -#define CONFIG_SPLASH_SCREEN 1 -#endif - -#define CONFIG_SYS_DCACHE_LINESZ 32 -#define CONFIG_SYS_ICACHE_LINESZ 32 - -#define CONFIG_NR_DRAM_BANKS 1 - -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_FLASH_CFI_DRIVER - -#define CONFIG_SYS_FLASH_BASE 0x00000000 -#define CONFIG_SYS_FLASH_SIZE 0x800000 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 135 - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_TEXT_BASE 0x00000000 - -#define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE -#define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE -#define CONFIG_SYS_SDRAM_BASE EBI_SDRAM_BASE - -#define CONFIG_SYS_FRAM_BASE 0x08000000 -#define CONFIG_SYS_FRAM_SIZE 0x20000 - -#define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_SIZE 65536 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE) - -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE) - -#define CONFIG_SYS_MALLOC_LEN (1024*1024) - -/* Allow 4MB for the kernel run-time image */ -#define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000) -#define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024) - -/* Other configuration settings that shouldn't have to change all that often */ -#define CONFIG_SYS_PROMPT "U-Boot> " -#define CONFIG_SYS_CBSIZE 256 -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_LONGHELP - -#define CONFIG_SYS_MEMTEST_START EBI_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x1f00000) - -#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 } - -#endif /* __CONFIG_H */ -- cgit From e5354b8a9e2ad7035c8623b552e7532ef7b133ae Mon Sep 17 00:00:00 2001 From: Andreas Bießmann Date: Mon, 11 May 2015 13:07:27 +0200 Subject: avr32: delete non generic board's atstk100{3, 4, 6} MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Andreas Bießmann --- include/configs/atstk1003.h | 150 --------------------------------------- include/configs/atstk1004.h | 150 --------------------------------------- include/configs/atstk1006.h | 168 -------------------------------------------- 3 files changed, 468 deletions(-) delete mode 100644 include/configs/atstk1003.h delete mode 100644 include/configs/atstk1004.h delete mode 100644 include/configs/atstk1006.h (limited to 'include/configs') diff --git a/include/configs/atstk1003.h b/include/configs/atstk1003.h deleted file mode 100644 index 4126b66d9d..0000000000 --- a/include/configs/atstk1003.h +++ /dev/null @@ -1,150 +0,0 @@ -/* - * Copyright (C) 2007 Atmel Corporation - * - * Configuration settings for the ATSTK1003 CPU daughterboard - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -#define CONFIG_AT32AP -#define CONFIG_AT32AP7001 -#define CONFIG_ATSTK1003 -#define CONFIG_ATSTK1000 - -/* - * Set up the PLL to run at 140 MHz, the CPU to run at the PLL - * frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the - * PLL frequency. - * (CONFIG_SYS_OSC0_HZ * CONFIG_SYS_PLL0_MUL) / CONFIG_SYS_PLL0_DIV = PLL MHz - */ -#define CONFIG_PLL -#define CONFIG_SYS_POWER_MANAGER -#define CONFIG_SYS_OSC0_HZ 20000000 -#define CONFIG_SYS_PLL0_DIV 1 -#define CONFIG_SYS_PLL0_MUL 7 -#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES 16 -/* - * Set the CPU running at: - * PLL / (2^CONFIG_SYS_CLKDIV_CPU) = CPU MHz - */ -#define CONFIG_SYS_CLKDIV_CPU 0 -/* - * Set the HSB running at: - * PLL / (2^CONFIG_SYS_CLKDIV_HSB) = HSB MHz - */ -#define CONFIG_SYS_CLKDIV_HSB 1 -/* - * Set the PBA running at: - * PLL / (2^CONFIG_SYS_CLKDIV_PBA) = PBA MHz - */ -#define CONFIG_SYS_CLKDIV_PBA 2 -/* - * Set the PBB running at: - * PLL / (2^CONFIG_SYS_CLKDIV_PBB) = PBB MHz - */ -#define CONFIG_SYS_CLKDIV_PBB 1 - -/* Reserve VM regions for SDRAM and NOR flash */ -#define CONFIG_SYS_NR_VM_REGIONS 2 - -/* - * The PLLOPT register controls the PLL like this: - * icp = PLLOPT<2> - * ivco = PLLOPT<1:0> - * - * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz). - */ -#define CONFIG_SYS_PLL0_OPT 0x04 - -#define CONFIG_USART_BASE ATMEL_BASE_USART1 -#define CONFIG_USART_ID 1 - -/* User serviceable stuff */ -#define CONFIG_DOS_PARTITION - -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - -#define CONFIG_STACKSIZE (2048) - -#define CONFIG_BAUDRATE 115200 -#define CONFIG_BOOTARGS \ - "console=ttyS0 root=/dev/mmcblk0p1 rootwait" - -#define CONFIG_BOOTCOMMAND \ - "mmc rescan; ext2load mmc 0:1 0x10400000 /boot/uImage; bootm" - -#define CONFIG_BOOTDELAY 1 - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_MMC - -#undef CONFIG_CMD_FPGA -#undef CONFIG_CMD_NFS -#undef CONFIG_CMD_SETGETDCR -#undef CONFIG_CMD_XIMG - -#define CONFIG_ATMEL_USART -#define CONFIG_PORTMUX_PIO -#define CONFIG_SYS_HSDRAMC -#define CONFIG_MMC -#define CONFIG_GENERIC_ATMEL_MCI -#define CONFIG_GENERIC_MMC - -#define CONFIG_SYS_DCACHE_LINESZ 32 -#define CONFIG_SYS_ICACHE_LINESZ 32 - -#define CONFIG_NR_DRAM_BANKS 1 - -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_FLASH_CFI_DRIVER - -#define CONFIG_SYS_FLASH_BASE 0x00000000 -#define CONFIG_SYS_FLASH_SIZE 0x800000 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 135 - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_TEXT_BASE 0x00000000 - -#define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE -#define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE -#define CONFIG_SYS_SDRAM_BASE EBI_SDRAM_BASE - -#define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_SIZE 65536 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE) - -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE) - -#define CONFIG_SYS_MALLOC_LEN (256*1024) - -/* Allow 4MB for the kernel run-time image */ -#define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000) -#define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024) - -/* Other configuration settings that shouldn't have to change all that often */ -#define CONFIG_SYS_PROMPT "U-Boot> " -#define CONFIG_SYS_CBSIZE 256 -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_LONGHELP - -#define CONFIG_SYS_MEMTEST_START EBI_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x700000) -#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 } - -#endif /* __CONFIG_H */ diff --git a/include/configs/atstk1004.h b/include/configs/atstk1004.h deleted file mode 100644 index 97a1d3ef14..0000000000 --- a/include/configs/atstk1004.h +++ /dev/null @@ -1,150 +0,0 @@ -/* - * Copyright (C) 2007 Atmel Corporation - * - * Configuration settings for the ATSTK1003 CPU daughterboard - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -#define CONFIG_AT32AP -#define CONFIG_AT32AP7002 -#define CONFIG_ATSTK1004 -#define CONFIG_ATSTK1000 - -/* - * Set up the PLL to run at 140 MHz, the CPU to run at the PLL - * frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the - * PLL frequency. - * (CONFIG_SYS_OSC0_HZ * CONFIG_SYS_PLL0_MUL) / CONFIG_SYS_PLL0_DIV = PLL MHz - */ -#define CONFIG_PLL -#define CONFIG_SYS_POWER_MANAGER -#define CONFIG_SYS_OSC0_HZ 20000000 -#define CONFIG_SYS_PLL0_DIV 1 -#define CONFIG_SYS_PLL0_MUL 7 -#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES 16 -/* - * Set the CPU running at: - * PLL / (2^CONFIG_SYS_CLKDIV_CPU) = CPU MHz - */ -#define CONFIG_SYS_CLKDIV_CPU 0 -/* - * Set the HSB running at: - * PLL / (2^CONFIG_SYS_CLKDIV_HSB) = HSB MHz - */ -#define CONFIG_SYS_CLKDIV_HSB 1 -/* - * Set the PBA running at: - * PLL / (2^CONFIG_SYS_CLKDIV_PBA) = PBA MHz - */ -#define CONFIG_SYS_CLKDIV_PBA 2 -/* - * Set the PBB running at: - * PLL / (2^CONFIG_SYS_CLKDIV_PBB) = PBB MHz - */ -#define CONFIG_SYS_CLKDIV_PBB 1 - -/* Reserve VM regions for SDRAM and NOR flash */ -#define CONFIG_SYS_NR_VM_REGIONS 2 - -/* - * The PLLOPT register controls the PLL like this: - * icp = PLLOPT<2> - * ivco = PLLOPT<1:0> - * - * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz). - */ -#define CONFIG_SYS_PLL0_OPT 0x04 - -#define CONFIG_USART_BASE ATMEL_BASE_USART1 -#define CONFIG_USART_ID 1 - -/* User serviceable stuff */ -#define CONFIG_DOS_PARTITION - -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - -#define CONFIG_STACKSIZE (2048) - -#define CONFIG_BAUDRATE 115200 -#define CONFIG_BOOTARGS \ - "console=ttyS0 root=/dev/mmcblk0p1 rootwait" - -#define CONFIG_BOOTCOMMAND \ - "mmc rescan; ext2load mmc 0:1 0x10200000 /boot/uImage; bootm" - -#define CONFIG_BOOTDELAY 1 - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_MMC - -#undef CONFIG_CMD_FPGA -#undef CONFIG_CMD_NFS -#undef CONFIG_CMD_SETGETDCR -#undef CONFIG_CMD_XIMG - -#define CONFIG_ATMEL_USART -#define CONFIG_PORTMUX_PIO -#define CONFIG_SYS_HSDRAMC -#define CONFIG_MMC -#define CONFIG_GENERIC_ATMEL_MCI -#define CONFIG_GENERIC_MMC - -#define CONFIG_SYS_DCACHE_LINESZ 32 -#define CONFIG_SYS_ICACHE_LINESZ 32 - -#define CONFIG_NR_DRAM_BANKS 1 - -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_FLASH_CFI_DRIVER - -#define CONFIG_SYS_FLASH_BASE 0x00000000 -#define CONFIG_SYS_FLASH_SIZE 0x800000 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 135 - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_TEXT_BASE 0x00000000 - -#define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE -#define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE -#define CONFIG_SYS_SDRAM_BASE EBI_SDRAM_BASE - -#define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_SIZE 65536 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE) - -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE) - -#define CONFIG_SYS_MALLOC_LEN (256*1024) - -/* Allow 2MB for the kernel run-time image */ -#define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00200000) -#define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024) - -/* Other configuration settings that shouldn't have to change all that often */ -#define CONFIG_SYS_PROMPT "U-Boot> " -#define CONFIG_SYS_CBSIZE 256 -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_LONGHELP - -#define CONFIG_SYS_MEMTEST_START EBI_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x700000) -#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 } - -#endif /* __CONFIG_H */ diff --git a/include/configs/atstk1006.h b/include/configs/atstk1006.h deleted file mode 100644 index cbf17dbd5f..0000000000 --- a/include/configs/atstk1006.h +++ /dev/null @@ -1,168 +0,0 @@ -/* - * Copyright (C) 2005-2006 Atmel Corporation - * - * Configuration settings for the ATSTK1002 CPU daughterboard - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -#define CONFIG_AT32AP -#define CONFIG_AT32AP7000 -#define CONFIG_ATSTK1006 -#define CONFIG_ATSTK1000 - - -/* - * Set up the PLL to run at 140 MHz, the CPU to run at the PLL - * frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the - * PLL frequency. - * (CONFIG_SYS_OSC0_HZ * CONFIG_SYS_PLL0_MUL) / CONFIG_SYS_PLL0_DIV = PLL MHz - */ -#define CONFIG_PLL -#define CONFIG_SYS_POWER_MANAGER -#define CONFIG_SYS_OSC0_HZ 20000000 -#define CONFIG_SYS_PLL0_DIV 1 -#define CONFIG_SYS_PLL0_MUL 7 -#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES 16 -/* - * Set the CPU running at: - * PLL / (2^CONFIG_SYS_CLKDIV_CPU) = CPU MHz - */ -#define CONFIG_SYS_CLKDIV_CPU 0 -/* - * Set the HSB running at: - * PLL / (2^CONFIG_SYS_CLKDIV_HSB) = HSB MHz - */ -#define CONFIG_SYS_CLKDIV_HSB 1 -/* - * Set the PBA running at: - * PLL / (2^CONFIG_SYS_CLKDIV_PBA) = PBA MHz - */ -#define CONFIG_SYS_CLKDIV_PBA 2 -/* - * Set the PBB running at: - * PLL / (2^CONFIG_SYS_CLKDIV_PBB) = PBB MHz - */ -#define CONFIG_SYS_CLKDIV_PBB 1 - -/* Reserve VM regions for SDRAM and NOR flash */ -#define CONFIG_SYS_NR_VM_REGIONS 2 - -/* - * The PLLOPT register controls the PLL like this: - * icp = PLLOPT<2> - * ivco = PLLOPT<1:0> - * - * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz). - */ -#define CONFIG_SYS_PLL0_OPT 0x04 - -#define CONFIG_USART_BASE ATMEL_BASE_USART1 -#define CONFIG_USART_ID 1 - -/* User serviceable stuff */ -#define CONFIG_DOS_PARTITION - -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - -#define CONFIG_STACKSIZE (2048) - -#define CONFIG_BAUDRATE 115200 -#define CONFIG_BOOTARGS \ - "console=ttyS0 root=mtd3 fbmem=2400k" - -#define CONFIG_BOOTCOMMAND \ - "fsload; bootm $(fileaddr)" - -#define CONFIG_BOOTDELAY 1 - -/* - * After booting the board for the first time, new ethernet addresses - * should be generated and assigned to the environment variables - * "ethaddr" and "eth1addr". This is normally done during production. - */ -#define CONFIG_OVERWRITE_ETHADDR_ONCE - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_MMC - -#undef CONFIG_CMD_FPGA -#undef CONFIG_CMD_SETGETDCR -#undef CONFIG_CMD_SOURCE -#undef CONFIG_CMD_XIMG - -#define CONFIG_ATMEL_USART -#define CONFIG_MACB -#define CONFIG_PORTMUX_PIO -#define CONFIG_SYS_NR_PIOS 5 -#define CONFIG_SYS_HSDRAMC -#define CONFIG_MMC -#define CONFIG_GENERIC_ATMEL_MCI -#define CONFIG_GENERIC_MMC - -#define CONFIG_SYS_DCACHE_LINESZ 32 -#define CONFIG_SYS_ICACHE_LINESZ 32 - -#define CONFIG_NR_DRAM_BANKS 1 - -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_FLASH_CFI_DRIVER - -#define CONFIG_SYS_FLASH_BASE 0x00000000 -#define CONFIG_SYS_FLASH_SIZE 0x800000 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 135 - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_TEXT_BASE 0x00000000 - -#define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE -#define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE -#define CONFIG_SYS_SDRAM_BASE EBI_SDRAM_BASE - -#define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_SIZE 65536 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE) - -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE) - -#define CONFIG_SYS_MALLOC_LEN (256*1024) - -/* Allow 4MB for the kernel run-time image */ -#define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000) -#define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024) - -/* Other configuration settings that shouldn't have to change all that often */ -#define CONFIG_SYS_PROMPT "U-Boot> " -#define CONFIG_SYS_CBSIZE 256 -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_LONGHELP - -#define CONFIG_SYS_MEMTEST_START EBI_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x3f00000) -#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 } - -#endif /* __CONFIG_H */ -- cgit From 0751b138064db28f0866f0c2439afb8b3975180c Mon Sep 17 00:00:00 2001 From: Bernhard Nortmann Date: Wed, 10 Jun 2015 10:51:40 +0200 Subject: sunxi: Enable CONFIG_SYS_64BIT_LBA when AHCI is used Due to absence of CONFIG_SYS_64BIT_LBA, u-boot-sunxi currently has no support for the (GPT) partioning scheme of large disks > 2TB. While the AHCI driver seems to handle this nicely, the problem is that lbaint_t values get truncated to 32-bit. This patch sets CONFIG_SYS_64BIT_LBA from sunxi_common.h for all SoCs that support AHCI (CONFIG_SUNXI_AHCI). Signed-off-by: Bernhard Nortmann Reviewed-by: Hans de Goede Signed-off-by: Hans de Goede --- include/configs/sunxi-common.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include/configs') diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 07db736d31..063abd56a9 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -126,6 +126,7 @@ #define CONFIG_SCSI_AHCI #define CONFIG_SCSI_AHCI_PLAT #define CONFIG_SUNXI_AHCI +#define CONFIG_SYS_64BIT_LBA #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 #define CONFIG_SYS_SCSI_MAX_LUN 1 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ -- cgit From af282245462186b8b06047c379ee85f4d0ec7a9c Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 6 Mar 2015 13:19:03 -0700 Subject: sandbox: Move CONFIG_SANDBOX_SERIAL to Kconfig Move this over to Kconfig and tidy up. Signed-off-by: Simon Glass --- include/configs/sandbox.h | 1 - 1 file changed, 1 deletion(-) (limited to 'include/configs') diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h index 3a857e2a3d..3caa83ce09 100644 --- a/include/configs/sandbox.h +++ b/include/configs/sandbox.h @@ -113,7 +113,6 @@ #define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 115200} -#define CONFIG_SANDBOX_SERIAL #define CONFIG_SYS_NO_FLASH -- cgit