From 4b37928d3577e1b540b12d709e9b551fee3ccbd6 Mon Sep 17 00:00:00 2001 From: "Derald D. Woods" Date: Fri, 29 Dec 2017 10:37:32 -0600 Subject: ARM: dts: omap3-beagle{-xm}: Enable DM and devicetree for BeagleBoard This commit updates the configuration files needed to support OF_CONTROL on the OMAP3 BeagleBoard(s). --- include/configs/omap3_beagle.h | 145 +++++++++++++++-------------------------- 1 file changed, 53 insertions(+), 92 deletions(-) (limited to 'include/configs') diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index 394bfb7434..843e345ffd 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -14,57 +14,69 @@ #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ +#include + /* - * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM - * 64 bytes before this address should be set aside for u-boot.img's - * header. That is 0x800FFFC0--0x80100000 should not be used for any - * other needs. We use this rather than the inherited defines from - * ti_armv7_common.h for backwards compatibility. + * We are only ever GP parts and will utilize all of the "downloaded image" + * area in SRAM which starts at 0x40200000 and ends at 0x4020FFFF (64KB). */ -#define CONFIG_SYS_TEXT_BASE 0x80100000 -#define CONFIG_SPL_BSS_START_ADDR 0x80000000 -#define CONFIG_SPL_BSS_MAX_SIZE (512 << 10) /* 512 KB */ -#define CONFIG_SYS_SPL_MALLOC_START 0x80208000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 +#undef CONFIG_SPL_TEXT_BASE +#define CONFIG_SPL_TEXT_BASE 0x40200000 -#include +#define CONFIG_SPL_FRAMEWORK #define CONFIG_MISC_INIT_R +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG -#define CONFIG_REVISION_TAG 1 +/* NAND */ +#if defined(CONFIG_NAND) +#define CONFIG_SYS_FLASH_BASE NAND_BASE +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_PAGE_COUNT 64 +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) +#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS +#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ + 10, 11, 12, 13} +#define CONFIG_SYS_NAND_ECCSIZE 512 +#define CONFIG_SYS_NAND_ECCBYTES 3 +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 +#define CONFIG_ENV_IS_IN_NAND 1 +#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ +#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ +#define CONFIG_ENV_OFFSET 0x260000 +#define CONFIG_ENV_ADDR 0x260000 #define CONFIG_ENV_OVERWRITE +#define CONFIG_MTD_PARTITIONS /* required for UBI partition support */ +/* NAND: SPL falcon mode configs */ +#if defined(CONFIG_SPL_OS_BOOT) +#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000 +#endif /* CONFIG_SPL_OS_BOOT */ +#endif /* CONFIG_NAND */ -/* Status LED */ - -/* Enable Multi Bus support for I2C */ -#define CONFIG_I2C_MULTI_BUS 1 - -/* Probe all devices */ -#define CONFIG_SYS_I2C_NOPROBES {{0x0, 0x0}} - -/* USB */ +/* MUSB */ +#define CONFIG_USB_OMAP3 #define CONFIG_USB_MUSB_OMAP2PLUS #define CONFIG_USB_MUSB_PIO_ONLY -#define CONFIG_TWL4030_USB 1 +#define CONFIG_TWL4030_USB /* USB EHCI */ - #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 147 -/* commands to include */ - -#define CONFIG_VIDEO_OMAP3 /* DSS Support */ +/* Enable Multi Bus support for I2C */ +#define CONFIG_I2C_MULTI_BUS -/* - * TWL4030 - */ -#define CONFIG_TWL4030_LED 1 +/* DSS Support */ +#define CONFIG_VIDEO_OMAP3 -/* - * Board NAND Info. - */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ - /* devices */ +/* TWL4030 LED Support */ +#define CONFIG_TWL4030_LED #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) @@ -91,6 +103,7 @@ "run bootscript; " \ "else " \ "if run loadimage; then " \ + "run loadfdt;" \ "run mmcboot;" \ "fi;" \ "fi; " \ @@ -105,13 +118,8 @@ #include #define CONFIG_EXTRA_ENV_SETTINGS \ - "loadaddr=0x80200000\0" \ - "kernel_addr_r=0x80200000\0" \ - "rdaddr=0x81000000\0" \ - "initrd_addr_r=0x81000000\0" \ + DEFAULT_LINUX_BOOT_ENV \ "fdt_high=0xffffffff\0" \ - "fdtaddr=0x80f80000\0" \ - "fdt_addr_r=0x80f80000\0" \ "usbtty=cdc_acm\0" \ "bootfile=uImage\0" \ "ramdisk=ramdisk.gz\0" \ @@ -127,7 +135,7 @@ "defaultdisplay=dvi\0" \ "mmcdev=0\0" \ "mmcroot=/dev/mmcblk0p2 rw\0" \ - "mmcrootfstype=ext3 rootwait\0" \ + "mmcrootfstype=ext4 rootwait\0" \ "nandroot=ubi0:rootfs ubi.mtd=4\0" \ "nandrootfstype=ubifs\0" \ "ramroot=/dev/ram0 rw ramdisk_size=65536 initrd=0x81000000,64M\0" \ @@ -190,10 +198,10 @@ "bootscript=echo Running bootscript from mmc${mmcdev} ...; " \ "source ${loadaddr}\0" \ "loadfdt=run validatefdt; load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \ - "mmcboot=echo Booting from mmc ...; " \ + "mmcboot=echo Booting ${bootfile} with DT from mmc${mmcdev} ...; " \ "run mmcargs; " \ - "bootm ${loadaddr}\0" \ - "mmcbootz=echo Booting with DT from mmc${mmcdev} ...; " \ + "bootm ${loadaddr} - ${fdtaddr}\0" \ + "mmcbootz=echo Booting ${bootfile} with DT from mmc${mmcdev} ...; " \ "run mmcargs; " \ "bootz ${loadaddr} - ${fdtaddr}\0" \ "nandboot=echo Booting from nand ...; " \ @@ -209,51 +217,4 @@ "userbutton_nonxm=gpio input 7;\0" \ BOOTENV -/* - * OMAP3 has 12 GP timers, they can be driven by the system clock - * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). - * This rate is divided by a local divisor. - */ -#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ - -/* **** PISMO SUPPORT *** */ -#if defined(CONFIG_CMD_NAND) -#define CONFIG_SYS_FLASH_BASE NAND_BASE -#endif - -/* Monitor at start of flash */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP - -#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ -#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ - -#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ -#define CONFIG_ENV_OFFSET 0x260000 -#define CONFIG_ENV_ADDR 0x260000 - -/* Defines for SPL */ - -/* NAND boot config */ -#define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_PAGE_COUNT 64 -#define CONFIG_SYS_NAND_PAGE_SIZE 2048 -#define CONFIG_SYS_NAND_OOBSIZE 64 -#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) -#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 -#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ - 10, 11, 12, 13} -#define CONFIG_SYS_NAND_ECCSIZE 512 -#define CONFIG_SYS_NAND_ECCBYTES 3 -#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 -/* NAND: SPL falcon mode configs */ -#ifdef CONFIG_SPL_OS_BOOT -#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000 -#endif - #endif /* __CONFIG_H */ -- cgit